CN111710275A

CN111710275A - Display panel and display device

Info

Publication number: CN111710275A
Application number: CN202010535632.3A
Authority: CN
Inventors: 张蒙蒙; 周星耀; 李玥
Original assignee: Shanghai Tianma AM OLED Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2020-06-12
Filing date: 2020-06-12
Publication date: 2020-09-25
Anticipated expiration: 2040-06-12
Also published as: CN111710275B

Abstract

The invention discloses a display panel and a display device. The display panel comprises a multi-path selection circuit, a data signal source terminal and a gating signal output terminal, wherein the multi-path selection circuit comprises a plurality of switch circuit groups, the switch circuit comprises a gating signal receiving terminal and a data signal output terminal, the gating signal output terminal comprises a first gating signal output terminal and/or a second gating signal output terminal, the first gating signal output terminal and the second gating signal output terminal are located on different sides of the data signal source terminal, sub-pixels emitting light of the same color are electrically connected with the data signal output terminals in the same switch circuit group through data lines, and the gating signal receiving terminals of at least one switch circuit group are electrically connected with the first gating signal output terminal or the second gating signal output terminal. The display panel and the display device provided by the invention reduce the number of channels and solve the problem of vertical stripes.

Description

Display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.

Background

With the development and progress of display technology, people put higher demands on the appearance design of display devices, and narrow frames are the pursued targets. Due to the limitation of the frame space, a Demultiplexer (DEMUX) is usually used to decompose one signal channel into multiple signal channels, and time-division multiplex the output signal channels of the driver chip, thereby reducing the number of output pins of the driver chip.

However, the DEMUX circuit divides one signal channel into more signal channels, and therefore needs more clock control signals CKH, and because the clock control signals CKH of the existing DEMUX circuit all adopt bilateral driving, more signal channels of the clock control signals CKH are needed, and therefore, a wider Chip On Film (COF) is needed to bind signal lines of the CKH with a driving chip, so that the chip on film occupies a larger space, and is not beneficial to reducing the width of a frame.

Disclosure of Invention

The invention provides a display panel and a display device, which are used for reducing the number of signal channels and the width of a chip on film.

In a first aspect, an embodiment of the present invention provides a display panel, including a display area and a non-display area located on one side of the display area;

the display area comprises a plurality of sub-pixels arranged in an array and data lines connected with the sub-pixels in the same column; the non-display area comprises a multi-path selection circuit, N data signal source terminals and a plurality of gating signal output terminals; the multi-path selection circuit comprises N multi-path selection sub-circuits, the multi-path selection sub-circuits comprise M switch circuits, each switch circuit comprises a data signal receiving terminal, a strobe signal receiving terminal and a data signal output terminal, the M data signal receiving terminals in the same multi-path selection sub-circuit are electrically connected to the corresponding same data signal source terminal, the data signal output terminals are electrically connected to the corresponding data lines, the strobe signal receiving terminals are electrically connected to the corresponding strobe signal output terminals, and both N and M are positive integers larger than 1;

the strobe signal output terminals comprise a plurality of first-type strobe signal output terminals and/or a plurality of second-type strobe signal output terminals; the first type strobe signal output terminal and the second type strobe signal output terminal are located on different sides of the data signal source terminal along a first direction, and the first direction intersects with the extending direction of the data line;

the N-M switching circuits in the multi-path selection circuit comprise a plurality of switching circuit groups, and the sub-pixels emitting light with the same color are electrically connected with a plurality of data signal output terminals in the same switching circuit group through the data lines;

there is at least one set of the switching circuit groups in which the strobe signal receiving terminals are all electrically connected to the first type of strobe signal output terminal or are all electrically connected to the second type of strobe signal output terminal.

In a second aspect, an embodiment of the present invention further provides a display device, including any one of the display panels described in the first aspect.

The invention makes the sub-pixel emitting the same color light to be electrically connected with a plurality of data signal output terminals in the same switch circuit group through the data line, so that the switch circuit of each switch circuit group controls the sub-pixel emitting the same color light to display, and the gating signal receiving terminals in at least one group of switch circuit groups are electrically connected with the gating signal output terminal positioned at the same side of the data signal source terminal, thereby reducing the number of the gating signal output terminals, and making the time sequence of the sub-pixel emitting the same color light for receiving the display signal controlled by the gating signal output terminal positioned at the same side of the data signal source terminal, therefore, in the same switch circuit group, the delay difference of the gating signal received by the adjacent switch circuit is smaller, the conduction time difference of the adjacent switch circuit is smaller, and further the display brightness difference of the sub-pixel emitting the same color light is smaller, the vertical stripe phenomenon is avoided when the display panel displays a monochromatic picture.

Drawings

Fig. 1 is a schematic structural diagram of a conventional display panel;

FIG. 2 is a schematic structural diagram of another conventional display panel;

FIG. 3 is a schematic waveform diagram of a clock control signal of a conventional display panel;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a partial enlarged structure of a display panel according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 9 is a schematic partial enlarged structure view of another display panel according to an embodiment of the invention;

fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 11 is a schematic partial enlarged structural view of another display panel according to an embodiment of the invention;

fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 13 is a schematic partial enlarged structural view of another display panel according to an embodiment of the invention;

fig. 14 is an expanded view of a display panel according to an embodiment of the present invention;

fig. 15 is a partially enlarged schematic view of a display panel according to an embodiment of the invention;

fig. 16 is a side view of a display panel according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a conventional display panel. Referring to fig. 1, the display panel includes a display area 10 and a non-display area 11, the display area 10 includes a plurality of sub-pixels arranged in an array and data lines 12 connecting the sub-pixels in the same column, and the non-display area 11 includes a DEMUX circuit 13. Taking the DEMUX circuit 13 of M-by-1 as an example, the DEMUX circuit 13 connects each M Data lines 12 to one Data signal input terminal Data1, Data2 … …, or DataN, and one Data signal input terminal is connected to one output signal channel of the driver chip, and when the sub-pixels are charged by using the DEMUX circuit 13, the Data signals are loaded to the Data lines 12 in a time-sharing manner by sequentially loading clock control signals CKH1-CKHM, so as to charge M × N columns of sub-pixels through N signal input terminals, thereby reducing the output signal channels of the driver chip to M times. However, the clock control signals CKH1-CKHM are driven by two sides, and the clock control signals CKH1-CKHM need to occupy 2M signal channels, so a wider Chip On Film (COF) is needed to bind the signal lines of CKH1-CKHM with the driving chip, and the chip on film occupies a larger space.

Fig. 2 is a schematic structural diagram of another conventional display panel, and fig. 3 is a schematic waveform diagram of a clock control signal of a conventional display panel. Referring to fig. 2 and 3, the a position is left driven, the delay of the clock control signal is small, and thus, the on time of the a position is long; the position B is driven on the right side, and the delay of the clock control signal is larger, so that the conduction time of the position B is shorter; the C position is driven bilaterally, the delay of the clock control signal is centered, and therefore the on-time of the C position is centered. When the loading time of the clock control signal is short, the delay difference of the clock control signals at the A position, the B position and the C position is highlighted, so that when the A position, the B position and the C position control the sub-pixels of the same color to display, the problem of vertical stripes can occur when a single-color picture is displayed.

Based on the foregoing technical problem, an embodiment of the present invention provides a display panel, which includes a display area and a non-display area located on one side of the display area, wherein the display area includes a plurality of sub-pixels arranged in an array and a data line connected to the sub-pixels in the same column, and the non-display area includes a multi-path selection circuit, N data signal source terminals, and a plurality of gate signal output terminals. The multi-path selection circuit comprises N multi-path selection sub-circuits, each multi-path selection sub-circuit comprises M switch circuits, each switch circuit comprises a data signal receiving terminal, a gating signal receiving terminal and a data signal output terminal, M data signal receiving terminals in the same multi-path selection sub-circuit are electrically connected to the same corresponding data signal source terminal, the data signal output terminals are electrically connected to corresponding data lines, the gating signal receiving terminals are electrically connected to the corresponding gating signal output terminals, and N and M are positive integers greater than 1; the strobe signal output terminals include a plurality of first-type strobe signal output terminals and/or a plurality of second-type strobe signal output terminals. Along the first direction, first class strobe signal output terminal and second class strobe signal output terminal are located the different side of data signal source terminal, the extending direction of first direction and data line is crossing, N M switching circuit in the multichannel selection circuit includes a plurality of switching circuit group, the sub-pixel that sends same colour light passes through the data line and is connected with a plurality of data signal output terminal electricity in same switching circuit group, there is at least a set of switching circuit group, strobe signal receiving terminal in this switching circuit group all is connected with first class strobe signal output terminal electricity, perhaps, all is connected with second class strobe signal output terminal electricity.

By adopting the technical scheme, the sub-pixels emitting the same color light are electrically connected with the plurality of data signal output terminals in the same switch circuit group through the data lines, so that the switch circuit of each switch circuit group controls the sub-pixels emitting the same color light to display, and the gating signal receiving terminals in at least one group of switch circuit groups are electrically connected with the gating signal output terminals positioned on the same side of the data signal source terminal, thereby reducing the number of the gating signal output terminals, controlling the time sequence of the sub-pixels emitting the same color light for receiving the display signals by the gating signal output terminals positioned on the same side of the data signal source terminal, and further ensuring that the delay difference of the gating signals received by the adjacent switch circuits is smaller, the conduction time difference of the adjacent switch circuits is smaller, and the display brightness difference of the sub-pixels emitting the same color light is smaller, the vertical stripe phenomenon is avoided when the display panel displays a monochromatic picture.

The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention, fig. 5 is a schematic structural diagram of a partial enlargement of the display panel according to an embodiment of the present invention, as shown in fig. 4 and fig. 5, the display panel according to an embodiment of the present invention includes a display area 20 and a non-display area 21 located at one side of the display area 20, the display area 20 includes a plurality of sub-pixels 201 arranged in an array and data lines 202 connected to the sub-pixels 201 in the same column, the non-display area 21 includes a multiplexing circuit 30, N data signal source terminals 31 and a plurality of gate signal output terminals 32, the multiplexing circuit 30 includes N multiplexing sub-circuits 301, the multiplexing sub-circuit 301 includes M switching circuits 40, the switching circuit 40 includes a data signal receiving terminal 401, a gate signal receiving terminal 402 and a data signal output terminal 403, the M data signal receiving terminals 401 in the same multiplexing sub-circuit 301 are electrically connected to the corresponding same data signal source terminal 31, the data signal output terminals 403 are electrically connected to the corresponding data lines 202, and the strobe signal receiving terminals 402 are electrically connected to the corresponding strobe signal output terminals 32, where N and M are positive integers greater than 1. The strobe signal output terminal 32 includes a plurality of first type strobe signal output terminals 321 and/or a plurality of second type strobe signal output terminals 322, the first type strobe signal output terminals 321 and the second type strobe signal output terminals 322 are located on different sides of the data signal source terminal 31 along a first direction X, and the first direction X intersects with an extending direction of the data lines 202. The N × M switching circuits 40 in the multiplexing circuit 30 include a plurality of switching circuit groups, and the sub-pixels 201 emitting light of the same color are electrically connected to a plurality of data signal output terminals 403 in the same switching circuit group through the data lines 202. There are at least one set of switching circuit groups in which the strobe signal receiving terminals 402 are each electrically connected to the first-type strobe signal output terminal 321, or are each electrically connected to the second-type strobe signal output terminal 322.

Illustratively, as shown in fig. 4, taking the example that the non-display area 21 includes the multiplexing circuit 30, N data signal source terminals 31, and 5M/3 gate signal output terminals 32, the multiplexing circuit 30 includes N multiplexing sub-circuits 301, the multiplexing sub-circuit 301 includes M switching circuits 40, the switching circuit 40 includes a data signal receiving terminal 401, a gate signal receiving terminal 402, and a data signal output terminal 403, when a gate signal is applied to the gate signal receiving terminal 402 of the switching circuit 40, conduction is made between the data signal receiving terminal 401 and the data signal output terminal 403, otherwise, disconnection is made between the data signal receiving terminal 401 and the data signal output terminal 403. The M data signal receiving terminals 401 in the same multiplexing sub-circuit 301 are electrically connected to the corresponding same data signal source terminal 31, the data signal output terminals 403 are electrically connected to the corresponding data lines 202, and the strobe signal receiving terminals 402 are electrically connected to the corresponding strobe signal output terminals 32, so that, in the same multiplexing sub-circuit 301, when a strobe signal is applied to the strobe signal receiving terminal 402 of one switch circuit 40, conduction is established between the data line 202 and the data signal source terminal 31 that are electrically connected to the switch circuit 40.

Illustratively, as shown in fig. 4, when a gate signal CKH1 is applied to one gate signal output terminal 32, the Data signal receiving terminal 401 and the Data signal output terminal 403 are electrically connected in the switch circuit 40 electrically connected to the gate signal output terminal 32, and the Data line 202 electrically connected to the switch circuit 40 receives the display signal Data1 or DataN provided from the signal source terminal 31, thereby driving the sub-pixel 201 connected to the Data line 202 to display. And then applying the gating signals CKH2-CKHM to the corresponding gating signal output terminals 32 in sequence, and loading the display signals Data1-DataN to the Data lines 202 in a time-sharing manner, so as to drive the N × M columns of sub-pixels to display through the N Data signal source terminals 31, thereby greatly reducing the number of the Data signal source terminals 31 and being beneficial to reducing the width of the flip chip.

With continuing reference to fig. 4 and 5, illustratively, taking the example that the strobe signal output terminals 32 include M first-type strobe signal output terminals 321 and 2M/3 second-type strobe signal output terminals 322, along the first direction X, the first-type strobe signal output terminals 321 are located on the left side of the data signal source terminal 31, and the second-type strobe signal output terminals 322 are located on the right side of the data signal source terminal 31. The 24 switching circuits 40 in the multiplexing circuit 30 are divided into a plurality of switching circuit groups, and the sub-pixels 201 emitting the same color light are electrically connected to a plurality of data signal output terminals 403 in the same switching circuit group via the data lines 202. The gate signal receiving terminals 402 of at least one group of switching circuits are electrically connected to the first type gate signal output terminal 321, or are electrically connected to the second type gate signal output terminal 322. Wherein the switch circuit 40 of each switch circuit group controls the sub-pixels 201 emitting the same color light to display, for example, if the switching circuits 40 of one switching circuit group control the red sub-pixel to display, and the gate signal receiving terminals 402 of the switching circuit group are all electrically connected to the first type gate signal output terminal 321, the timing at which the red subpixel receives the display signal Data1 or Data2 is controlled by the first-type strobe signal output terminal 321, since the first-type strobe signal output terminals 321 are all located on the left side of the data signal source terminal 31, in the same switch circuit group, the delay difference of the gate signals received by the adjacent switch circuits 40 is small, the conduction time difference of the adjacent switch circuits 40 is small, therefore, the display brightness difference of the adjacent red sub-pixels is small, and the phenomenon of vertical stripes when the display panel displays a red picture is avoided. In addition, since the gate signal receiving terminal 402 of the group of switch circuits is electrically connected to only the first type gate signal output terminal 321, compared with the prior art in which the group of switch circuits is electrically connected to both the first type gate signal output terminal 321 and the second type gate signal output terminal 322, the group of switch circuits reduces half of the gate signal output terminals 32, thereby being beneficial to reducing the width of the chip on film.

It should be noted that the display panel shown in fig. 4 and 5 is only an example, and in other embodiments, the first type strobe signal output terminal 321 may be located on the right side of the data signal source terminal 31, and the second type strobe signal output terminal 322 may be located on the left side of the data signal source terminal 31, as long as the first type strobe signal output terminal 321 and the second type strobe signal output terminal 322 are located on different sides of the data signal source terminal 31. In addition, the light emitting color and the arrangement mode of the sub-pixels 201, the number of columns of the sub-pixels 201, the numerical values of M and N, and the like can be set according to actual requirements.

In the display panel provided by the embodiment of the present invention, the sub-pixels 201 emitting the same color light are electrically connected to the plurality of data signal output terminals 403 in the same switch circuit group through the data lines 202, so that the switch circuits 40 of each switch circuit group control the sub-pixels 201 emitting the same color light to display, and the gate signal receiving terminals 402 of at least one switch circuit group are electrically connected to the gate signal output terminals 32 located on the same side of the data signal source terminal 31, so as to reduce the number of the gate signal output terminals 32, and to control the timings of receiving the display signals by the sub-pixels 201 emitting the same color light by the gate signal output terminals 32 located on the same side of the data signal source terminal 31, so that in the same switch circuit group, the delay difference of the gate signals received by the adjacent switch circuits 40 is small, and the conduction time difference of the adjacent switch circuits 40 is small, therefore, the display brightness difference of the adjacent sub-pixels 201 emitting the same color light is small, and the vertical stripe phenomenon when the display panel displays a single-color picture is avoided.

With continued reference to fig. 4 and 5, optionally, the sub-pixel 201 includes a first sub-pixel 51 emitting light of a first color, a second sub-pixel 52 emitting light of a second color, and a third sub-pixel 53 emitting light of a third color, the plurality of sub-pixels 201 arranged in an array includes a first sub-pixel column R1, a second sub-pixel column G1, and a third sub-pixel column B1, the first sub-pixel column R1 includes the first sub-pixel 51, the second sub-pixel column G1 includes the second sub-pixel 52, and the third sub-pixel column B1 includes the third sub-pixel 53. The switching circuit group includes a first switching circuit group, the first sub-pixel column R1 is electrically connected to the data signal output terminal 403 in the first switch circuit group through the data line 202, the second sub-pixel column G1 is electrically connected to the data signal output terminal 403 in the second switch circuit group through the data line 202, the third sub-pixel column B1 is electrically connected to the data signal output terminal 403 in the third switch circuit group through the data line, the gate signal receiving terminals 402 in the first switch circuit group are electrically connected to the first type gate signal output terminal 321 or the second type gate signal output terminal 322, the gate signal receiving terminals 402 in the second switch circuit group are electrically connected to the first type gate signal output terminal 321 and the second type gate signal output terminal 322, and the gate signal receiving terminals 402 in the third switch circuit group are electrically connected to the first type gate signal output terminal 321 and the second type gate signal output terminal 322.

For example, as shown in fig. 4 and 5, taking the first color light as red, the second color light as green, and the third color light as blue as an example, the sub-pixels 201 in the first sub-pixel column R1 are all red sub-pixels, the sub-pixels 201 in the second sub-pixel column G1 are all green sub-pixels, and the sub-pixels 201 in the third sub-pixel column B1 are all blue sub-pixels. Since the first sub-pixel column R1 is electrically connected to the data signal output terminal 403 in the first switching circuit group through the data line 202, the second sub-pixel column G1 is electrically connected to the data signal output terminal 403 in the second switching circuit group through the data line 202, and the third sub-pixel column B1 is electrically connected to the data signal output terminal 403 in the third switching circuit group through the data line, the switching circuit 40 in the first switching circuit group controls the red sub-pixel to display, the switching circuit 40 in the second switching circuit group controls the green sub-pixel to display, and the switching circuit 40 in the third switching circuit group controls the blue sub-pixel to display. The gate signal receiving terminals 402 in the first switch circuit group are electrically connected to the first-type gate signal output terminals 321 or the second-type gate signal output terminals 322, so that the timings of the red sub-pixels for receiving the display signals are controlled by the gate signal output terminals 32 located on the same side of the data signal source terminals 31, thereby preventing the display panel from generating the vertical stripe phenomenon when displaying the red image.

The gating signal receiving terminals 402 in the second switching circuit group are electrically connected with the first gating signal output terminal 321 and the second gating signal output terminal 322, and the gating signal receiving terminals 402 in the third switching circuit group are electrically connected with the first gating signal output terminal 321 and the second gating signal output terminal 322, so that the time sequences of the green sub-pixels and the blue sub-pixels for receiving the display signals are controlled by the gating signal output terminals 32 positioned at two sides of the data signal source terminal 31, the display brightness difference of the adjacent green sub-pixels is small, the display brightness difference of the adjacent blue sub-pixels is small, and the vertical stripe phenomenon when the display panel displays a single-color picture is avoided. In addition, the timing sequence of the green sub-pixel and the blue sub-pixel for receiving the display signal is controlled by the gating signal output terminals 32 positioned at two sides of the data signal source terminal 31, which is favorable for reducing the voltage drop of the gating signal on the wiring and reducing the delay of the gating signal.

Taking the display panel shown in fig. 4 and 5 as an example, the first sub-pixel 51 is controlled by the gate signal output terminal 32 located on the same side of the data signal source terminal 31 to display, and the second sub-pixel 52 and the third sub-pixel 53 are controlled by the gate signal output terminals 32 located on both sides of the data signal source terminal 31 to display, so that when a single-color image is displayed on the display panel, a vertical stripe phenomenon occurs, and at the same time, only 5M/3 gate signal output terminals 32 are used, which reduces M/3 gate signal output terminals 32 compared with a scheme that both adopt bilateral driving, and is beneficial to reducing the width of the flip chip film.

It should be noted that the first color light, the second color light and the third color light described in the embodiments of the present invention are not limited to red, green and blue, and those skilled in the art can design the first color light, the second color light and the third color light according to actual requirements.

Fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and as shown in fig. 5 and fig. 6, optionally, the sub-pixel 201 includes a first sub-pixel 51 emitting a first color light, a second sub-pixel 52 emitting a second color light, and a third sub-pixel 53 emitting a third color light. The plurality of sub-pixels 201 arranged in an array includes a first sub-pixel column R1, a second sub-pixel column G1, and a third sub-pixel column B1, the first sub-pixel column R1 includes a first sub-pixel 51, the second sub-pixel column G1 includes a second sub-pixel 52, and the third sub-pixel column B1 includes a third sub-pixel 53. The switch circuit group includes a first switch circuit group, a second switch circuit group, and a third switch circuit group, the first sub-pixel column R1 is electrically connected to the data signal output terminal 403 in the first switch circuit group through the data line 202, the second sub-pixel column G1 is electrically connected to the data signal output terminal 403 in the second switch circuit group through the data line 202, and the third sub-pixel column B1 is electrically connected to the data signal output terminal 403 in the third switch circuit group through the data line 202. The gate signal receiving terminals 402 in the first switching circuit group are electrically connected to the first-type gate signal output terminal 321 or the second-type gate signal output terminal 322, the gate signal receiving terminals 402 in the second switching circuit group are electrically connected to the first-type gate signal output terminal 321 or the second-type gate signal output terminal 322, and the gate signal receiving terminals 402 in the third switching circuit group are electrically connected to the first-type gate signal output terminal 321 and the second-type gate signal output terminal 322.

For example, as shown in fig. 5 and 6, taking the first color light as red, the second color light as green, and the third color light as blue as an example, the sub-pixels 201 in the first sub-pixel column R1 are all red sub-pixels, the sub-pixels 201 in the second sub-pixel column G1 are all green sub-pixels, and the sub-pixels 201 in the third sub-pixel column B1 are all blue sub-pixels. Since the first sub-pixel column R1 is electrically connected to the data signal output terminal 403 in the first switching circuit group through the data line 202, the second sub-pixel column G1 is electrically connected to the data signal output terminal 403 in the second switching circuit group through the data line 202, and the third sub-pixel column B1 is electrically connected to the data signal output terminal 403 in the third switching circuit group through the data line, the switching circuit 40 in the first switching circuit group controls the red sub-pixel to display, the switching circuit 40 in the second switching circuit group controls the green sub-pixel to display, and the switching circuit 40 in the third switching circuit group controls the blue sub-pixel to display. The strobe signal receiving terminals 402 in the first switching circuit group are electrically connected with the first-type strobe signal output terminals 321 or the second-type strobe signal output terminals 322, so that the timing of receiving the display signals by the red sub-pixels is controlled by the strobe signal output terminals 32 on the same side of the data signal source terminals 31; the strobe signal receiving terminal 402 of the second switch circuit group is electrically connected to the first strobe signal output terminal 321 or the second strobe signal output terminal 322, so that the timing of receiving the display signal by the green sub-pixel is controlled by the strobe signal output terminal 32 on the same side of the data signal source terminal 31, thereby avoiding the vertical stripe phenomenon when the display panel displays the monochrome picture.

By arranging the gating signal receiving terminal 402 in the third switching circuit group to be electrically connected with the first gating signal output terminal 321 and the second gating signal output terminal 322, the time sequence of the blue sub-pixel for receiving the display signal is controlled by the gating signal output terminals 32 at the two sides of the data signal source terminal 31, so that the display brightness difference of the adjacent blue sub-pixels is small, and the vertical stripe phenomenon is avoided when the display panel displays a blue picture. In addition, the time sequence of receiving the display signal by the blue sub-pixel is controlled by the gating signal output terminals 32 positioned at two sides of the data signal source terminal 31, which is favorable for reducing the voltage drop of the gating signal on the routing and reducing the delay of the gating signal.

Taking the display panel shown in fig. 5 and 6 as an example, the first sub-pixel 51 is controlled by the gate signal output terminal 32 located on the same side of the data signal source terminal 31 to display, the second sub-pixel 52 is controlled by the gate signal output terminal 32 located on the same side of the data signal source terminal 31 to display, and the third sub-pixel 53 is controlled by the gate signal output terminals 32 located on both sides of the data signal source terminal 31 to display, so that the vertical stripe phenomenon occurring when the display panel displays a monochrome picture is avoided, and at the same time, only 4M/3 gate signal output terminals 32 are used, compared with a scheme that both sides are driven, 2M/3 gate signal output terminals 32 are reduced, which is beneficial to reducing the width of the flip chip film.

With continued reference to fig. 6, optionally, the strobe signal receiving terminals 402 in the first switching circuit group are all electrically connected to the first-type strobe signal output terminal 321, and the strobe signal receiving terminals 402 in the second switching circuit group are all electrically connected to the second-type strobe signal output terminal 322; alternatively, the gate signal receiving terminals 402 in the first switching circuit group are all electrically connected to the second type gate signal output terminal 322, and the gate signal receiving terminals 402 in the second switching circuit group are all electrically connected to the first type gate signal output terminal 321.

The gating signal on the gating signal output terminal 32 is usually provided by the driving chip, and since the pins on the driving chip are of a symmetrical structure, when only the pin on one side of the driving chip is used, the corresponding pin on the other side of the driving chip is suspended, so that the utilization rate of the pin on the driving chip is reduced. With reference to fig. 6, in the embodiment of the present invention, the gate signal output terminals 32 electrically connected to the gate signal receiving terminals 402 in the first switch circuit group and the gate signal output terminals 32 electrically connected to the gate signal receiving terminals 402 in the second switch circuit group are respectively disposed at different sides of the data signal source terminal 31, so that the number of the gate signal output terminals 32 at two sides of the data signal source terminal 31 is equivalent, thereby reducing the number of pins hanging on the driving chip and improving the utilization rate of the pins on the driving chip.

Fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 5 and 7, optionally, the sub-pixel 201 includes a first sub-pixel 51 emitting a first color light, a second sub-pixel 52 emitting a second color light, and a third sub-pixel 53 emitting a third color light, the plurality of sub-pixels 201 arranged in an array are divided into a first sub-pixel column R1, a second sub-pixel column G1, and a third sub-pixel column B1, the first sub-pixel column R1 includes the first sub-pixel 51, the second sub-pixel column G1 includes the second sub-pixel 52, and the third sub-pixel column B1 includes the third sub-pixel 53. The switch circuit group comprises a first switch circuit group, a second switch circuit group and a third switch circuit group; the first sub-pixel column R1 is electrically connected to the data signal output terminals 403 in the first switching circuit group through the data lines 202, the second sub-pixel column G1 is electrically connected to the data signal output terminals 403 in the second switching circuit group through the data lines 202, and the third sub-pixel column B1 is electrically connected to the data signal output terminals 403 in the third switching circuit group through the data lines 202. The gate signal receiving terminals 402 in the first switching circuit group are electrically connected to the first-type gate signal output terminal 321 or the second-type gate signal output terminal 322, the gate signal receiving terminals 402 in the second switching circuit group are electrically connected to the first-type gate signal output terminal 321 or the second-type gate signal output terminal 322, and the gate signal receiving terminals 402 in the third switching circuit group are electrically connected to the first-type gate signal output terminal 321 or the second-type gate signal output terminal 322.

For example, as shown in fig. 5 and 7, taking the first color light as red, the second color light as green, and the third color light as blue as examples, the sub-pixels 201 in the first sub-pixel column R1 are all red sub-pixels, the sub-pixels 201 in the second sub-pixel column G1 are all green sub-pixels, and the sub-pixels 201 in the third sub-pixel column B1 are all blue sub-pixels. Since the first sub-pixel column R1 is electrically connected to the data signal output terminal 403 in the first switching circuit group through the data line 202, the second sub-pixel column G1 is electrically connected to the data signal output terminal 403 in the second switching circuit group through the data line 202, and the third sub-pixel column B1 is electrically connected to the data signal output terminal 403 in the third switching circuit group through the data line, the switching circuit 40 in the first switching circuit group controls the red sub-pixel to display, the switching circuit 40 in the second switching circuit group controls the green sub-pixel to display, and the switching circuit 40 in the third switching circuit group controls the blue sub-pixel to display. Meanwhile, the gating signal receiving terminal 402 in the first switching circuit group, the gating signal receiving terminal 402 in the second switching circuit group and the gating signal receiving terminal 402 in the third switching circuit group are respectively and electrically connected with the first gating signal output terminal 321 or the second gating signal output terminal 322, so that the time sequences of receiving display signals by the red sub-pixel, the green sub-pixel and the blue sub-pixel are respectively controlled by the gating signal output terminal 32 on the same side of the data signal source terminal 31, and the vertical stripe phenomenon of the display panel during display is avoided.

Taking the display panel shown in fig. 5 and 6 as an example, the first sub-pixel 51, the second sub-pixel 52, and the third sub-pixel 53 are respectively controlled by the gating signal output terminals 32 located on the same side as the data signal source terminals 31 to display, so that the vertical stripe phenomenon occurring during the display of the display panel is avoided, and at the same time, only M gating signal output terminals 32 are used, which reduces half of the gating signal output terminals 32 compared with the scheme that all the gating signal output terminals are driven at two sides, and is beneficial to reducing the width of the flip chip.

With reference to fig. 6, optionally, in the first, second and third switching circuit groups, the gating signal receiving terminals 402 in at least one switching circuit group are electrically connected to the first type gating signal output terminal 321, and the gating signal receiving terminals 402 in at least one switching circuit group are electrically connected to the second type gating signal output terminal 322.

The gating signal on the gating signal output terminal 32 is usually provided by the driving chip, and since the pins on the driving chip are of a symmetrical structure, when only the pin on one side of the driving chip is used, the corresponding pin on the other side of the driving chip is suspended, so that the utilization rate of the pin on the driving chip is reduced. By arranging that the gating signal receiving terminals 402 in at least one group of switch circuit groups are electrically connected with the first gating signal output terminal 321, and the gating signal receiving terminals 402 in at least one group of switch circuit groups are electrically connected with the second gating signal output terminal 322, the difference of the number of the gating signal output terminals 32 on two sides of the data signal source terminal 31 is reduced, thereby reducing the suspended pins on the driving chip and improving the utilization rate of the pins on the driving chip.

Fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 9 is a schematic partial enlarged structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 8 and fig. 9, optionally, the sub-pixels 201 include a first sub-pixel 51 emitting light of a first color, a second sub-pixel 52 emitting light of a second color, and a third sub-pixel 53 emitting light of a third color, the plurality of sub-pixels 201 arranged in an array include a fourth sub-pixel column BR and a fifth sub-pixel column G2, the fourth sub-pixel column BR includes the first sub-pixel 51 and the second sub-pixel 52, and the fifth sub-pixel column G2 includes the third sub-pixel 53. The switch circuit group comprises a fourth switch circuit group and a fifth switch circuit group, the fourth sub-pixel column BR is electrically connected with the data signal output terminal 403 in the fourth switch circuit group through the data line 202, and the fifth sub-pixel column G2 is electrically connected with the data signal output terminal 403 in the fifth switch circuit group through the data line 202; the gate signal receiving terminals 402 in the fourth switch circuit group are all electrically connected with the first type gate signal output terminal 321, or are all electrically connected with the second type gate signal output terminal 322, and the gate signal receiving terminals 402 in the fifth switch circuit group are all electrically connected with the first type gate signal output terminal 321, and/or are all electrically connected with the second type gate signal output terminal 322, or the gate signal receiving terminals 402 in the fourth switch circuit group are all electrically connected with the first type gate signal output terminal 321, and/or are all electrically connected with the second type gate signal output terminal 322, and the gate signal receiving terminals 402 in the fifth switch circuit group are all electrically connected with the first type gate signal output terminal 321, or are all electrically connected with the second type gate signal output terminal 322.

For example, as shown in fig. 8 and 9, taking the first color light as red, the second color light as blue, and the third color light as green as an example, the fourth sub-pixel column BR includes red sub-pixels and blue sub-pixels, and the sub-pixels 201 in the fifth sub-pixel column G2 are all green sub-pixels. The arrangement of the Sub-pixels 201 is as shown in fig. 9, and the display panel adopts a Sub Pixel Rendering (SPR) technique, so as to improve the PPI of the display panel.

Since the fourth sub-pixel column BR is electrically connected to the data signal output terminal 403 in the fourth switching circuit group through the data line 202, and the fifth sub-pixel column G2 is electrically connected to the data signal output terminal 403 in the fifth switching circuit group through the data line 202, the switching circuit 40 in the fourth switching circuit group controls the red sub-pixel and the blue sub-pixel to display, and the switching circuit 40 in the fifth switching circuit group controls the green sub-pixel to display. At least one of the fourth switch circuit group and the fifth switch circuit group is electrically connected to the first strobe signal output terminal 321 or the second strobe signal output terminal 322, so that the red sub-pixel and the blue sub-pixel, and/or the timing sequence of the green sub-pixel for receiving the display signal is controlled by the strobe signal output terminal 32 on the same side of the data signal source terminal 31, thereby preventing the display panel from generating vertical stripes during displaying.

Taking the display panel shown in fig. 8 and 9 as an example, the gating signal receiving terminals 402 in the fourth switching circuit group are electrically connected to the first-type gating signal output terminals 321, and the gating signal receiving terminals 402 in the fifth switching circuit group are electrically connected to the second-type gating signal output terminals 322, so that the red sub-pixel and the blue sub-pixel are controlled by the gating signal output terminals 32 located on the same side of the data signal source terminal 31, and the green sub-pixel is controlled by the gating signal output terminals 32 located on the same side of the data signal source terminal 31, thereby avoiding the occurrence of the vertical stripe phenomenon when the display panel displays, and simultaneously using only M gating signal output terminals 32, compared with the scheme that both sides are driven, reducing half of the gating signal output terminals 32, and being beneficial to reducing the width of the flip chip.

With continued reference to fig. 8 and 9, optionally, the plurality of sub-pixels 201 arranged in an array includes a plurality of sub-pixel groups 60, each sub-pixel group 60 includes a fourth sub-pixel column BR1 and a fifth sub-pixel column G2, and the fourth sub-pixel column BR includes a fourth sub-pixel column BR1 and a fourth sub-pixel column BR2, which are sequentially arranged along the first direction X, the fourth sub-pixel column BR1, the fifth sub-pixel column G2 and the fourth sub-pixel column BR 2.

The pixel arrangement shown in fig. 9 is helpful to achieve higher resolution with the same number of sub-pixels 201. It should be noted that the display panel shown in fig. 9 is only an example, and those skilled in the art can set the arrangement of the sub-pixels 201 according to actual requirements.

Optionally, M/3 ═ k, where k is a positive integer greater than or equal to 1.

On the basis of the pixel arrangement shown in fig. 4-9, the M switching circuits are set to be multiples of 3, so that the sub-pixels emitting light of the same color can be controlled by the switching circuits 40 in the same switching circuit group.

Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 11 is a schematic partial enlarged structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 10 and fig. 11, exemplarily, the non-display area 21 includes a multiplexing circuit 30, N data signal source terminals 31, and M strobe signal output terminals 32, the multiplexing circuit 30 includes N multiplexing sub-circuits 301, and the multiplexing sub-circuit 301 includes M switch circuits 40, where M is a multiple of 3. When a gate signal CKH1 is applied to one gate signal output terminal 32, the Data signal receiving terminal 401 and the Data signal output terminal 403 are electrically connected in the switch circuit 40 electrically connected to the gate signal output terminal 32, and the Data line 202 electrically connected to the switch circuit 40 receives the display signals Data1, Data2 or DataN supplied from the signal source terminal 31, thereby driving the sub-pixel 201 connected to the Data line 202 to display. And then applying the gate signals CKH2-CKHM to the corresponding gate signal output terminals 32 in sequence, and loading the display signals Data1-DataN to the Data lines 202 in a time-sharing manner, so as to drive M × N columns of sub-pixels to display through the N Data signal source terminals 31, thereby reducing the number of the Data signal source terminals 31 and being beneficial to reducing the width of the flip chip.

Continuing to refer to fig. 10, exemplarily, taking the example that the strobe signal output terminals 32 include 2M/3 first-type strobe signal output terminals 321 and M/3 second-type strobe signal output terminals 322, along the first direction X, the first-type strobe signal output terminals 321 are located on the left side of the data signal source terminal 31, and the second-type strobe signal output terminals 322 are located on the right side of the data signal source terminal 31. The sub-pixels 201 emitting the same color light are electrically connected with a plurality of data signal output terminals 403 in the same switch circuit group through the data lines 202, and the gating signal receiving terminals 402 of each switch circuit group are electrically connected with the first gating signal output terminals 321 or the second gating signal output terminals 322, so that the vertical stripe phenomenon of the display panel during display is avoided. In addition, since the gate signal receiving terminal 402 of each switching circuit group is electrically connected to only the gate signal output terminal 32 located on the same side as the data signal source terminal 31, compared with the schemes that all the gate signal receiving terminals are driven at two sides, half of the gate signal output terminals 32 are reduced, thereby being beneficial to reducing the width of the chip on film.

It should be noted that the number M of the switch circuits is not limited to be a multiple of 3, and in other embodiments, M may also be another value, for example, M may also be a multiple of 2, and those skilled in the art may set M according to the pixel arrangement. Similarly, the number of columns of the sub-pixels 202, the number N of data signal source terminals, and the like may also be set according to actual requirements.

Fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 13 is a schematic partial enlarged structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 12 and fig. 13, a sub-pixel 201 includes a first sub-pixel 51 emitting light of a first color, a second sub-pixel 52 emitting light of a second color, and a third sub-pixel 53 emitting light of a third color, and in the plurality of sub-pixels 201 arranged in an array, at least one column of sub-pixels 201 includes the first sub-pixel 51, the second sub-pixel 52, and the third sub-pixel 53. The switch circuit group comprises a sixth switch circuit group, and the first sub-pixel 51, the second sub-pixel 52 and the third sub-pixel 53 are all electrically connected with the data signal output terminal 403 in the sixth switch circuit group through the data line 202. The gate signal receiving terminals 402 in the sixth switching circuit group are all electrically connected to the first-type gate signal output terminal 321, or are all electrically connected to the second-type gate signal output terminal 322.

Illustratively, as shown in fig. 12 and 13, each column of sub-pixels 201 includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, taking the first color light as red, the second color light as green, and the third color light as blue as an example. Since the first sub-pixel 51, the second sub-pixel 52 and the third sub-pixel 53 are all electrically connected to the data signal output terminal 403 in the sixth switching circuit group through the data line 202, the switching circuit 40 in the sixth switching circuit group controls the red sub-pixel, the green sub-pixel and the blue sub-pixel to display. By arranging that the gating signal receiving terminal 402 in the sixth switching circuit group is electrically connected with the first-type gating signal output terminal 321 or the second-type gating signal output terminal 322, the time sequence of receiving the display signals by the red sub-pixel, the green sub-pixel and the blue sub-pixel is controlled by the gating signal output terminal 32 which is positioned on the same side of the data signal source terminal 31, so that the vertical stripe phenomenon is avoided when the display panel displays.

Taking the display panel shown in fig. 12 and 13 as an example, the first sub-pixel 51, the second sub-pixel 52 and the third sub-pixel 53 are all controlled by the gating signal output terminal 32 located on the same side as the data signal source terminal 31 to display, so that when a monochrome picture is displayed on the display panel, a vertical stripe phenomenon is avoided, and at the same time, only M gating signal output terminals 32 are used, which reduces half of the gating signal output terminals 32 compared with a scheme that all adopt bilateral driving, and is beneficial to reducing the width of the flip chip.

Fig. 14 is an expanded view of a display panel according to an embodiment of the present invention, fig. 15 is a partially enlarged schematic view of the display panel according to the embodiment of the present invention, and fig. 16 is a side view of the display panel according to the embodiment of the present invention, as shown in fig. 14 to 16, the display panel according to the embodiment of the present invention further includes a flip chip 70 and a driving chip 71 disposed on the flip chip 70. The chip on film 70 includes N data signal connection terminals 701, and further includes a plurality of first-type gate signal connection terminals 702 and/or a plurality of second-type gate signal connection terminals 703, along the first direction X, the first-type gate signal connection terminals 702 are located at the first sides 81 of the N data signal connection terminals 701, and the second-type gate signal connection terminals 703 are located at the second sides 82 of the N data signal connection terminals 701. The driving chip 71 includes N data signal pins 711, and further includes a plurality of first type strobe signal pins 712 and/or a plurality of second type strobe signal pins 713, and along the first direction X, the first type strobe signal pins 712 are located at the first sides 81 of the N data signal pins 711, and the second type strobe signal pins 713 are located at the second sides 82 of the N data signal pins 711. The N data signal pins 711 and the N data signal connection terminals 701 are electrically connected in a one-to-one correspondence, the plurality of first-type gate signal pins 712 and the plurality of first-type gate signal connection terminals 702 are electrically connected in a one-to-one correspondence, and the plurality of second-type gate signal pins 713 and the plurality of second-type gate signal connection terminals 703 are electrically connected in a one-to-one correspondence. The N data signal connection terminals 701 are connected to the N data signal source terminals 31 in a one-to-one correspondence, the plurality of first-type strobe signal connection terminals 702 are connected to the plurality of first-type strobe signal output terminals 321 in a one-to-one correspondence, and the plurality of second-type strobe signal connection terminals 703 are connected to the plurality of second-type strobe signal output terminals 322 in a one-to-one correspondence.

The driving chip 71 is disposed on the chip on film 70, the data signal pins 711 of the driving chip 71 are correspondingly connected to the data signal source terminals 31 through the data signal connection terminals 701 of the chip on film 70, the first-type gating signal pins 712 of the driving chip 71 are correspondingly connected to the first-type gating signal output terminals 321 through the first-type gating signal connection terminals 702 of the chip on film 70, and the second-type gating signal pins 713 of the driving chip 71 are correspondingly connected to the second-type gating signal output terminals 322 through the second-type gating signal connection terminals 703 of the chip on film 70, so that the driving chip 71 provides the gating signals and the display signals for the multi-channel selection circuit. The driving chip 71 can be bent to the back of the display panel through the chip on film 70, so as to reduce the frame width of the display panel, which is beneficial to realizing full-screen display.

The embodiment of the invention provides a plurality of display panels according to the pixel arrangement mode, the sub-pixels 201 emitting the same color light are arranged and electrically connected with a plurality of data signal output terminals 403 in the same switch circuit group through the data lines 202, so that the switch circuit 40 of each switch circuit group controls the sub-pixels 201 emitting the same color light to display, and the gating signal receiving terminals 402 in at least one group of switch circuit groups are electrically connected with the gating signal output terminals 32 on the same side of the data signal source terminal 31, thereby reducing the number of the gating signal output terminals 32, further reducing the number of the first type gating signal connecting terminals 702 and the second type gating signal connecting terminals 703 on the chip on film 70, and being beneficial to reducing the width of the chip on film 70 and the area of a frame.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, fig. 17 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and as shown in fig. 17, the display device 90 includes a display panel 91 according to any embodiment of the present invention, so that the display device 90 provided in the embodiment of the present invention has the technical effects of the technical solutions in any embodiment, and explanations of structures and terms that are the same as or corresponding to the embodiments are not repeated herein. The display device 90 provided in the embodiment of the present invention may be a mobile phone shown in fig. 17, and may also be any electronic product with a display function, including but not limited to the following categories: the touch screen display system comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited in this respect.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel includes a display area and a non-display area located on one side of the display area;

2. The display panel according to claim 1, wherein the sub-pixels include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light;

the plurality of sub-pixels arranged in the array comprise a first sub-pixel column, a second sub-pixel column and a third sub-pixel column; the first sub-pixel column comprises the first sub-pixel, the second sub-pixel column comprises the second sub-pixel, and the third sub-pixel column comprises the third sub-pixel;

the switch circuit group comprises a first switch circuit group, a second switch circuit group and a third switch circuit group;

the first sub-pixel column is electrically connected to the data signal output terminals in the first switching circuit group through the data lines, the second sub-pixel column is electrically connected to the data signal output terminals in the second switching circuit group through the data lines, and the third sub-pixel column is electrically connected to the data signal output terminals in the third switching circuit group through the data lines;

the gate signal receiving terminals in the first switch circuit group are electrically connected with the first type of gate signal output terminal or the second type of gate signal output terminal, the gate signal receiving terminals in the second switch circuit group are electrically connected with the first type of gate signal output terminal and the second type of gate signal output terminal, and the gate signal receiving terminals in the third switch circuit group are electrically connected with the first type of gate signal output terminal and the second type of gate signal output terminal.

3. The display panel according to claim 1, wherein the sub-pixels include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light;

the gate signal receiving terminals in the first switch circuit group are electrically connected with the first type of gate signal output terminal or the second type of gate signal output terminal, the gate signal receiving terminals in the second switch circuit group are electrically connected with the first type of gate signal output terminal or the second type of gate signal output terminal, and the gate signal receiving terminals in the third switch circuit group are electrically connected with the first type of gate signal output terminal and the second type of gate signal output terminal.

4. The display panel according to claim 3, wherein the gate signal receiving terminals in the first switch circuit group are each electrically connected to the first type of gate signal output terminal, and the gate signal receiving terminals in the second switch circuit group are each electrically connected to the second type of gate signal output terminal; or, the gating signal receiving terminals in the first switch circuit group are all electrically connected with the second type gating signal output terminal, and the gating signal receiving terminals in the second switch circuit group are all electrically connected with the first type gating signal output terminal.

5. The display panel according to claim 2, wherein the sub-pixels include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light;

the plurality of sub-pixels arranged in the array are divided into a first sub-pixel column, a second sub-pixel column and a third sub-pixel column; the first sub-pixel column comprises the first sub-pixel, the second sub-pixel column comprises the second sub-pixel, and the third sub-pixel column comprises the third sub-pixel;

the gating signal receiving terminals in the first switching circuit group are electrically connected with the first type gating signal output terminal or the second type gating signal output terminal, and the gating signal receiving terminals in the second switching circuit group are electrically connected with the first type gating signal output terminal or the second type gating signal output terminal; the gate signal receiving terminals in the third switching circuit group are electrically connected to the first type gate signal output terminal or the second type gate signal output terminal.

6. The display panel according to claim 5, wherein the gate signal receiving terminals in at least one of the first, second, and third switching circuit groups are electrically connected to the first-type gate signal output terminals, and the gate signal receiving terminals in at least one of the switching circuit groups are electrically connected to the second-type gate signal output terminals.

7. The display panel according to claim 1, wherein the sub-pixels include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light;

the plurality of sub-pixels arranged in the array comprise a fourth sub-pixel column and a fifth sub-pixel column;

the fourth sub-pixel column comprises the first sub-pixel and the second sub-pixel, and the fifth sub-pixel column comprises the third sub-pixel;

the switch circuit group comprises a fourth switch circuit group and a fifth switch circuit group;

the fourth sub-pixel column is electrically connected to the data signal output terminals in the fourth switching circuit group through the data line, and the fifth sub-pixel column is electrically connected to the data signal output terminals in the fifth switching circuit group through the data line;

gating signal receiving terminals in the fourth switch circuit group are electrically connected with the first gating signal output terminal or the second gating signal output terminal; the gating signal receiving terminals in the fifth switch circuit group are electrically connected with the first gating signal output terminal and/or the second gating signal output terminal;

or, the gating signal receiving terminals in the fourth switch circuit group are all electrically connected with the first gating signal output terminal and/or are all electrically connected with the second gating signal output terminal; and the gating signal receiving terminals in the fifth switch circuit group are electrically connected with the first gating signal output terminal or the second gating signal output terminal.

8. The display panel of claim 7, wherein the plurality of sub-pixels arranged in an array comprises a plurality of sub-pixel groups, each sub-pixel group comprising a fourth sub-pixel column and a fifth sub-pixel column;

the fourth sub-pixel column comprises a fourth sub-pixel column and a fourth sub-pixel column, and the fourth sub-pixel column, the fifth sub-pixel column and the fourth sub-pixel column are sequentially arranged along the first direction.

9. The display panel according to any one of claims 2 to 6 or 8, wherein M/3 ═ k, where k is a positive integer equal to or greater than 1.

10. The display panel according to claim 1, wherein the sub-pixels include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light;

at least one column of the sub-pixels in the plurality of sub-pixels arranged in an array comprises the first sub-pixel, the second sub-pixel and the third sub-pixel;

the switch circuit group comprises a sixth switch circuit group;

the first sub-pixel, the second sub-pixel and the third sub-pixel are electrically connected with the data signal output terminal in the sixth switching circuit group through the data line;

and the gating signal receiving terminals in the sixth switching circuit group are electrically connected with the first gating signal output terminal or the second gating signal output terminal.

11. The display panel of claim 1, further comprising a chip on film and a driving chip on the chip on film;

the chip on film comprises N data signal connecting terminals, a plurality of first-type gating signal connecting terminals and/or a plurality of second-type gating signal connecting terminals; along the first direction, the first type of strobe signal connection terminal is positioned at the first side of the N data signal connection terminals, and the second type of strobe signal connection terminal is positioned at the second side of the N data signal connection terminals;

the driving chip comprises N data signal pins, a plurality of first-type gating signal pins and/or a plurality of second-type gating signal pins; along the first direction, the first type gating signal pins are positioned at the first sides of the N data signal pins, and the second type gating signal pins are positioned at the second sides of the N data signal pins;

the N data signal pins are electrically connected with the N data signal connecting terminals in a one-to-one corresponding mode, the plurality of first type gating signal pins are electrically connected with the plurality of first type gating signal connecting terminals in a one-to-one corresponding mode, and the plurality of second type gating signal pins are electrically connected with the plurality of second type gating signal connecting terminals in a one-to-one corresponding mode;

the N data signal connecting terminals are correspondingly connected with the N data signal source terminals one by one; the first-class gating signal connecting terminals are connected with the first-class gating signal output terminals in a one-to-one correspondence mode; and the plurality of second-class gating signal connecting terminals are connected with the plurality of second-class gating signal output terminals in a one-to-one correspondence mode.

12. A display device characterized by comprising the display panel according to any one of claims 1 to 11.