CN110931543A - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN110931543A CN110931543A CN201911368415.3A CN201911368415A CN110931543A CN 110931543 A CN110931543 A CN 110931543A CN 201911368415 A CN201911368415 A CN 201911368415A CN 110931543 A CN110931543 A CN 110931543A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Abstract
The invention discloses a display panel, a driving method thereof and a display device, wherein a plurality of gating circuits are used for providing data signals for data lines, so that the design of high screen occupation ratio and narrow frame is facilitated. In addition, for the same sub-pixel group connected to the same gate circuit, the gate circuit outputs the data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs the scanning signals, and the gate circuit finishes outputting the data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs the scanning signals. That is, for the same sub-pixel group, the time of outputting the scanning signal by the first scanning line and the time of outputting the data signal by the gate circuit are in an overlapping relationship, so that the charging time of the scanning signal can be ensured to be the time of scanning one row of pixels, that is, the sufficient charging time of the scanning signal can be ensured, thereby realizing high-frequency display, and simultaneously eliminating vertical stripes caused by the short charging time of the scanning signal, thereby improving the display effect.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.
Background
An electroluminescent display is a self-luminous device, and can realize a display function without a backlight module, so that the display has the characteristics of light weight, thinness and the like, and is widely applied in various fields.
The electroluminescent display generally has two specifications of a conventional product, that is, a product having a scanning frequency of 60Hz, and a high frequency product, that is, a product having a scanning frequency of 120 Hz. At present, a gating circuit is usually arranged in a conventional product, and the charging time of a corresponding scanning signal is generally less than 0.5 microsecond; and if the high frequency product adopts the structure setting of conventional product, scanning signal's charge time is also less than 0.5 microseconds, leads to scanning signal's charge time serious not enough this moment, easily appears the vertical line problem when showing the picture, and display effect reduces.
Therefore, how to improve the display effect of the high-frequency electroluminescent display is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The embodiment of the invention provides a display panel, a driving method thereof and a display device, which are used for improving the display effect of a high-frequency electroluminescent display panel.
An embodiment of the present invention provides a display panel, including: the pixel array comprises a plurality of columns of sub-pixels, a plurality of data lines extending along a first direction, a plurality of scanning lines sequentially arranged along the first direction and extending along a second direction, and a plurality of gating circuits; the first direction intersects the second direction;
each sub-pixel in each row of sub-pixels is correspondingly connected with two adjacent scanning lines, one scanning line is a first scanning line, the other scanning line is a second scanning line, and the first scanning line and the second scanning line are used for sequentially outputting scanning signals;
each column of sub-pixels corresponds to one or Q data lines, at least part of the columns of sub-pixels correspond to Q data lines, and Q is an integer greater than or equal to 2;
each gating circuit is provided with an input end and M output ends, and each output end is connected with one data line in a one-to-one correspondence mode; m is an integer greater than 1;
the gating circuit is used for outputting data signals to the corresponding data lines in sequence through the M output ends, and for each sub-pixel connected with the same gating circuit, the sub-pixels with the same two corresponding scanning lines are used as a sub-pixel group; for the same sub-pixel group connected with the same gating circuit, the gating circuit outputs data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs scanning signals, and finishes outputting data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs scanning signals.
Correspondingly, an embodiment of the present invention further provides a method for driving any one of the display panels, including:
outputting scanning signals to the scanning lines line by line, and outputting the scanning signals to the second scanning lines corresponding to the sub-pixels after outputting the scanning signals to the first scanning lines corresponding to the sub-pixels;
controlling each gating circuit to sequentially output data signals to the corresponding data lines through the M output ends, and regarding each sub-pixel connected with the same gating circuit, regarding the sub-pixel with the same two corresponding scanning lines as a sub-pixel group; for the same sub-pixel group connected with the same gating circuit, the gating circuit outputs data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs scanning signals, and finishes outputting the data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs scanning signals.
Correspondingly, the embodiment of the invention also provides a display device which comprises any one of the display panels provided by the embodiment of the invention.
The invention has the following beneficial effects:
according to the display panel, the driving method thereof and the display device provided by the embodiment of the invention, the plurality of gating circuits are used for providing data signals for the data lines, and each gating circuit corresponds to the plurality of data lines, so that the high screen occupation ratio and the narrow frame design are favorably realized. In addition, for the same sub-pixel group connected to the same gate circuit, the gate circuit outputs the data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs the scanning signals, and the gate circuit finishes outputting the data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs the scanning signals. That is, for the same sub-pixel group, the time of outputting the scanning signal by the first scanning line and the time of outputting the data signal by the gate circuit are in an overlapping relationship, so that the charging time of the scanning signal can be ensured to be the time of scanning one row of pixels, that is, the sufficient charging time of the scanning signal can be ensured, thereby realizing high-frequency display, and simultaneously eliminating vertical stripes caused by the short charging time of the scanning signal, thereby improving the display effect.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a timing diagram of signals corresponding to the display panel shown in FIG. 1;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 4 is a timing diagram of signals corresponding to the display panel shown in FIG. 3;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 6 is a timing diagram of signals corresponding to the display panel shown in FIG. 5;
fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 9 is a flowchart of a driving method of a display panel according to an embodiment of the invention;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
Currently, for a product with a conventional scan frequency (e.g. a product with a scan frequency of 60 Hz), in order to reduce the frame width, a gating circuit design is generally adopted, and the corresponding time for displaying a frame of picture is generally 16.67ms, and if the resolution of such a product is 1080 × 2340, the time for scanning a row of pixels is 16.67ms/2340, i.e. the time for scanning a row of sub-pixels is 7.1 μ s. However, in actual scanning, it is necessary to consider the time interval between the input of the scanning signals of the adjacent scanning lines, and therefore, in practice, the time for scanning a row of sub-pixels is generally less than 5 μ s.
For a high frequency product (for example, a product with a scanning frequency of 120 Hz), if the design of the gate circuit is also adopted, when the corresponding time for displaying a frame of picture is kept unchanged, the time for scanning a row of sub-pixels is reduced by at least one half compared with the time for displaying a frame of picture by the low frequency product, and in the time period for scanning a row of sub-pixels, the scanning signal needs to be input to the scanning line after the data line corresponding to the sub-pixel row corresponding to the scanning line finishes outputting the data signal, so that the charging time of the scanning signal is reduced to less than 0.5 μ s in the time for scanning a row of sub-pixels, which results in serious shortage of the charging time of the scanning signal. Therefore, the current high-frequency products generally adopt a hipin design, so that the charging time of the scanning signals can reach 2 mus, but the hipin design can make the frame of the display panel wider, which is not beneficial to the current narrow frame design.
In view of the above, embodiments of the present invention provide a display panel, a driving method thereof and a display device, which can adopt a gate circuit design even if the display panel is a high frequency product, and ensure that the scan lines have sufficient charging time.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted. The words expressing the position and direction described in the present invention are illustrated in the accompanying drawings, but may be changed as required and still be within the scope of the present invention. The drawings of the present invention are for illustrative purposes only and do not represent true scale.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims.
The following describes a display panel, a driving method thereof, and a display device according to an embodiment of the present invention with reference to the accompanying drawings.
Fig. 1, fig. 3 and fig. 5 show a display panel according to an embodiment of the present invention, where fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention; fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention; fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention; the method comprises the following steps: a plurality of columns of subpixels pix, a plurality of data lines data extending along a first direction X, a plurality of scan lines S1, S2, S3, … … arranged in sequence along the first direction X and extending along a second direction Y, and a plurality of gate circuits 01; the first direction X intersects the second direction Y;
each sub-pixel pix in each row of sub-pixels pix is correspondingly connected with two adjacent scanning lines Sn and Sn +1, wherein one scanning line is a first scanning line S (1), the other scanning line is a second scanning line S (2), and the first scanning line S (1) and the second scanning line S (2) are used for sequentially outputting scanning signals;
each column of sub-pixels pix corresponds to one or Q data lines data, at least part of the columns of sub-pixels pix correspond to the Q data lines data, and Q is an integer greater than or equal to 2;
each gating circuit 01 is provided with an input end IN and M output ends O1-OM, and each output end On is connected with a data line data IN a one-to-one correspondence manner; m is an integer greater than 1;
as shown in fig. 2, 4 and 6, fig. 2 is a signal timing diagram corresponding to the display panel shown in fig. 1; FIG. 4 is a timing diagram of signals corresponding to the display panel shown in FIG. 3; FIG. 6 is a timing diagram of signals corresponding to the display panel shown in FIG. 5; the gating circuit 01 is used for sequentially outputting data signals to corresponding data lines data through M output ends O1-OM, and for each sub-pixel pix connected with the same gating circuit 01, the sub-pixel pix with the same two corresponding scanning lines S (1) and S (2) is taken as a sub-pixel group 02; for the same sub-pixel group 02 connected to the same gate circuit 01, the gate circuit 01 sequentially outputs data signals to the sub-pixels pix of the sub-pixel group 02 when the scan signal is output from the first scan line S (1) corresponding to the sub-pixel group 02, and finishes outputting data signals to all the sub-pixels pix of the sub-pixel group 02 before the scan signal is output from the second scan line S (2) corresponding to the sub-pixel group 02.
According to the display panel provided by the embodiment of the invention, the plurality of gating circuits are used for providing data signals for the data lines, and each gating circuit corresponds to the plurality of data lines, so that the design of high screen occupation ratio and narrow frame is facilitated. In addition, for the same sub-pixel group connected to the same gate circuit, the gate circuit outputs the data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs the scanning signals, and the gate circuit finishes outputting the data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs the scanning signals. That is, for the same sub-pixel group, the time of outputting the scanning signal by the first scanning line and the time of outputting the data signal by the gate circuit are in an overlapping relationship, so that the charging time of the scanning signal can be ensured to be the time of scanning one row of pixels, that is, the sufficient charging time of the scanning signal can be ensured, thereby realizing high-frequency display, and simultaneously eliminating vertical stripes caused by the short charging time of the scanning signal, thereby improving the display effect.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is for better explaining the present invention, but not limiting the present invention.
Optionally, in the display panel provided in the embodiment of the present invention, as shown in fig. 1, M is an even number (fig. 1 takes M-4 as an example);
two scanning lines S (1) and S (2) which are correspondingly connected with each sub-pixel pix in each row of sub-pixels pix are the same;
a second scanning line S (2) corresponding to the sub-pixel pix in the nth row is connected with a first scanning line S (1) corresponding to the sub-pixel pix in the (n +1) th row, and n is an integer larger than 0;
each gating circuit 01 corresponds to M/2 columns of sub-pixels pix, the number of the sub-pixels pix included in each column of sub-pixels pix is the same, each column of sub-pixels pix corresponds to two data lines data, each sub-pixel pix in each column is connected with one data line data of the two data lines data, and the data lines data connected with any two adjacent sub-pixels pix in each column are different.
Specifically, the display panel shown in fig. 1 will be described with reference to the timing chart of fig. 2. During the time when the first row of sub-pixels is scanned (H indicates the time when the first row of sub-pixels is scanned), the scan line S1 outputs a scan signal for performing reset control on the sub-pixels pix of the first row, and at the same time, during the first H, each gate circuit 01 completes outputting a data signal to the sub-pixels pix of the first row. In the second H, the scan line S2 outputs a scan signal for reset control of the sub-pixels pix of the second row and for data write control of the sub-pixels pix of the first row to write the gate circuit 01 outputting a data signal to the sub-pixels pix of the first row into the sub-pixels pix of the first row. Meanwhile, in the second H, each gate circuit 01 completes outputting the data signal to the sub-pixel pix of the second row. And in the nth H, the analogy is repeated, and finally the scanning of one frame of picture is finished.
Specifically, referring to fig. 1, taking the first gate circuit 01 as an example, in the first H, the scan line S1 outputs a scan signal, and the gate circuit 01 outputs a data signal to the subpixel pix1 and then outputs a data signal to the subpixel pix 2. Then, in the second H, the scan line S2 outputs a scan signal, and the gate circuit 01 outputs a data signal to the subpixel pix3 and then outputs a data signal to the subpixel pix 4. That is, the gate circuit 01 sequentially outputs the data signals to the subpixels pix of the subpixel group 02 when the scan signal is output from the first scan line S (1) corresponding to the subpixel group 02, and finishes outputting the data signals to all the subpixels pix of the subpixel group 02 before the scan signal is output from the second scan line S (2) corresponding to the subpixel group 02. If the interval time between the scan signals is not considered, the charge time of the scan signals can be made equal to an H time even if the charge time of the scan signals reaches a maximum. Therefore, the scanning signals can be ensured to have enough charging time, so that the vertical stripes caused by the short charging time of the scanning signals can be eliminated while high-frequency display is realized, and the display effect is improved.
Optionally, in the display panel provided in the embodiment of the present invention, as shown in fig. 3, M is an integer multiple of 3 (fig. 3 exemplifies that M is equal to 6);
two scanning lines S (1) and S (2) which are correspondingly connected with each sub-pixel pix in the sub-pixel pix of the 3K +1 th row are the same;
two scanning lines S (1) and S (2) which are correspondingly connected with the sub-pixels pix in the 3K +3 th row of sub-pixels pix are the same;
in the 3K +2 row of sub-pixels pix, any two adjacent sub-pixels pix are provided, wherein two scanning lines S (1) and S (2) correspondingly connected with one sub-pixel pix are the same as the two scanning lines S (1) and S (2) correspondingly connected with the sub-pixels pix in the 3K +1 row of sub-pixels pix, and the two scanning lines S (1) and S (2) correspondingly connected with the other sub-pixel pix are the same as the two scanning lines S (1) and S (2) correspondingly connected with the sub-pixels pix in the 3K +3 row of sub-pixels pix;
a second scanning line (2) corresponding to the sub-pixel pix in the 3K +1 row is connected with a first scanning line (1) corresponding to the sub-pixel pix in the 3K +3 row, and K is an integer greater than or equal to 0;
each gating circuit 01 corresponds to M/3 columns of sub-pixels pix, the number of the sub-pixels pix included in each column of sub-pixels pix is the same, each column of sub-pixels pix corresponds to 3 data lines data, in each column of sub-pixels pix, every 3 sub-pixels pix which are adjacent in sequence are taken as a sub-pixel pix unit, and 3 sub-pixels pix in each sub-pixel pix unit are respectively connected with one of the 3 data lines data; in each column of sub-pixels pix, the data lines data connected with the sub-pixels pix in the 1 st row in different sub-pixel pix units are the same, the data lines data connected with the sub-pixels pix in the 2 nd row in different sub-pixel pix units are the same, and the data lines data connected with the sub-pixels pix in the 3 rd row in different sub-pixel pix units are the same.
Specifically, the display panel shown in fig. 3 will be described with reference to the timing chart of fig. 4. During the time of scanning the subpixels in the first row (H represents the time of scanning the subpixels in one row), the scan line S1 outputs scan signals for reset control of the subpixels pix in the first row and the subpixels pix in the odd-numbered positions in the second row, and at the same time, during the first H, each gate circuit 01 completes the output of data signals to the subpixels pix in the first row and the subpixels pix in the odd-numbered positions in the second row. In the second H, the scan line S2 outputs scan signals for performing reset control on the sub-pixels pix in the third row and the sub-pixels pix in the even-numbered positions in the second row, and for performing data write control on the sub-pixels pix in the first row and the sub-pixels pix in the odd-numbered positions in the second row, so as to write the data signals output by the gate circuit 01 to the sub-pixels pix in the first row and the sub-pixels pix in the odd-numbered positions in the second row. Meanwhile, in the second H, each gating circuit 01 completes outputting data signals to the sub-pixels pix in the third row and the sub-pixels pix in the even-numbered positions in the second row. And in the nth H, the analogy is repeated, and finally the scanning of one frame of picture is finished.
Specifically, referring to fig. 3, taking the first gate circuit 01 as an example, in the first H, the scan line S1 outputs a scan signal, and the gate circuit 01 outputs a data signal to the subpixel pix1, then outputs a data signal to the subpixel pix2, and then outputs a data signal to the subpixel pix 3. Then, in the second H, the scan line S2 outputs a scan signal, and the gate circuit 01 outputs a data signal to the subpixel pix4, then outputs a data signal to the subpixel pix5, and then outputs a data signal to the subpixel pix 6. That is, the gate circuit 01 sequentially outputs the data signals to the subpixels pix of the subpixel group 02 when the scan signal is output from the first scan line S (1) corresponding to the subpixel group 02, and finishes outputting the data signals to all the subpixels pix of the subpixel group 02 before the scan signal is output from the second scan line S (2) corresponding to the subpixel group 02. If the interval time between the scan signals is not considered, the charge time of the scan signals can be made equal to an H time even if the charge time of the scan signals reaches a maximum. Therefore, the scanning signals can be ensured to have enough charging time, so that the vertical stripes caused by the short charging time of the scanning signals can be eliminated while high-frequency display is realized, and the display effect is improved.
Optionally, in the display panel provided in the embodiment of the present invention, as shown in fig. 5, M is an odd number greater than 1 (fig. 5 exemplifies that M is equal to 3);
each gating circuit 01 corresponds to (M +1)/2 columns of sub-pixels pix, and in (M +1)/2 columns of sub-pixels pix, one column of sub-pixels pix is a first sub-pixel pixa, the rest columns of sub-pixels pix are second sub-pixels pixb, the number of the first sub-pixels pixa in one column is half of the number of the second sub-pixels pixa in one column, each column of the first sub-pixels pixa corresponds to one data line data, and each column of the second sub-pixels pixb corresponds to two data lines data;
for each second sub-pixel pixb, two scanning lines S (1) and S (2) which are correspondingly connected with each second sub-pixel pixb in each row of second sub-pixels pixb are the same;
a second scanning line S (2) corresponding to the second sub-pixel pixb in the nth row is connected with a first scanning line S (1) corresponding to the second sub-pixel pixb in the (n +1) th row, and n is an integer larger than 0;
for each first sub-pixel pixa, in any two adjacent columns of the first sub-pixels pixa, in one column of the first sub-pixels pixa, the scan lines S (1) and S (2) connected to the xth first sub-pixel pixa are the same as the scan lines S (1) and S (2) connected to the 2x-1 th second sub-pixel pixb; in the other column of the first subpixels pixa, the scan lines S (1) and S (2) connected to the xth first subpixel pixa are the same as the scan lines S (1) and S (2) connected to the 2 xth second subpixel pixb, where x is an integer greater than 0.
Specifically, the display panel shown in fig. 5 will be described with reference to the timing chart of fig. 6. During the time of scanning the first row of sub-pixels (H represents the time of scanning one row of sub-pixels), the scan line S1 outputs a scan signal for performing reset control of the first sub-pixel pixb in the first row and the first sub-pixel pixa in the first row among the second sub-pixels pixb in the first row and the 2y (y is an odd number) column sub-pixels, and at the same time, during the first H, each gate circuit 01 completes output of a data signal to the first sub-pixel pixa in the first row among the second sub-pixels pixb in the first row and the 2y (y is an odd number) column sub-pixels. In the second H, the scan line S2 outputs a scan signal for performing reset control on the second subpixel pixb in the second row and the first subpixel pixa in the first row in the 2y (y is an even number) column subpixels, and for performing data write control on the first subpixel pixa in the first row in the second subpixel pixb in the first row and the 2y (y is an odd number) column subpixels to write the gate circuit 01 to the second subpixel pixb in the first row and the first subpixel pixa in the first row in the 2y (y is an odd number) column subpixels into the second subpixel pixb in the first row and the first subpixel pixa in the first row in the 2y (y is an odd number) column subpixels. Meanwhile, in the second H, each gate circuit 01 completes outputting the data signal to the second subpixel pixb in the second row and the first subpixel pixa in the first row among the subpixels in the 2y (y is an even number) th column. And in the nth H, the analogy is repeated, and finally the scanning of one frame of picture is finished.
It should be noted that, for the sub-pixels located in the 2 y-th column, that is, for each first sub-pixel column, the number of rows where the first sub-pixel is located is sorted by the number of first sub-pixels in the column where the first sub-pixel is located.
Specifically, referring to fig. 5, taking the first gate circuit 01 and the second gate circuit 01 as an example, in the first H, the scan line S1 outputs a scan signal, while the first gate circuit 01 outputs a data signal to the subpixel pix1 first, while the second gate circuit 01 outputs a data signal to the subpixel pix4 first, and then the first gate circuit 01 outputs a data signal to the subpixel pix 3. Then, in the second H, the scan line S2 outputs a scan signal, the first gate circuit 01 outputs a data signal to the subpixel pix3 while the second gate circuit 01 outputs a data signal to the subpixel pix5, and then the second gate circuit 01 outputs a data signal to the subpixel pix 6. That is, the gate circuit 01 sequentially outputs the data signals to the subpixels pix of the subpixel group 02 when the scan signal is output from the first scan line S (1) corresponding to the subpixel group 02, and finishes outputting the data signals to all the subpixels pix of the subpixel group 02 before the scan signal is output from the second scan line S (2) corresponding to the subpixel group 02. If the interval time between the scan signals is not considered, the charge time of the scan signals can be made equal to an H time even if the charge time of the scan signals reaches a maximum. Therefore, the scanning signals can be ensured to have enough charging time, so that the vertical stripes caused by the short charging time of the scanning signals can be eliminated while high-frequency display is realized, and the display effect is improved.
Optionally, in the display panel provided in the embodiment of the present invention, as shown in fig. 7, fig. 7 is a schematic view of another structure of the display panel provided in the embodiment of the present invention; the scan lines are not shown in fig. 7, but only to schematically illustrate the relative position relationship between the first sub-pixel and the second sub-pixel, and the connection relationship between the first sub-pixel and the scan lines and the second sub-pixel is the same as that in fig. 5.
In fig. 7, the width of the first sub-pixel pixa is greater than the width of the second sub-pixel pixb along the first direction X; and, the center of the first subpixel pixa of the x-th line is located between the center of the second subpixel pixb of the 2x-1 th line and the center of the second subpixel pixb of the 2 x-th line. Since the number of the first sub-pixels pixa in the first sub-pixel column is half of the number of the second sub-pixels pixb in the second sub-pixel column, for example, the reduction of the aperture ratio of the display panel due to the small number of the first sub-pixels pixa is avoided, and therefore, along the first direction X, the width of the first sub-pixels pixa is greater than the width of the second sub-pixels pixb, so that the aperture ratio of the display panel can be ensured. In addition, since the first subpixel pixa in a column corresponds to one data line data, that is, the number of the data lines data is reduced, the aperture ratio of the display panel can be further improved.
Optionally, in the display panel provided in the embodiment of the present invention, as shown in fig. 1, fig. 3, and fig. 5, the gate circuit 01 further includes M control terminals;
the mth control end is connected with the mth clock control end Cm and used for controlling the on/off of the input end IN and the mth output end Om, wherein M is an integer which is greater than 0 and less than or equal to M;
the 1 st to Mth clock control terminals C1-CM are used for outputting clock signals in sequence.
In specific implementation, as shown in fig. 1, 3 and 5, the gating circuit 01 specifically includes M transistors: T1-TM, the first pole of the nth transistor Tn is connected to the input terminal IN, the second pole of the nth transistor Tn is connected to the nth output terminal On, and the gate of the nth transistor Tn is connected to the nth control terminal.
Optionally, in the display panel provided in the embodiment of the present invention, the transistors in the gate circuit are all N-shaped transistors or all P-shaped transistors, which is not limited herein.
Optionally, in the display panel provided in the embodiment of the present invention, as shown in fig. 1 and fig. 3, when each gating circuit 01 corresponds to M/2 columns of sub-pixels pix or M/3 columns of sub-pixels pix, M clock signal lines CLK1 to CLKM are further included;
each of the clock signal terminals C1 through CM corresponding to each gate circuit 01 is connected to one of the M clock signal lines CLK1 through CLKM, respectively. That is, all gate circuits share the clock signal line, and a part of the gate circuits can be reduced by the width of the frame region of the display panel.
Optionally, in the display panel provided in the embodiment of the present invention, as shown in fig. 5, when M is an odd number, the display panel further includes M +1 clock signal lines;
each clock signal end corresponding to each gating circuit 01 is correspondingly connected with one of the M +1 clock signal lines. That is, all gate circuits share the clock signal line, and a part of the gate circuits can be reduced by the width of the frame region of the display panel.
Optionally, in the display panel provided in the embodiment of the present invention, as shown in fig. 8, fig. 8 is a schematic view of another structure of the display panel provided in the embodiment of the present invention; the display panel has a display area a and a frame area surrounding the display area B, and each gate circuit 01 is located in the frame area B. In specific implementation, the sub-pixel pix (not shown in fig. 8), the data line data, and the scan line Sn are all disposed in the display area a. The gate driving circuit 03 connected to each scanning line Sn may be further provided in the frame region B, and the gate driving circuit 03 may be further provided at one end of the scanning line Sn, or the gate driving circuit 03 may be provided at both ends of the scanning line Sn, which is not limited herein. Fig. 8 illustrates an example in which the gate driver circuits 03 are provided at both ends of the scanning line Sn.
Based on the same inventive concept, an embodiment of the present invention further provides a driving method of any one of the display panels provided by the embodiments of the present invention, as shown in fig. 9, fig. 9 is a flowchart of the driving method of a display panel provided by the embodiments of the present invention; the method comprises the following steps:
s101, outputting scanning signals to each scanning line row by row, and outputting the scanning signals to a corresponding second scanning line after outputting the scanning signals to a corresponding first scanning line aiming at each sub-pixel;
s102, controlling each gating circuit to sequentially output data signals to corresponding data lines through M output ends, and regarding each sub-pixel connected with the same gating circuit, taking the sub-pixel with the same two corresponding scanning lines as a sub-pixel group; for the same sub-pixel group connected with the same gating circuit, the gating circuit outputs data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs scanning signals, and finishes outputting the data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs the scanning signals.
In specific implementation, because the principle of the driving method for solving the problem is similar to that of the display panel, the implementation of the driving method can refer to the implementation of the display panel, and repeated details are not repeated.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises any one of the display panels provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like shown in fig. 10. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
According to the display panel, the driving method thereof and the display device provided by the embodiment of the invention, the plurality of gating circuits are used for providing data signals for the data lines, and each gating circuit corresponds to the plurality of data lines, so that the high screen occupation ratio and the narrow frame design are favorably realized. In addition, for the same sub-pixel group connected to the same gate circuit, the gate circuit outputs the data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs the scanning signals, and the gate circuit finishes outputting the data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs the scanning signals. That is, for the same sub-pixel group, the time of outputting the scanning signal by the first scanning line and the time of outputting the data signal by the gate circuit are in an overlapping relationship, so that the charging time of the scanning signal can be ensured to be the time of scanning one row of pixels, that is, the sufficient charging time of the scanning signal can be ensured, thereby realizing high-frequency display, and simultaneously eliminating vertical stripes caused by the short charging time of the scanning signal, thereby improving the display effect.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. A display panel, comprising: the pixel array comprises a plurality of columns of sub-pixels, a plurality of data lines extending along a first direction, a plurality of scanning lines sequentially arranged along the first direction and extending along a second direction, and a plurality of gating circuits; the first direction intersects the second direction;
each sub-pixel in each row of sub-pixels is correspondingly connected with two adjacent scanning lines, one scanning line is a first scanning line, the other scanning line is a second scanning line, and the first scanning line and the second scanning line are used for sequentially outputting scanning signals;
each column of sub-pixels corresponds to one or Q data lines, at least part of the columns of sub-pixels correspond to Q data lines, and Q is an integer greater than or equal to 2;
each gating circuit is provided with an input end and M output ends, and each output end is connected with one data line in a one-to-one correspondence mode; m is an integer greater than 1;
the gating circuit is used for outputting data signals to the corresponding data lines in sequence through the M output ends, and for each sub-pixel connected with the same gating circuit, the sub-pixels with the same two corresponding scanning lines are used as a sub-pixel group; for the same sub-pixel group connected with the same gating circuit, the gating circuit outputs data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs scanning signals, and finishes outputting data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs scanning signals.
2. The display panel of claim 1, wherein M is an even number;
two scanning lines correspondingly connected with the sub-pixels in each row of sub-pixels are the same;
the second scanning line corresponding to the sub-pixel in the nth row is connected with the first scanning line corresponding to the sub-pixel in the (n +1) th row, and n is an integer greater than 0;
each gating circuit corresponds to M/2 columns of sub-pixels, the number of the sub-pixels in each column of sub-pixels is the same, each column of sub-pixels corresponds to two data lines, each sub-pixel in each column is connected with one of the two data lines, and the data lines connected with any two adjacent sub-pixels in each column are different.
3. The display panel according to claim 1, wherein M is an integer multiple of 3;
two scanning lines correspondingly connected with the sub-pixels in the 3K +1 th row of sub-pixels are the same;
two scanning lines correspondingly connected with the sub-pixels in the 3K +3 th row of sub-pixels are the same;
in the sub-pixels in the 3K +2 th row, two scanning lines correspondingly connected with one sub-pixel are the same as two scanning lines correspondingly connected with the sub-pixels in the 3K +1 th row, and two scanning lines correspondingly connected with the other sub-pixel are the same as two scanning lines correspondingly connected with the sub-pixels in the 3K +3 th row;
the second scanning line corresponding to the sub-pixel in the 3K +1 th row is connected with the first scanning line corresponding to the sub-pixel in the 3K +3 rd row, and K is an integer greater than or equal to 0;
each gating circuit corresponds to M/3 columns of sub-pixels, the number of the sub-pixels included in each column of sub-pixels is the same, each column of sub-pixels corresponds to 3 data lines, each 3 sequentially adjacent sub-pixels in each column of sub-pixels are taken as a sub-pixel unit, and 3 sub-pixels in each sub-pixel unit are respectively connected with one of the 3 data lines; in each column of sub-pixels, the data lines connected with the sub-pixels in the 1 st row in different sub-pixel units are the same, the data lines connected with the sub-pixels in the 2 nd row in different sub-pixel units are the same, and the data lines connected with the sub-pixels in the 3 rd row in different sub-pixel units are the same.
4. The display panel of claim 1, wherein M is an odd number greater than 1;
each gating circuit corresponds to (M +1)/2 rows of sub-pixels, in the (M +1)/2 rows of sub-pixels, one row of sub-pixels is a first sub-pixel, the rest rows of sub-pixels are second sub-pixels, the number of the first sub-pixels in one row is half of that of the second sub-pixels in one row, each row of the first sub-pixels corresponds to one data line, and each row of the second sub-pixels corresponds to two data lines;
for each second sub-pixel, two scanning lines correspondingly connected with each second sub-pixel in each row of the second sub-pixels are the same;
the second scanning line corresponding to the second sub-pixel in the nth row is connected with the first scanning line corresponding to the second sub-pixel in the (n +1) th row, and n is an integer greater than 0;
for each first sub-pixel, in any two adjacent columns of the first sub-pixels, in one column of the first sub-pixels, the scanning line connected to the xth first sub-pixel is the same as the scanning line connected to the 2x-1 th second sub-pixel; in another column of the first sub-pixels, the scan line connected to the xth first sub-pixel is the same as the scan line connected to the 2 xth second sub-pixel, where x is an integer greater than 0.
5. The display panel according to any one of claims 2 to 4, wherein the gate circuit further includes M control terminals;
the mth control end is connected with the mth clock control end and used for controlling the on/off of the input end and the mth output end, wherein M is an integer which is greater than 0 and less than or equal to M;
the 1 st to Mth clock control ends are used for sequentially outputting clock signals.
6. The display panel of claim 5, wherein when each of the gate circuits corresponds to M/2 columns of sub-pixels or M/3 columns of sub-pixels, further comprising M clock signal lines,
and each clock signal end corresponding to each gating circuit is correspondingly connected with one of the M clock signal lines respectively.
7. The display panel of claim 5, further comprising M +1 clock signal lines when M is an odd number,
and each clock signal end corresponding to each gating circuit is correspondingly connected with one of the M +1 clock signal lines respectively.
8. The display panel of claim 4,
the width of the first sub-pixel is larger than that of the second sub-pixel along the first direction;
and the center of the first sub-pixel of the x-th row is positioned between the center of the second sub-pixel of the 2 x-1-th row and the center of the second sub-pixel of the 2 x-th row.
9. The display panel according to claim 1, wherein the display panel has a display area and a frame area surrounding the display area, and each of the gate circuits is located in the frame area.
10. The method for driving a display panel according to any one of claims 1 to 9, comprising:
outputting scanning signals to the scanning lines line by line, and outputting the scanning signals to the second scanning lines corresponding to the sub-pixels after outputting the scanning signals to the first scanning lines corresponding to the sub-pixels;
controlling each gating circuit to sequentially output data signals to the corresponding data lines through the M output ends, and regarding each sub-pixel connected with the same gating circuit, regarding the sub-pixel with the same two corresponding scanning lines as a sub-pixel group; for the same sub-pixel group connected with the same gating circuit, the gating circuit outputs data signals to the sub-pixel group in sequence when the first scanning line corresponding to the sub-pixel group outputs scanning signals, and finishes outputting the data signals to the sub-pixel group before the second scanning line corresponding to the sub-pixel group outputs scanning signals.
11. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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