CN111708291B - DSP information mutual transmission method for domestic chip - Google Patents
DSP information mutual transmission method for domestic chip Download PDFInfo
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- CN111708291B CN111708291B CN202010469988.1A CN202010469988A CN111708291B CN 111708291 B CN111708291 B CN 111708291B CN 202010469988 A CN202010469988 A CN 202010469988A CN 111708291 B CN111708291 B CN 111708291B
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/22—Pc multi processor system
- G05B2219/2225—Communication, CPU accesses own I-O and next CPU over dual port memory
Abstract
The invention discloses a DSP information mutual transmission method for a domestic chip, which is applied to more than two DSP controllers, wherein carrier signals of the controllers are synchronous; each controller is provided with an McBSP communication module, and the McBSP communication modules of the two controllers are communicated with each other so as to establish a communication relationship between the two controllers; which comprises the following steps: any one of the two communicating controllers sends information by the McBSP communication module; before the carrier signal reaches a preset amplitude value, the other controller synchronously receives information through the McBSP communication module and synchronously stores the received information; the controller for transmitting information is switched when the carrier signal reaches a predetermined amplitude. The information mutual transmission method can realize the large data volume receiving and transmitting between the two controllers, and can effectively improve the communication efficiency between the two controllers so as to ensure the real-time transmission.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a DSP information mutual transmission method for a domestic chip.
Background
The existing uninterruptible power supply mostly adopts a domestic chip, two DSP controllers are arranged to respectively control a rectifier and an inverter, and various types of information such as sampled current value information, fault information and the like need to be shared between the two controllers in real time so as to maintain the stable use of an uninterruptible power supply system. That is, a large amount of information needs to be efficiently transmitted between two DSP controllers, so that a large amount of data needs to be synchronously received and transmitted in the information transmission process, and the communication efficiency needs to be improved to ensure real-time transmission between the two DSP controllers.
At present, information transmission between two controllers is realized through IO or SCI communication modes; however, although the communication efficiency of the IO communication method is high (up to 100 microseconds), each IO port can only transmit 1 bit signal, and the single transmission information amount is too small to meet the requirement of large data amount transmission. The SCI communication mode has large information amount which can be transmitted at one time, but the communication efficiency is lower, and the high timeliness in the information mutual transmission process cannot be ensured; in addition, the communication protocol algorithm of the SCI communication mode is complex and has low analysis efficiency, and the communication efficiency is further reduced.
Disclosure of Invention
The invention aims to overcome the defects or problems in the background art and provide a DSP information mutual transmission method for a domestic chip, which can realize the large data volume receiving and transmitting between two controllers and effectively improve the communication efficiency between the two controllers so as to ensure the real-time transmission.
In order to achieve the purpose, the invention adopts the following technical scheme:
a DSP information mutual transmission method for a domestic chip is applied to more than two DSP controllers, and carrier signals of the controllers are synchronous; each controller is provided with an McBSP communication module, and the McBSP communication modules of the two controllers are communicated with each other so as to establish a communication relationship between the two controllers; which comprises the following steps: any one of the two communicating controllers sends information by the McBSP communication module; before the carrier signal reaches a preset amplitude value, the other controller synchronously receives information through the McBSP communication module and synchronously stores the received information; switching a controller for transmitting information when the carrier signal reaches a predetermined amplitude; the preset amplitude of the carrier signal is zero and a peak value; the two communication controllers are respectively a first controller and a second controller; when the carrier signal of the first controller reaches a preset amplitude value, the information receiving and transmitting state of the first controller is switched; and sending a corresponding state switching instruction to the second controller; and after receiving the state switching instruction, the second controller correspondingly switches the information receiving and transmitting states.
Preferably, the McBSP communication module of each controller communicates with its memory module via its DMA channel; the McBSP communication module of any one of the two communicating controllers receives information and transmits the received information to the memory module for storage through the DMA channel; in the period that the memory module of any one of the two communicating controllers transmits the stored information to be transmitted to the McBSP communication module of the controller through the DMA channel, the McBSP communication module transmits the information received by the memory module to the McBSP communication module of the other controller.
Preferably, the CPU processing module of each controller is communicated with the memory module; when any one of the two communicating controllers is switched from a message receiving state to a message sending state, the DMA channel occupies bus resources and interrupts the main control of the CPU processing module; and the received information stored by the memory module is used for being called by the CPU processing module during the main control interruption of the CPU processing module.
Preferably, each controller performs cumulative counting on the interrupt times of the main control of the CPU processing module by setting a chip selection counter; the information to be sent stored by the memory module comprises strong aging information which needs to be sent during each interruption and weak aging information which can be sent at intervals during a plurality of interruptions; when any one of the two communicating controllers is switched from a message receiving state to a message sending state, the message to be sent stored by the memory module is packaged and encoded into a data format suitable for being received by the McBSP communication module; the data format at least comprises a first data segment, a second data segment and counting bits arranged between the first data segment and the second data segment; and writing the strong aging information into a first data segment, writing the current interruption time count value accumulated by the chip selection counter into a counting bit, and writing the weak aging information required to be sent by the current interruption into a second data segment.
Preferably, when any one of the two communicating controllers is switched from the information receiving state to the information sending state, the CPU processing module performs analysis processing of all data segments on the called received information.
Preferably, the CPU processing module of any one of the two communicating controllers feeds back the processing result of the received information to the memory module thereof.
Preferably, the first controller adjusts the interval period during which the carrier signal reaches a predetermined amplitude value according to the length of the information to be transmitted stored by the first controller.
Preferably, the McBSP communication module of each controller includes a transmission register and a reception register; the transmitting register of the McBSP communication module of any one controller of the two communicating controllers is communicated with the receiving register of the McBSP communication module of the other controller.
As can be seen from the above description of the present invention, the present invention has the following advantages over the prior art:
1. the carrier signals of the DSP controllers are synchronous, that is, the amplitude of the carrier signals of the two controllers which need to transmit information to each other at any time point is the same, so that the receiving and sending states of the two controllers are synchronously switched when the carrier signals reach the preset amplitude.
Specifically, when the carrier signal reaches a predetermined amplitude, the controllers for sending information are switched, so that the two controllers can alternately send information to realize mutual information transmission between the two controllers; namely, any one of the two communicating controllers is ensured to be in an information sending state, and the other controller is synchronously in an information receiving state; the situation that two controllers send or receive at the same time is avoided, so that the accuracy of information mutual transmission is ensured. The controller synchronously stores the received information in the receiving process so as to avoid occupying the cache space of the McBSP communication module for a long time and further improve the communication efficiency.
The two controllers establish the communication relationship between the two controllers through the McBSP communication modules arranged on the two controllers respectively so as to realize the mutual information transmission between the two controllers; compared with the conventional IO or SCI communication mode, the data volume transmittable at a single time is greatly improved by receiving and transmitting information through the McBSP communication module, the communication efficiency in the receiving and transmitting process is high, and the timeliness of information transmission can be ensured.
2. The McBSP communication module in each controller is communicated with the memory module through the DMA channel, namely, the information between the McBSP communication module and the memory module is received and transmitted through the DMA channel.
The information to be sent stored in the memory module can be directly read through the DMA channel so as to be rapidly transmitted to the McBSP communication module, and the information transmission efficiency in the single controller is greatly improved without other intermediate media; and the McBSP communication module sends the information received by the memory module to the McBSP communication module of the other controller, so that the information transmission with large data volume and high timeliness between the two controllers can be realized.
Similarly, the information received by the McBSP communication module can be quickly transmitted to the memory module for storage through the DMA channel, so that the communication efficiency between the two controllers is further improved.
3. When any one of the two communicating controllers is switched from a message receiving state to a message sending state, the DMA channel occupies bus resources, namely bus addresses, and interrupts the main control of the CPU processing module; because the DMA module directly occupies the bus address, each information to be sent can be directly sent to the corresponding receiving address of the McBSP communication module from the storage address in the memory module, so that the information transmission efficiency in the single controller is greatly improved.
The CPU processing module calls the memory module to receive complete received information at the same time when the CPU processing module sends information in the memory module so as to further and completely analyze and process the received information; and incomplete information receiving is called in the information receiving process of the controller, so that mistransmission of the information is avoided, and the accuracy and the integrity of information receiving are ensured.
4. Because the data volume of the information to be sent is large and the information to be sent is difficult to be completely transmitted in a single interruption, the information to be sent can be roughly divided into two types according to the timeliness requirement of each information to be sent, wherein the two types of information comprise strong timeliness information which needs to be sent every interruption and weak timeliness information which can be sent at intervals of a plurality of interruptions.
The information to be sent needs to be packaged and encoded into a data format suitable for being received by the McBSP communication module and then transmitted for multiple times. The method comprises the steps that strong aging information which needs to be sent every time of interruption is fixedly written into a first data segment, a current interruption time count value accumulated by a chip selection counter is written into a counting bit, and the counting bit is used for marking the accumulated time of the current interruption; therefore, the weak aging information content required to be sent in the current interruption can be determined according to the current interruption count value, and then the weak aging information is fixedly written into the second data segment.
The information with different timeliness requirements is classified and transmitted for several times, so as to meet the requirements of large data volume and high timeliness of single information transmission. Therefore, when the CPU processing module of any one of the two communicating controllers calls the received information stored in the memory module, the information type can be distinguished and correspondingly analyzed according to the position of the written data segment, the information type does not need to be judged again, and the analyzing and processing efficiency is further improved.
5. When any one of the two communicating controllers is switched from a received information state to a sent information state, the CPU processing module needs to decode the called received information by a full data segment, so that the condition that the analysis of only a part of data segments is easy to cause wrong time analysis of counting bits or a second data segment is avoided, and the integrity and the accuracy of information analysis are ensured.
6. The CPU processing module feeds back the processing result of the received information to the memory module for storage or sends the processing result to another controller according to the feedback requirement.
7. The two communication controllers are respectively a first controller and a second controller, the first controller is used for switching the information transceiving state when the carrier signal reaches a preset amplitude value, and sending a corresponding state switching instruction to the second controller according to the switched state, so that the second controller correspondingly switches the information transceiving state after receiving the state switching instruction; so as to ensure that when any one of the two controllers is in the information sending state, the other controller is synchronously in the information receiving state.
The control mode takes a first controller as a main control, and a second controller as a controlled control; the first controller can timely switch the receiving and sending states of the information according to the amplitude change of the carrier signal, the control logic of the whole state switching is simple and easy to realize, and the high-efficiency transmission of information mutual transmission is not influenced.
8. If the length of the information to be sent stored in the first controller is far longer than that of the information to be sent in the second controller, when the carrier wave reaches the preset amplitude and the first controller is switched from the information receiving state to the information sending state, the sending period of the first controller can be prolonged by prolonging the interval period when the carrier wave signal reaches the preset amplitude again, and the information to be sent of the first controller can be completely transmitted each time. And when the carrier signal reaches the preset amplitude and the first controller is switched from the information sending state to the information receiving state, the sending period of the second controller can be shortened by compressing the interval period when the carrier signal reaches the preset amplitude again, so that the information to be sent of the second controller can be completely transmitted.
Similarly, if the length of the information to be transmitted stored in the first controller is much smaller than that of the information to be transmitted in the second controller, when the carrier wave reaches the predetermined amplitude and the first controller is switched from the information receiving state to the information transmitting state, the transmission period of the first controller can be compressed by compressing the interval period when the carrier wave signal reaches the predetermined amplitude again, so that the information to be transmitted of the first controller can be completely transmitted. And when the carrier signal reaches the preset amplitude and the first controller is switched from the information sending state to the information receiving state, the sending period of the second controller can be prolonged by prolonging the interval period when the carrier signal reaches the preset amplitude again, and the information to be sent of the second controller can be completely transmitted each time.
In summary, the interval period when the carrier signal reaches the predetermined amplitude is adjusted according to the data amount of the information to be transmitted in the two controllers, so as to reasonably allocate the respective transmission periods of the two controllers, and improve the transmission efficiency between the two controllers on the premise of ensuring complete information transmission.
9. The carrier signal has a predetermined amplitude of zero value and a peak value, that is, the controller for sending information is switched each time the carrier signal reaches the zero value and the peak value, so that the two communicating controllers can alternately send information to realize mutual information transmission between the two controllers.
10. The McBSP communication module of each controller comprises a sending register and a receiving register, wherein the sending register is used for receiving information to be sent by the memory module of the sending register, and the receiving register is used for sending the information received by the other controller to the memory module of the receiving register. Namely, the McBSP communication module is respectively provided with two registers for sending or receiving information to another controller so as to form two independent receiving and sending channels for convenient control and can utilize the transmission space of each channel with the maximum efficiency. .
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a connection relationship between two DSP controllers according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a transmit-receive timing sequence for mutual information transmission according to an embodiment of the present invention;
fig. 3 is a logic diagram of an information sending process according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are presently preferred embodiments of the invention and are not to be taken as an exclusion of other embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the claims, the specification and the drawings of the present invention, unless otherwise expressly limited, the terms "first", "second" or "third", etc. are used for distinguishing between different items and not for describing a particular sequence.
In the claims, the specification and the drawings of the present invention, unless otherwise expressly limited, all directional or positional relationships indicated by the terms "center," "lateral," "longitudinal," "horizontal," "vertical," "top," "bottom," "inner," "outer," "upper," "lower," "front," "rear," "left," "right," "clockwise," "counterclockwise," and the like are based on the directional or positional relationships indicated in the drawings and are used for convenience in describing the present invention and for simplicity in description, but do not indicate or imply that the device or element so indicated must have a particular orientation or be constructed and operated in a particular orientation, and therefore should not be construed as limiting the scope of the present invention.
In the claims, the description and the drawings of the present application, unless otherwise expressly limited, the terms "fixedly connected" or "fixedly connected" should be interpreted broadly, that is, any connection between the two that does not have a relative rotational or translational relationship, that is, non-detachably fixed, integrally connected, and fixedly connected by other devices or elements.
In the claims, the specification and the drawings of the present invention, the terms "including", "having" and their variants, if used, are intended to be inclusive and not limiting.
Referring to fig. 1, fig. 1 shows a connection relationship between two DSP controllers in an embodiment of the present invention, in this embodiment, the two controllers are a first controller and a second controller, respectively; the carrier signals of the first controller and the second controller are synchronized.
The first controller and the second controller are respectively provided with an McBSP communication module, a DMA channel, a memory module, a CPU processing module and a chip selection counter; the McBSP communication module comprises a sending register and a receiving register, and the DMA channel comprises a sending channel and a receiving channel.
In the first controller or the second controller, a sending register of an McBSP communication module is connected with a memory module through a sending channel of a DMA channel, and a receiving register of the McBSP communication module is connected with the memory module through a receiving channel of the DMA channel; the CPU processing module is connected with the memory module. When the DAM channel occupies bus resources, each controller interrupts the main control of the CPU processing module, and counts the interrupt times of the main control of the CPU processing module through a chip selection counter.
The McBSP communication modules of the two communicating controllers are communicated with each other, so that the two controllers establish a communication relationship to transmit information to each other; the CPU master control interrupt system and the CPU master control interrupt system are provided with a memory module, wherein the memory module is used for storing information to be sent, which needs to be mutually transmitted, the information to be sent comprises strong aging information which needs to be sent every time the CPU master control interrupt system and weak aging information which can be sent at intervals of a plurality of interrupts, the strong aging information comprises information such as fast protection logic data and the like, and the weak aging information comprises information such as slow protection logic data or effective value data and the like.
Specifically, a sending register of the McBSP communication module in the first controller is connected with a receiving register of the McBSP communication module in the second controller, and a receiving register of the McBSP communication module in the first controller is connected with a sending register of the McBSP communication module in the second controller.
Referring to fig. 2, fig. 2 shows a transceiving timing sequence in the process of information mutual transmission between the first controller and the second controller in this embodiment. In this embodiment, the following information mutual transmission method is adopted for information transmission between the first controller and the second controller, and specifically includes the following steps:
the carrier signals of the first controller and the second controller are synchronized, and in the embodiment, the predetermined amplitudes of the carrier signals are zero 0 and peak 1.
As shown in fig. 2, during the period when the carrier signal rises from a predetermined amplitude zero value of 0 to a peak value of 1, the first controller sends information to the second controller through its McBSP communication module; and the second controller synchronously receives the information through the McBSP communication module before the carrier signal reaches the preset amplitude peak value 1 and synchronously stores the received information.
Switching a controller for transmitting information when the carrier signal reaches a predetermined amplitude peak value 1; in this embodiment, the first controller is switched from the information sending state to the information receiving state, and sends a corresponding state switching instruction to the second controller; and after receiving the state switching instruction, the second controller switches the information receiving state into the information sending state.
During the period that the carrier signal is reduced to zero value 0 from the preset amplitude peak value 1, the second controller sends information to the first controller through the McBSP thereof, and the first controller synchronously receives the information through the McBSP communication module thereof and synchronously stores the received information.
When the carrier signal reaches a preset amplitude value of zero 0, the first controller is switched from an information receiving state to an information sending state, and sends a corresponding state switching instruction to the second controller; and after receiving the state switching instruction, the second controller switches the information sending state into the information receiving state.
The carrier signals of the first controller and the second controller are synchronous, that is, the amplitude of the carrier signals of the first controller and the second controller at any time point is ensured to be the same, and when the amplitude of the carrier signals of the first controller and the second controller reaches a preset amplitude, the receiving and sending states of the two controllers can be synchronously switched; the first controller and the second controller can alternately send information to realize information transmission between the first controller and the second controller, and ensure that any one of the two controllers is in an information sending state and the other controller is synchronously in an information receiving state; the situation that two controllers send or receive at the same time is avoided, and the accuracy of information mutual transmission is ensured. In this embodiment, the control mode uses the first controller as a master control, and the second controller as a slave control; the first controller can switch the information receiving and sending states in time according to the amplitude change of the carrier signal, and correspondingly switch the information receiving and sending states of the second controller, the control logic of the whole state switching is simple and easy to realize, and the high-efficiency transmission in the information mutual transmission process is not influenced.
Specifically, after a first controller or a second controller in the two communicating controllers is switched from a message sending state to a message receiving state, the McBSP communication module receives messages and transmits the received messages to the memory module for storage through the receiving channel of the DMA channel. The controller synchronously stores the received information in the process of receiving the information so as to avoid occupying the cache space of the receiving register in the McBSP communication module for a long time and further improve the communication efficiency.
When the first controller or the second controller in the two communication controllers is switched from the information receiving state to the information sending state, the DMA channel occupies bus resources and interrupts the main control of the CPU processing module, and the interrupt times of the main control of the CPU processing module are accumulated and counted by the chip selection counter.
Specifically, the information to be sent stored in the memory module is packaged and encoded into a data format suitable for being received by the McBSP communication module; and the memory module transmits each information to be transmitted after the packaging and encoding to the transmission register of the McBSP communication module through the transmission channel of the DMA channel. During the period of transmitting the information to the McBSP communication module through the DMA channel, the transmitting register of the McBSP communication module correspondingly transmits the information received by the memory module to the receiving register of the McBSP communication module of the second controller or the first controller. And the memory module stores the received information for the CPU processing module to call during the main control interruption period of the CPU processing module.
The first controller and the second controller can directly read each information to be sent stored in the memory module of the first controller and the second controller through the DMA channel without other intermediate media; and the DMA module directly occupies the bus address, so that each information to be sent can be directly sent to the corresponding receiving address in the McBSP communication module from the storage address in the memory module, and the information transmission efficiency in the single controller is greatly improved. Similarly, the information received by the McBSP communication module can be quickly transmitted to the memory module for storage through the DMA channel.
The McBSP communication module of any one of the two communicating controllers sends the information received by the memory module to the McBSP communication module of the other controller, so that two independent receiving and sending channels are formed between the two controllers, and the information transmission with large data volume and high timeliness between the two controllers can be realized. Compared with a conventional IO or SCI communication mode, the data volume which can be transmitted at a single time is greatly increased by receiving and transmitting information through the two connected McBSP communication modules, the communication efficiency in the receiving and transmitting process is high due to the simple communication protocol, and the timeliness of information transmission can be ensured; the independent transceiving paths are convenient to control, and the transmission space of each path can be utilized to the maximum efficiency.
Specifically, the data format suitable for the McBSP communication module to receive and transmit at least comprises a first data segment, a second data segment and counting bits arranged between the first data segment and the second data segment. Writing the strong aging information into the first data segment, writing the current interruption times counting value accumulated by the chip selection counter into the counting bit, and writing the weak aging information required to be sent by the current interruption into the second data segment.
The information with different timeliness requirements is classified and transmitted for multiple times, so that the requirements of large data volume and high timeliness of single information transmission are met. Therefore, when the CPU processing module of any one of the two communicating controllers calls the received information stored in the memory module, the information type can be distinguished and correspondingly analyzed according to the position of the written data segment, the information type does not need to be judged again, and the analyzing and processing efficiency is further improved.
As shown in fig. 3, in this embodiment, when the CPU processing module is in main control interruption for the 1 st time, the strong aging information is fixedly written into the first data segment, the count value 1 is written into the count bit, and the weak aging information that needs to be sent in the current interruption and is determined according to the current interruption count value is written into the second data segment. In the same way, when the CPU processing module is in main control interruption for the 2 nd time, the strong aging information is also fixedly written into the first data segment, the count value 2 obtained by adding 1 to the count value in an accumulated manner is written into the count bit, and the weak aging information to be sent in the current interruption, which is determined according to the current interruption count value, is written into the second data segment. And sending the information according to the mode when the main control is interrupted every time until the information is completely sent by the main control interruption of the CPU processing module at the kth time, and finishing the sending process of the controller. Preferably, the weak aging information written into the second data segment can be marked according to the count value, so that subsequent corresponding identification is facilitated, and the error rate of analysis identification is reduced.
Preferably, if the first controller or the second controller needs to analyze the received information, that is, when the first controller or the second controller switches from the information receiving state to the information sending state, that is, during the period of main control interruption of the CPU, the CPU processing module calls the received information stored by the memory module and performs analysis processing on the full data segment; and the CPU processing module feeds back the processing result of the received information to the memory module.
The CPU processing module calls the memory module to receive complete received information during the period of sending information by the memory module so as to analyze and process the received information in a full data segment; the incomplete information receiving process is not called in the information receiving process of the controller, so that the information is prevented from being mistakenly transmitted, and the accuracy and the integrity of information receiving are ensured; and the condition that the count bit or the second data segment is analyzed at wrong time due to the fact that only partial data segments are analyzed is avoided, and the completeness and the accuracy of information analysis are further guaranteed.
In this embodiment, since the amount of information data to be mutually transmitted between the first controller and the second controller is equivalent, the lengths of the periods for transmitting information by the first controller and the second controller are relatively consistent, and the period for the carrier signal to reach the predetermined amplitude does not need to be adjusted. The first controller can adjust the interval period of the carrier signal reaching the preset amplitude value each time according to the length of the information to be sent stored by the first controller.
Specifically, if the length of the information to be sent stored in the first controller is much longer than that of the information to be sent in the second controller, when the carrier wave reaches the predetermined amplitude and the first controller is switched from the information receiving state to the information sending state, the sending period of the first controller can be prolonged by prolonging the interval period when the carrier wave signal reaches the predetermined amplitude again, so that the information to be sent of the first controller can be completely transmitted each time. And when the carrier signal reaches the preset amplitude and the first controller is switched from the information sending state to the information receiving state, the sending period of the second controller can be shortened by compressing the interval period when the carrier signal reaches the preset amplitude again, and the information to be sent of the second controller can be completely transmitted.
Similarly, if the length of the information to be transmitted stored in the first controller is much smaller than that of the information to be transmitted in the second controller, when the carrier wave reaches the predetermined amplitude and the first controller is switched from the information receiving state to the information transmitting state, the transmission period of the first controller can be compressed by compressing the interval period when the carrier wave signal reaches the predetermined amplitude again, so as to ensure that the information to be transmitted of the first controller can be completely transmitted. And when the carrier signal reaches the preset amplitude and the first controller is switched from the information sending state to the information receiving state, the sending period of the second controller can be prolonged by prolonging the interval period when the carrier signal reaches the preset amplitude again, and the information to be sent of the second controller can be completely transmitted each time.
Therefore, the interval period of the carrier signal reaching the preset amplitude is adjusted according to the data quantity of the information to be transmitted in the two controllers, so that the respective transmission periods of the two controllers are reasonably allocated, and the transmission efficiency between the two controllers is improved on the premise of ensuring complete information transmission.
In summary, the present embodiment provides a DSP information mutual transmission method for a homemade chip, where any two communicating controllers in a parallel system use the information mutual transmission method, and the information mutual transmission method can not only realize large data volume transceiving between the two controllers, but also effectively improve communication efficiency between the two controllers, so as to ensure real-time transmission.
The description of the above specification and examples is intended to be illustrative of the scope of the present invention and is not intended to be limiting. Modifications, equivalents and other improvements which may occur to those skilled in the art and which may be made to the embodiments of the invention or portions thereof through a reasonable analysis, inference or limited experimentation, in light of the common general knowledge, the common general knowledge in the art and/or the prior art, are intended to be within the scope of the invention.
Claims (8)
1. A DSP information mutual transmission method for a domestic chip is applied to more than two DSP controllers and is characterized in that: synchronizing carrier signals of all controllers; each controller is provided with an McBSP communication module, and the McBSP communication modules of the two controllers are communicated with each other so as to establish a communication relationship between the two controllers; which comprises the following steps:
any one of the two communicating controllers sends information by the McBSP communication module; before the carrier signal reaches a preset amplitude value, the other controller synchronously receives information through the McBSP communication module and synchronously stores the received information;
switching a controller for transmitting information when the carrier signal reaches a predetermined amplitude; the preset amplitude of the carrier signal is zero and a peak value; the two communication controllers are respectively a first controller and a second controller; when the carrier signal of the first controller reaches a preset amplitude value, the information receiving and transmitting state of the first controller is switched; and sending a corresponding state switching instruction to the second controller; and after receiving the state switching instruction, the second controller correspondingly switches the information receiving and transmitting states.
2. The DSP information interaction method for a localization chip as claimed in claim 1, characterized in that: the McBSP communication module of each controller is communicated with the memory module thereof through the DMA channel;
the McBSP communication module of any one of the two communicating controllers receives information and transmits the received information to the memory module for storage through the DMA channel;
in the period that the memory module of any one of the two communicating controllers transmits the stored information to be transmitted to the McBSP communication module of the controller through the DMA channel, the McBSP communication module transmits the information received by the memory module to the McBSP communication module of the other controller.
3. The DSP information interaction method for a localization chip as claimed in claim 2, characterized in that: the CPU processing module of each controller is communicated with the memory module;
when any one of the two communicating controllers is switched from a message receiving state to a message sending state, the DMA channel occupies bus resources and interrupts the main control of the CPU processing module; and the received information stored by the memory module is used for being called by the CPU processing module during the main control interruption of the CPU processing module.
4. The DSP information mutual transmission method for a localization chip as claimed in claim 3, characterized in that: each controller carries out accumulated counting on the interruption times of the main control of the CPU processing module by setting a chip selection counter; the information to be sent stored by the memory module comprises strong aging information which needs to be sent during each interruption and weak aging information which can be sent at intervals during a plurality of interruptions;
when any one of the two communicating controllers is switched from a message receiving state to a message sending state, the message to be sent stored by the memory module is packaged and encoded into a data format suitable for being received by the McBSP communication module;
the data format at least comprises a first data segment, a second data segment and counting bits arranged between the first data segment and the second data segment;
and writing the strong aging information into a first data segment, writing the current interruption time count value accumulated by the chip selection counter into a counting bit, and writing the weak aging information required to be sent by the current interruption into a second data segment.
5. The DSP information mutual transmission method for a localization chip as claimed in claim 4, characterized in that: when any one of the two communication controllers is switched from a received information state to a sent information state, the CPU processing module analyzes and processes all data segments of the called received information.
6. The DSP information mutual transmission method for the localization chip as claimed in claim 5, wherein the CPU processing module of any one of the two communication controllers feeds back the processing result of the received information to the memory module.
7. The DSP information interaction method for a localization chip as claimed in claim 1, characterized in that: and the first controller adjusts the interval period of the carrier signal reaching the preset amplitude according to the length of the stored information to be sent.
8. The DSP information interaction method for a localization chip as claimed in claim 1, characterized in that: the McBSP communication module of each controller comprises a sending register and a receiving register; the transmitting register of the McBSP communication module of any one controller of the two communicating controllers is communicated with the receiving register of the McBSP communication module of the other controller.
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