CN103901772B - Two CSTR redundancy inertial platform controller - Google Patents
Two CSTR redundancy inertial platform controller Download PDFInfo
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- CN103901772B CN103901772B CN201410166141.0A CN201410166141A CN103901772B CN 103901772 B CN103901772 B CN 103901772B CN 201410166141 A CN201410166141 A CN 201410166141A CN 103901772 B CN103901772 B CN 103901772B
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Abstract
Two CSTR redundancy inertial platform controller, belongs to platform stabilizing circuit control, phantom ring servo antrol and phantom ring locking control field.In order to the problem that the processor generation fault solving current inertial navigation system causes running owing to lacking spare controller.It comprises A/D convertor circuit, I/O circuit, bus module, power output module, handover module, judging module, the first dsp processor and the second dsp processor; A/D convertor circuit communicates with two dsp processors simultaneously, I/O circuit is communicated with two dsp processors by optocoupler simultaneously, second dsp processor monitors the duty of the first dsp processor by McBSP, judging module is for judging the duty of oneself state and the first dsp processor, handover module switches the first dsp processor and the second dsp processor according to the signal of judging module, power output module is according to switching signal output pwm signal, and bus module is used for the data of received power output module, the first dsp processor and the second dsp processor.It is for the controller of the inertial platform of inertial navigation system.
Description
Technical field
The invention belongs to platform stabilizing circuit control, phantom ring servo antrol and phantom ring locking control field.
Background technology
Being widely used in the inertial platform of inertial navigation system, also claiming gyrostabilized platform, is the vitals in inertial navigation.By setting up the mode of the reference frame that does not affect by aircraft movements on board the aircraft, measure the attitude information of aircraft.The stability of inertial platform, will produce conclusive impact to whole navigational system.
Along with the development of computer technology, at a high speed, the microprocessor of high integration, low cost comes out and rapid article, microprocessor, with its powerful advantages in data operation and control ability, has been widely used in each side such as space flight, navigation, military affairs, industrial automation, traffic, the energy.At present, DSP is widely used in the inertial platform in space industry, in the servo-actuated circuit of servo that platform stabilizing circuit control, phantom ring servo antrol and phantom ring locking control, play great role.
In the servocontrol of inertial platform, due to the defect etc. of various unpredictable external interference or servo control software system, all may cause the problems such as processor deadlock, program fleet, once there is such accident in inertial navigation system, just may cause the massive losses of personnel and financial resources, produce serious consequence.And in traditional controller, once processor breaks down, be just difficult to ensure that the safety and steady of navigational system runs.So in the inertial platform that stability requirement is very high, it is very important for introducing fault-tolerant technique.
Summary of the invention
The processor that the object of the invention is to solve current inertial navigation system produces the problem that fault causes running owing to lacking spare controller, the invention provides a kind of two CSTR redundancy inertial platform controller.
Two CSTR redundancy inertial platform controller of the present invention, described controller comprises A/D convertor circuit, I/O circuit, bus module, power output module, handover module, judging module, the first dsp processor and the second dsp processor;
The gyro digital signal output end of A/D convertor circuit is connected with the gyro digital signal input end of the first dsp processor and the second dsp processor simultaneously, the data output end of I/O circuit is connected with the data input pin of the first dsp processor and the second dsp processor by optocoupler simultaneously, the working state signal output terminal of the first dsp processor is connected with the working state signal input end of the second dsp processor by McBSP, the periodic pulse signal output terminal of the first dsp processor is connected with the periodic pulse signal input end of judging module, first dsp processor fault detection signal output terminal of the second dsp processor is connected with the first dsp processor fault detection signal input end of judging module,
The decision signal output terminal of judging module is connected with the decision signal input end of handover module, the pwm signal input/output terminal of the first dsp processor is connected with the first pwm signal input/output terminal of handover module, the pwm signal input/output terminal of the second dsp processor is connected with the second pwm signal input/output terminal of handover module, the pwm signal output terminal of handover module is connected with the input end of the pwm signal of power output module, the pwm signal output terminal of power output module is connected with the pwm signal input end of bus module
The data input/output terminal of the first dsp processor and the data input/output terminal of the second dsp processor are connected with the first data input/output terminal of bus module and the second data input/output terminal respectively.
Described judging module comprises FPGA module, detection module and combinational logic circuit;
FPGA module, for the pulse signal of the GPIO pin by detection first dsp processor, determines whether the first dsp processor breaks down, and sends the first dsp processor breakdown judge signal to combinational logic circuit;
Whether detection module, break down for detecting FPGA module, and send FPGA module breakdown judge signal to combinational logic circuit;
Combinational logic circuit, for adjudicating according to receiving the first dsp processor fault detection signal that the first dsp processor breakdown judge signal, FPGA module breakdown judge signal and the second dsp processor export, export the decision signal whether the first dsp processor 7 and the second dsp processor switch.
Beneficial effect of the present invention is, two CSTR processor is used to carry out redundancy fault-tolerant design, take full advantage of the powerful advantages of dsp processor in process data on the one hand, high speed is effective to be controlled inertial platform, ensure that permissible accuracy and stability in inertial navigation; Judge whether the first dsp processor 7 normally works by input on the other hand, if combinational logic circuit judges that main frame breaks down, then send a command to handover module, and then realize being switched to the second dsp processor 8 by the first dsp processor 7 when processor breaks down, ensure the safe operation of inertial navigation system.In addition judging module does not detect the first dsp processor 7 by means of only FPGA module, also by the second dsp processor 8, first dsp processor 7 is detected, add simultaneously and detect the detection module of FPGA module, ensure that the reliability to the first dsp processor 7 fault whether judged result.Ensure that the normal table of inertial navigation system runs.
Accompanying drawing explanation
Fig. 1 is the principle schematic of the two CSTR redundancy inertial platform controller described in embodiment one.
The principle schematic of the 4th tunnel access that Fig. 2 is the A/D convertor circuit described in embodiment one.
Fig. 3 is the principle schematic of the I/O circuit described in embodiment one.
Fig. 4 is the principle schematic of the judging module described in embodiment two.
Fig. 5 is the principle schematic of the detection module described in embodiment three.
Fig. 6 is the principle schematic of the combinational logic circuit described in embodiment four.
Fig. 7 is the principle schematic of the handover module 5 described in embodiment seven.
Embodiment
Embodiment one: composition graphs 1, Fig. 2 and Fig. 3 illustrate present embodiment, two CSTR redundancy inertial platform controller described in present embodiment, described controller comprises A/D convertor circuit 1, I/O circuit 2, bus module 3, power output module 4, handover module 5, judging module 6, first dsp processor 7 and the second dsp processor 8;
The gyro digital signal output end of A/D convertor circuit 1 is connected with the gyro digital signal input end of the first dsp processor 7 and the second dsp processor 8 simultaneously, the data output end of I/O circuit 2 is connected with the data input pin of the first dsp processor 7 and the second dsp processor 8 by optocoupler simultaneously, the working state signal output terminal of the first dsp processor 7 is by McBSP (MultichannelBufferedSerialPort, multichannel buffer serial port) be connected with the working state signal input end of the second dsp processor 8, the periodic pulse signal output terminal of the first dsp processor 7 is connected with the periodic pulse signal input end of judging module 6, first dsp processor 7 fault detection signal output terminal of the second dsp processor 8 is connected with the first dsp processor 7 fault detection signal input end of judging module 6,
The decision signal output terminal of judging module 6 is connected with the decision signal input end of handover module 5, the pwm signal input/output terminal of the first dsp processor 7 is connected with the first pwm signal input/output terminal of handover module 5, the pwm signal input/output terminal of the second dsp processor 8 is connected with the second pwm signal input/output terminal of handover module 5, the pwm signal output terminal of handover module 5 is connected with the input end of the pwm signal of power output module 4, the pwm signal output terminal of power output module 4 is connected with the pwm signal input end of bus module 3
The data input/output terminal of the first dsp processor 7 and the data input/output terminal of the second dsp processor 8 are connected with the first data input/output terminal of bus module 3 and the second data input/output terminal respectively.
In present embodiment, using original DSP as the first dsp processor 7, increase a slice DSP and realize principal and subordinate's Redundancy Design as the second dsp processor 8, first dsp processor 7 and the second dsp processor 8.
A/D convertor circuit 1 by the three gyrostatic analog input amounts in road respectively by two independently A/D chip carry out parallel access first dsp processor 7 and the second dsp processor 8 after analog to digital conversion, the signal of each passage adopts isolation design, avoids occurring coupled relation; 5V voltage is received on 4th tunnel of AD, compares through conversion, judge that whether AD is normal.As shown in Figure 2.
In the I/O circuit 2 of present embodiment, 1ms bus timing look-at-me and four road IO control signals walk abreast and are linked into the GPIO (GeneralPurposeInputOutput of the first dsp processor 7 and the second dsp processor 8, general input/output port) in, the 3.3VIO level match of the GPIO of outside 5V level and dsp processor is guaranteed, as shown in Figure 3 by light-coupled isolation.
In present embodiment, handover module is realized by stage switching circuit, the selection signal deciding produced by judging module exports the pwm signal of which dsp processor, if it is 0 that judging module exports, then export the pwm signal of the first dsp processor 7, if Combinational logic output is 1, then export the pwm signal of the second dsp processor 8.
Embodiment two: composition graphs 4 illustrates present embodiment, present embodiment is the further restriction to the two CSTR redundancy inertial platform controller described in embodiment one, and described judging module 6 comprises FPGA module, detection module and combinational logic circuit;
FPGA module, for the pulse signal of the GPIO pin by detection first dsp processor 7, determines whether the first dsp processor 7 breaks down, and sends the first dsp processor 7 breakdown judge signal to combinational logic circuit;
Whether detection module, break down for detecting FPGA module, and send FPGA module breakdown judge signal to combinational logic circuit;
Combinational logic circuit, for adjudicating according to receiving the first dsp processor 7 fault detection signal that the first dsp processor 7 breakdown judge signal, FPGA module breakdown judge signal and the second dsp processor 8 export, export the decision signal whether the first dsp processor 7 and the second dsp processor 8 switch.
The GPIO pin of the first dsp processor 7 is detected by FPGA module, second dsp processor 8 is by McBSP (MultichannelBufferedSerialPort, multichannel buffer serial port) monitor the working condition of the first dsp processor 7, once FPGA module and the second dsp processor 8 detect that the first dsp processor 7 breaks down simultaneously, then be switched to the second dsp processor 8 and carry out work, and run, no longer switch; always In order to prevent the impact of damage meeting on bringing on a disaster property of whole system of FPGA module itself, by detection module, FPGA module is detected again, if FPGA is working properly, then its I/O port exports the pulse in a 1ms cycle, the whether normal of this pulse can be able to be detected by detection module, and then whether judges FPGA module fault; FPGA module to the testing result of the first dsp processor, testing circuit to the testing result of FPGA module and the second dsp processor 8 to the testing result of the first dsp processor 7 by combinational logic circuit draw whether carry out that the first dsp processor 7 and the second dsp processor 8 switch conclusion.
Embodiment three: composition graphs 5 illustrates present embodiment, present embodiment is the further restriction to the two CSTR redundancy inertial platform controller described in embodiment two, described detection module is monostalbe trigger circuit, and adopts monostalbe trigger SN54LS123J to realize.
As shown in Figure 7, detect FPGA module by Retargetable compiler monostalbe trigger 74LS123 whether to break down.When being input as clock signal, the inverse output terminal mouth of trigger can produce negative pulse, and additional capacitance-resistance value can be regulated to set the width of negative pulse.When negative pulse width is greater than the one-period of input clock and is less than two cycles, its inverse output terminal mouth is no longer negative pulse train, but a low level.When low and high level change no longer occurs suddenly input clock signal, in the end a negative pulse terminates rear redirect to its inverse output terminal mouth is high level.
Embodiment four: composition graphs 6 illustrates present embodiment, present embodiment is the further restriction to the two CSTR redundancy inertial platform controller described in embodiment two, and combinational logic circuit comprises a Sheffer stroke gate and a rejection gate; The first dsp processor 7 fault detection signal that first dsp processor 7 breakdown judge signal and the second dsp processor 8 export inputs to two input ends of Sheffer stroke gate respectively, the output signal of Sheffer stroke gate and FPGA module breakdown judge signal input to two input ends of rejection gate respectively, and rejection gate exports the decision signal whether the first dsp processor 7 and the second dsp processor 8 switch.
Corresponding to the function realizing combinational logic circuit, a Sheffer stroke gate CD4011BF and rejection gate CD4001BF is adopted to realize.
Embodiment five: present embodiment is the further restriction to the two CSTR redundancy inertial platform controller described in embodiment four, a is the true value of the first dsp processor 7 breakdown judge signal that FPGA module exports, b is the true value of the FPGA module breakdown judge signal that detection module exports, c is the true value of the first dsp processor 7 fault detection signal that the second dsp processor 8 exports, f is the true value of the decision signal whether the first dsp processor 7 and the second dsp processor 8 switch, when a or b or c is low level, represent that current judged result is trouble-free, otherwise then for there being fault, when f is high level, represent switching first dsp processor 7 and the second dsp processor 8, namely the second dsp processor 8 is replaced the first dsp processor 7 and is worked.
In present embodiment, when for low level, represent that current judged result is trouble-free, otherwise then for there being fault.A, b and c tri-judge signal, after entering combinational logic circuit, obtain total judgement to export, this judgement exports can be designated as f, f then drives change-over switch, completes the switching of PWM output signal, when f is low level, export the pwm signal of the first dsp processor 7, otherwise output is the pwm signal of the second dsp processor 8.The combined expression of f is
the truth table of described combinational logic circuit is:
The truth table of table 1 combinational logic circuit
Embodiment six: present embodiment is the further restriction to the two CSTR redundancy inertial platform controller described in embodiment one, and described bus module 3 is RS422/RS485 bus module.
In RS422/RS485 bus module, RS485 and RS422 bus after level transferring chip, then passes through light-coupled isolation, then two SCI modules of F2812 are inputed to, RS485 adopts one-way transmission mode, only receives and does not send out, and increases electric current and drive between Max485 and optocoupler; RS422 adopts bus carry form, the serial ports of two panels DSP exports after light-coupled isolation and level conversion, and direct carry is in RS422 bus, and two-way RS422 can receive data simultaneously, but once can only have one and be in transmission state, the Enable Pin of transmission is controlled by the GPIO of DSP.
Embodiment seven: composition graphs 7 illustrates present embodiment, present embodiment is the further restriction to the two CSTR redundancy inertial platform controller described in embodiment one, and described handover module 5 adopts chip SN54517 to realize.
Embodiment eight: composition graphs 7 illustrates present embodiment, present embodiment is the further restriction to the two CSTR redundancy inertial platform controller described in embodiment seven, and described power output module 4 comprises power device MSK4201 and filtering buffer circuit; The pwm signal that handover module 5 exports inputs to power device MSK4201 after optocoupler, and the pwm signal that power device MSK4201 exports inputs to filtering buffer circuit.
The pwm signal of two DSP, is first selected by chip SN54157, then isolates through 6N137 optocoupler, because the output current of SN54157 can reach 16mA, and can Direct driver optocoupler.Pwm signal, through optocoupler rear drive power device MSK4201, at power output stage, then with reference to original motor-drive circuit, adds filtering and buffer circuit.
It is of the present invention that to realize the implementation procedure that the first dsp processor 7 and the second dsp processor carry out switching as follows:
The first step, 5V voltage is received on 4th tunnel of A/D convertor circuit 1, A/D convertor circuit 1 the 4th circuit-switched data is delivered to the first dsp processor 7, the digital quantity corresponding with known 5V of the data volume after the 4th tunnel conversion is utilized to compare, if in certain threshold value, then the first dsp processor 7 judges that AD is normal, if comparative result exceeds certain threshold value, then the first dsp processor 7 judges that exception appears in A/D convertor circuit 1.
Second step, the GPIO pin detecting the first dsp processor 7 by FPGA module exports, under normal circumstances, the GPIO pin of the first dsp processor 7 can export the pulse that the cycle is 1ms, if the first dsp processor 7 detects that A/D convertor circuit 1 breaks down or himself breaks down in the first step, then the first dsp processor 7 no longer sends this pulse to FPGA module, and judges that the breakdown judge signal of the first dsp processor 7 becomes high level.
Simultaneously, second dsp processor 8 monitors the first dsp processor 7 by McBSP, first dsp processor 7 often sends a signal to the second dsp processor 8, and the just set again of the timer 0 in the second dsp processor 8, whether the first dsp processor 7 breaks down to utilize timer 0 to detect.If the second dsp processor 8 detects that the first dsp processor 7 breaks down or himself breaks down, then judge that the FPGA module breakdown judge signal that detection module exports becomes high level.
3rd step, the 1ms recurrent pulse that the I/O port detecting FPGA module by Retargetable compiler monostalbe trigger exports, when FPGA module is normal, monostalbe trigger output low level, when FPGA module occurs abnormal, its I/O port no longer exports recurrent pulse, and in the end a negative pulse terminates rear redirect to monostalbe trigger delivery outlet is high level, judges that the first dsp processor 7 fault detection signal that the second dsp processor 8 exports also is the outputs level signals of monostalbe trigger.
By a, b and c tri-that second step and the 3rd step obtain, 4th step, judges that Signal transmissions is to combinational logic circuit, obtain total judgement export f through combinational logic computing.
5th step, decision signal f drives change-over switch, completes the switching of PWM output signal, exports the pwm signal of the first dsp processor 7 when f is 0, on the contrary the pwm signal of defeated second dsp processor 8.
Claims (7)
1. two CSTR redundancy inertial platform controller, described controller comprises A/D convertor circuit (1), I/O circuit (2), bus module (3), power output module (4), handover module (5), judging module (6), the first dsp processor (7) and the second dsp processor (8);
The gyro digital signal output end of A/D convertor circuit (1) is connected with the gyro digital signal input end of the first dsp processor (7) and the second dsp processor (8) simultaneously, the data output end of I/O circuit (2) is connected with the data input pin of the first dsp processor (7) and the second dsp processor (8) by optocoupler simultaneously, the working state signal output terminal of the first dsp processor (7) is connected with the working state signal input end of the second dsp processor (8) by McBSP, the periodic pulse signal output terminal of the first dsp processor (7) is connected with the periodic pulse signal input end of judging module (6), first dsp processor fault detection signal output terminal of the second dsp processor (8) is connected with the first dsp processor fault detection signal input end of judging module (6),
The decision signal output terminal of judging module (6) is connected with the decision signal input end of handover module (5), the pwm signal input/output terminal of the first dsp processor (7) is connected with the first pwm signal input/output terminal of handover module (5), the pwm signal input/output terminal of the second dsp processor (8) is connected with the second pwm signal input/output terminal of handover module (5), the pwm signal output terminal of handover module (5) is connected with the input end of the pwm signal of power output module (4), the pwm signal output terminal of power output module (4) is connected with the pwm signal input end of bus module (3),
The data input/output terminal of the first dsp processor (7) and the data input/output terminal of the second dsp processor (8) are connected with the first data input/output terminal of bus module (3) and the second data input/output terminal respectively;
It is characterized in that, described judging module (6) comprises FPGA module, detection module and combinational logic circuit;
FPGA module, for the pulse signal of the GPIO pin by detection first dsp processor, determines whether the first dsp processor breaks down, and sends the first dsp processor breakdown judge signal to combinational logic circuit;
Whether detection module, break down for detecting FPGA module, and send FPGA module breakdown judge signal to combinational logic circuit;
Combinational logic circuit, for adjudicating according to receiving the first dsp processor fault detection signal that the first dsp processor breakdown judge signal, FPGA module breakdown judge signal and the second dsp processor (8) export, export the decision signal whether the first dsp processor (7) and the second dsp processor (8) switch.
2. two CSTR redundancy inertial platform controller according to claim 1, it is characterized in that, described detection module is monostalbe trigger circuit, and adopts monostalbe trigger SN54LS123J to realize.
3. two CSTR redundancy inertial platform controller according to claim 1, is characterized in that, combinational logic circuit comprises a Sheffer stroke gate and a rejection gate; The first dsp processor fault detection signal that first dsp processor breakdown judge signal and the second dsp processor (8) export inputs to two input ends of Sheffer stroke gate respectively, the output signal of Sheffer stroke gate and FPGA module breakdown judge signal input to two input ends of rejection gate respectively, and rejection gate exports the decision signal whether the first dsp processor (7) and the second dsp processor (8) switch.
4. two CSTR redundancy inertial platform controller according to claim 3, it is characterized in that, the truth table of described combinational logic circuit is:
The truth table of combinational logic circuit
A is the true value of the first dsp processor breakdown judge signal that FPGA module exports, b is the true value of the FPGA module breakdown judge signal that detection module exports, c is the true value of the first dsp processor fault detection signal that the second dsp processor (8) exports, f is the true value of the decision signal whether the first dsp processor (7) and the second dsp processor (8) switch
when a, b or c are low level, represent that current judged result is trouble-free, otherwise then for there being fault, when f is high level, represent switching first dsp processor (7) and the second dsp processor (8), namely the second dsp processor (8) replaces the first dsp processor (7) work.
5. two CSTR redundancy inertial platform controller according to claim 1, is characterized in that, described bus module (3) is RS422/RS485 bus module.
6. two CSTR redundancy inertial platform controller according to claim 1, is characterized in that, described handover module (5) adopts chip SN54517 to realize.
7. two CSTR redundancy inertial platform controller according to claim 6, it is characterized in that, described power output module (4) comprises power device MSK4201 and filtering buffer circuit; The pwm signal that handover module (5) exports inputs to power device MSK4201 after optocoupler, and the pwm signal that power device MSK4201 exports inputs to filtering buffer circuit.
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