CN111679170B - Transistor array structure design method based on reliability rapid test - Google Patents
Transistor array structure design method based on reliability rapid test Download PDFInfo
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- CN111679170B CN111679170B CN202010518365.9A CN202010518365A CN111679170B CN 111679170 B CN111679170 B CN 111679170B CN 202010518365 A CN202010518365 A CN 202010518365A CN 111679170 B CN111679170 B CN 111679170B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
Abstract
The invention discloses a transistor array structure design method based on reliability rapid test, which adopts a metal-oxide-semiconductor field effect transistor as a single tube structure; and carrying out matrix arrangement on a plurality of single tube structures, respectively carrying out treatment of a local shared grid and a local shared drain, respectively carrying out overall public connection on a source electrode and a substrate to form a transistor array structure, and carrying out reliability test on the array structure. The invention obviously reduces the number of the pad structures for testing, obviously improves the overall utilization rate of the wafer, can freely select devices in a large area for testing according to different requirements, realizes the optimized utilization of the testing time, radically shortens the testing period greatly and achieves the effect of rapid testing.
Description
Technical Field
The invention belongs to the field of semiconductor device testing, and particularly relates to a method for designing a transistor array test structure to quickly complete reliability testing when meeting the reliability testing requirement of a semiconductor device.
Background
The conventional integrated circuit generally refers to a semiconductor integrated circuit, which is a miniaturized circuit produced by using a semiconductor material (Si, Ge, etc.) as a substrate and integrating electronic components, active devices and metal interconnections inside the substrate, on the surface of the substrate or on the substrate through a series of processes, so as to meet the functional requirements of a specific circuit or system. Under the continuous development of moore's law, the feature size of an integrated circuit device is continuously reduced, the number of metal wiring layers is increased, the related reliability requirements are continuously improved, and the reliability test is always an indispensable part of main processes related to integrated circuit design, process development, product production and the like for the integrated circuit. According to international universal standards, the service life of common electronic products must be longer than 10 years, and the reliability evaluation generally adopts an accelerated stress test mode, namely, under abnormal working conditions (such as high temperature and high pressure), device reliability data is obtained in a short time, then, the reliability of the device is evaluated according to a failure mechanism, a mathematical physical model is established, and the service life of the device under normal working conditions is calculated.
In actual tests, the existing device reliability test method is generally a single-tube test, one reliability test period of each MOSFET test structure is generally more than 10000s, and a mass production period is occupied for a pretest chip which needs to obtain a result quickly. In addition, basic characteristic tests are carried out at the early stage of the reliability test, a needle inserting path is re-planned according to the integration level on the circle in the test, the needle raising time and the needle inserting time are small in midway, if the needle raising time and the needle inserting time are multiplied by the total number of the tests, a lot of test time is occupied, the needle inserting depths of different devices cannot be guaranteed to be the same, and uncertainty is increased for the result of the reliability test. Therefore, the present invention proposes a transistor array design that significantly contributes to a reduction in reliability test cycle.
Disclosure of Invention
The invention aims to provide a transistor array structure design method based on a reliability quick test, aiming at the defects of the existing reliability test period.
The purpose of the invention is realized by the following technical scheme: a transistor array structure design method based on reliability rapid test comprises the following steps:
(1) the metal-oxide-semiconductor field effect transistor MOSFET is used as a single tube structure.
(2) The method comprises the following steps of carrying out matrix arrangement on a plurality of single-tube structures, and respectively carrying out treatment of a local shared grid and a local shared drain, namely, the grids of the single-tube structures in the same physical column are connected in common through a metal connecting wire and connected to a test pad end of the grid, and the drains of the single-tube structures in the same physical row are connected in common through the metal connecting wire and connected to a test pad end of the drain; and respectively and commonly connecting the source electrode and the substrate, namely commonly connecting the source electrodes of all the single-tube structures through metal connecting wires and connecting the source electrodes to the testing pad end of the source electrode, and connecting the substrates of all the single-tube structures to each other through the metal connecting wires and connecting the substrates to the testing pad end of the substrate to form the transistor array structure.
(3) When the reliability test is carried out, grid stress is applied to a grid pad end of the array structure, drain stress is applied to a drain pad end, and the source pad end and a substrate pad end are grounded or 0V voltage is used for testing.
Further, in the step (1), the technology node of the metal-oxide-semiconductor field effect transistor includes, but is not limited to, 40nm and 55 nm.
Further, in the step (1), the semiconductor layer of the metal-oxide-semiconductor field effect transistor includes, but is not limited to, a silicon substrate, a germanium substrate, and a silicon germanium substrate.
Further, in the step (1), the oxide layer of the metal-oxide-semiconductor field effect transistor includes, but is not limited to, a silicon oxide layer, an aluminum oxide layer, and a silicon oxynitride layer.
Further, in the step (1), the metal-oxide-semiconductor field effect transistor should have a structure capable of connecting the gate, the drain, the source and the substrate to the pad terminal through metal wires.
Further, the layout drawing and subsequent design checking and level checking software includes, but is not limited to, Cadence Virtuoso and Calibre MDP.
Further, the design checking method includes, but is not limited to, design rule checking, electrical rule checking, layout-to-schematic comparison, design manufacturability checking, and the like.
Further, in the step (2), the single-tube structures composing the same transistor array are generated in the same batch, and the structure, size and orientation thereof need to be consistent, and only the metal connection lines are allowed to have differences.
Further, in the step (2), the number of pads required by the m × n array structure is m + n +2, and if the number of required pads is 4 × m × n calculated by the same number of single-tube structures, the number of required pads can be greatly reduced by the array structure, and the occupied wafer area is optimized.
Further, in the step (3), the reliability test includes, but is not limited to, a hot carrier injection effect test, a negative bias voltage instability test, and the like.
The invention has the beneficial effects that: 1. because the devices are densely arranged in an array form, the occupied area is greatly reduced, and the overall utilization rate of the wafer is obviously improved; 2. the special connection form of sharing the drain electrode by a physical row, sharing the grid electrode by a physical column and commonly grounding the source electrode and the substrate enables call of the pad structure for testing to be obviously reduced, and the probe structure corresponding to the pad structure is designed to eliminate the links of raising and pricking the device in the whole testing process and realize the optimized utilization of testing time; 3. the array structure can ensure that all devices can be pressurized simultaneously in the true sense under the condition that the same stress output is provided by a test instrument, devices in a large area can be freely selected according to different requirements for testing, test results in the area are output in batches, and the test period is radically shortened. The invention has wide application prospect in the field of reliability test of mass transistors in the integrated circuit industry.
Drawings
Fig. 1 is a schematic structural diagram of a cell transistor according to the present invention.
Fig. 2 is a schematic structural diagram of the array transistor according to the present invention.
Fig. 3 is a schematic structural diagram of the single transistor structure connected to the pad terminal according to the present invention.
FIG. 4 is a schematic diagram of the transistor array structure of the present invention connected to the pad terminal.
FIG. 5 is a schematic diagram of the input and output of each part in the hot carrier effect reliability test using the array structure according to an embodiment of the present invention.
In the figure, a gate G, a drain D, a source S, a substrate B, a test pad, an Array structure Array, and a gate stress VGDrain stress VDDrain current IDSubstrate current IBThreshold voltage VTAnd is grounded GND.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
The application provides a transistor array structure design method based on reliability rapid test, which comprises the following steps:
(1) the metal-oxide-semiconductor field effect transistor MOSFET is used as a single tube structure.
(2) The method comprises the following steps of carrying out matrix arrangement on a plurality of single-tube structures, and respectively carrying out treatment of a local shared grid and a local shared drain, namely, the grids of the single-tube structures in the same physical column are connected in common through a metal connecting wire and connected to a test pad end of the grid, and the drains of the single-tube structures in the same physical row are connected in common through the metal connecting wire and connected to a test pad end of the drain; in addition, the source electrodes and the substrates are respectively connected in common, namely the source electrodes of all the single-tube structures are connected in common through metal connecting wires and connected to the testing pad ends of the source electrodes, and the substrates of all the single-tube structures are connected in parallel through the metal connecting wires and connected to the testing pad ends of the substrates to form the transistor array structure in an m x n mode.
(3) In the reliability test, usually, a gate stress is applied to a gate pad end of the array structure, a drain stress is applied to a drain pad end, and a source pad end and a substrate pad end are grounded or a 0V voltage is applied to perform the test.
Further, in the step (1), the technology node of the metal-oxide-semiconductor field effect transistor includes, but is not limited to, 40nm and 55 nm.
Further, in the step (1), the semiconductor layer of the metal-oxide-semiconductor field effect transistor includes, but is not limited to, a silicon substrate, a germanium substrate, and a silicon germanium substrate.
Further, in the step (1), the oxide layer of the metal-oxide-semiconductor field effect transistor includes, but is not limited to, a silicon oxide layer, an aluminum oxide layer, and a silicon oxynitride layer.
Further, in the step (1), the metal-oxide-semiconductor field effect transistor should have a structure capable of connecting the gate, the drain, the source and the substrate to the pad terminal through metal wires.
Further, in the step (2), a lot of designed single-tube structures are placed through layout drawing software, the relative positions on the layout are taken as standards, the local common grid and the local common drain are respectively processed, and the source and the substrate are respectively connected in a whole common mode to form the transistor array structure.
Further, the layout drawing and subsequent level checking and design checking software includes, but is not limited to, Cadence Virtuoso and Calibre MDP.
Further, the design checking method includes, but is not limited to, design rule checking, electrical rule checking, layout-to-schematic comparison, design manufacturability checking, and the like.
Further, in the step (2), the single-tube structures composing the same transistor array are generated in the same batch, and the structure, size and orientation thereof need to be consistent, and only the metal connection lines are allowed to have differences.
Further, in the step (2), the total required number of pads of the array structure is m + n +2, and if the number of the required pads is calculated according to the same number of single-tube structures, the required number of the pads is 4 m n, so that the number of pad ends required by adopting the array structure is greatly reduced, and the occupied wafer area is also optimized.
Further, in the step (3), the reliability test includes, but is not limited to, a hot carrier injection effect test, a negative bias voltage instability test, and the like.
Fig. 1 is a schematic diagram of a single transistor structure according to the present invention. The structure of the transistor comprises four input and output ends, namely a grid electrode, a drain electrode, a source electrode and a substrate, can be an N-type metal oxide semiconductor or a P-type metal oxide semiconductor, and is required to work normally under the condition of applying normal stress.
Fig. 2 is a schematic diagram of a transistor array structure according to the present invention. And respectively processing a local shared grid and a local shared drain on a batch of single-tube structures, and respectively and commonly connecting the source and the substrate to form an m x n-shaped transistor array structure, wherein originally required 4 x m x n pad ends are reduced to m + n +2 pad ends, so that resources are optimized.
Fig. 3 is a schematic structural diagram of the single transistor structure connected to the pad terminal according to the present invention. Typically 1 unit under test contains 12 pads and 1 single-tube structure contains G, D, S, B four inputs and outputs that need to be externally connected to the pad terminals, so that a maximum of 3 single-tube structures can be placed in 1 unit under test.
FIG. 4 is a schematic diagram of the transistor array structure of the present invention connected to the pad terminal. The maximum 5 x 5 transistor array structure can be theoretically placed in 1 test unit, and the structure comprises 5 grids, 5 drains, 1 source and 1 substrate input and output end. Therefore, in a test period, compared with the simultaneous test of 3 transistors tested by single tubes, the array structure can allow the stress application test of 25 transistors simultaneously during the test, the test efficiency is improved by nearly 8 times, in the aspect of occupied area, more than 8 test units are needed by 25 single tube structures, the array structure only needs 1 test unit, the occupied area is only one eighth, and the production cost is effectively optimized.
Fig. 5 is a schematic diagram illustrating input and output of each part in a hot carrier effect reliability test performed by using an array structure according to an embodiment of the invention. Wherein, by applying an arbitrary V to a specific padGAnd VDThe combined stress is used for basic characteristic test, so that parallel test of a plurality of devices can be realized, and I can be rapidly outputB，ID，VTAnd the like, and when testing the reliability of the hot carrier effect, the failure time TTF of all the devices in the array can be simultaneously obtained through parallel testing, and then model parameters are calculated through a corresponding mathematical physical model and substituted into actual working conditions to calculate and evaluate the service life of the transistors. As the pressurizing time of the reliability test is usually more than 10000s, the use of the array structure can greatly shorten the reliability test time and improve the reliability test efficiency.
The above-described embodiments are merely illustrative of the present invention, and although the best mode of the invention and the drawings are disclosed for illustrative purposes, those skilled in the art will appreciate that: various substitutions, changes and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the disclosure of the preferred embodiments and the accompanying drawings.
Claims (7)
1. A transistor array structure design method based on reliability rapid test is characterized by comprising the following steps:
(1) the metal-oxide-semiconductor field effect transistor MOSFET is used as a single tube structure, the technical node comprises 40nm and 55nm, the semiconductor layer comprises a silicon substrate, a germanium substrate and a silicon-germanium substrate, and the oxide layer comprises a silicon oxide layer, an aluminum oxide layer and a silicon oxynitride layer.
(2) The method comprises the following steps of carrying out matrix arrangement on a plurality of single-tube structures, and respectively carrying out treatment of a local shared grid and a local shared drain, namely, the grids of the single-tube structures in the same physical column are connected in common through a metal connecting wire and connected to a test pad end of the grid, and the drains of the single-tube structures in the same physical row are connected in common through the metal connecting wire and connected to a test pad end of the drain; and respectively and commonly connecting the source electrode and the substrate, namely commonly connecting the source electrodes of all the single-tube structures through metal connecting wires and connecting the source electrodes to the testing pad end of the source electrode, and connecting the substrates of all the single-tube structures to each other through the metal connecting wires and connecting the substrates to the testing pad end of the substrate to form the transistor array structure.
(3) When the reliability test is carried out, grid stress is applied to a grid pad end of the array structure, drain stress is applied to a drain pad end, and the source pad end and a substrate pad end are grounded or 0V voltage is used for testing.
2. The method as claimed in claim 1, wherein in step (1), the metal-oxide-semiconductor field effect transistor has a structure capable of connecting the gate, the drain, the source and the substrate to the pad terminal through metal wires.
3. The transistor array structure design method based on the reliability rapid test as claimed in claim 1, wherein the layout drawing and the subsequent design check and level check software comprise Cadence Virtuoso and Calibre MDP.
4. The transistor array structure design method based on the reliability rapid test as claimed in claim 3, wherein the design check method comprises design rule check, electrical rule check, layout and schematic diagram comparison, design manufacturable check.
5. The method according to claim 1, wherein in the step (2), the single-tube structures forming the same transistor array are generated in the same batch, and the structure, size and orientation thereof need to be consistent, and only the metal connection lines are allowed to have differences.
6. The method according to claim 1, wherein in the step (2), the number of pads required for the m × n array structure is m + n + 2.
7. The method for designing a transistor array structure based on a rapid reliability test as claimed in any one of claims 1 to 6, wherein in the step (3), the reliability test includes but is not limited to a hot carrier injection effect test, a negative bias voltage instability test, and the like.
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| US11892499B2 (en) | 2020-12-21 | 2024-02-06 | Changxin Memory Technologies, Inc. | Testing machine and testing method |
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