CN105185723A - Electric property testing method for semiconductor device - Google Patents
Electric property testing method for semiconductor device Download PDFInfo
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- CN105185723A CN105185723A CN201510662806.1A CN201510662806A CN105185723A CN 105185723 A CN105185723 A CN 105185723A CN 201510662806 A CN201510662806 A CN 201510662806A CN 105185723 A CN105185723 A CN 105185723A
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- semiconductor device
- testing
- electrical property
- drain electrode
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The invention provides an electric property testing method for a semiconductor device. The method includes the following steps: 1. four pins of a source electrode, a drain electrode, a grid electrode and a substrate of a semiconductor are kept equipotential; 2. sequentially turning a diode formed between a drain region and the substrate and a diode formed between a source region and the substrate and releasing charges; 3. releasing charges after forming a conducting channel under a gate oxide; and 4. performing electric property testing on a semiconductor device obtained by the Step 3. According to the electric property testing method for the semiconductor device provided by the invention, bias voltage is loaded on the drain electrode and the source electrode and charges are released, bias voltage is loaded on the grid electrode and the drain electrode and charges are released, finally bias voltage is loaded on the drain electrode, current of the source electrode and the drain electrode in the semiconductor device in a non-working state is measured, charges in the semiconductor device are guaranteed to be released to an extent that influence on an electric property test is extremely small, and the method can eliminate unordered charges in the semiconductor device, thereby improving accuracy of the electric property test.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of semiconductor device electrical property method of testing.
Background technology
Along with the development of IC industry, the demand of user is also to volume littleization, the development of energy consumption lowizationer, and changing into the requirement of design and processes is exactly that characteristic size reduces further, at prerequisite decline low-work voltage and the electric current of retainer member performance.This not only needs more advanced manufacturing process and material, more need more accurately measuring tool and gimmick to judge whether manufacturing process reaches requirement.Such as, after entering 90 nm technology node, the minimum of semiconductor device is only only less than 1 volt, corresponding operating current is then less than 1 μ A, and the leakage current under non operating state is more small enough to pA level, the detection of similar this minimum electric current is very responsive to test condition, and electrostatic and the remaining electric charge in the semiconductor device of crystal column surface and surrounding all can cause very large interference to test result.
For N-type MOS device, gate oxide and polysilicon gate are between source-drain electrode, and the source-drain electrode that N-type is injected is arranged in P type trap isolates mutually with peripheral devices.Semiconductor technology can use electron beam, ion beam apparatus usually; and be distributed in the electrostatic of surrounding environment, after successively technique, in material, storeroom randomly may be dispersed with some free charges; be transmitted to testing equipment end when testing by connecting line, test result is had an impact.
The common way of current semiconductor manufacturing factory is tested the semiconductor device electrical property parameter of FEOL after section line in the completed again, i.e. wafer acceptance testing (Waferacceptancetest, WAT), this method of testing adopts most advanced and sophisticated superfine probe and is connected the metal pad that single device respectively holds and contacts, and by loading different voltage, currents combination collects corresponding electrical parameter.When testing Weak current parameter (as leakage current), increase the testing time, the test value read after stablizing contributes to the electrostatic getting rid of metal pad surface, but this method still can not get rid of the electric charge interference of the inner random distribution of semi-conducting material.
Although method of testing has done corresponding improvement, take the method for repeatedly testing to reduce interference, even complete in the subenvironment destaticed, residual charge still cannot have been avoided completely on the impact of test result.The leakage current value that usual first time measures exceeds nearly 5 ~ 10 times than actual value, far beyond product specification, judges to have a significant impact to test result.Therefore be necessary that invention is a kind of and can get rid of the electrostatic of crystal column surface and surrounding and remaining electric charge in the semiconductor device, improve the method for testing of test accuracy.
Summary of the invention
The invention provides a kind of semiconductor device electrical property method of testing, its drain electrode and source electrode on load bias voltage after and discharge electric charge, grid with drain electrode on load bias voltage after and discharge electric charge, finally testing electrical property is carried out to the semiconductor device discharging electric charge, guarantee the electric charge in semiconductor device to be released into the impact of testing electrical property extremely small, this method can get rid of the electrostatic of crystal column surface and surrounding and remaining electric charge in the semiconductor device, improves test accuracy.
For achieving the above object, the invention provides a kind of semiconductor device electrical property method of testing, comprising the following steps:
Step one: these four pins of the source electrode of semiconductor, drain electrode, grid and substrate are kept equipotential;
Step 2: the diode making successively to be formed between described drain region and described substrate, the diode formed between described source region and described substrate are opened, and discharged electric charge;
Step 3: discharge electric charge after form conducting channel under gate oxide;
Step 4: semiconductor device step 3 obtained carries out testing electrical property.
As preferably, in step one, these four pins of the source electrode of semiconductor, drain electrode, grid and substrate are kept equipotentials, then in semiconductor device, in source region, drain region and well region, electric charge disordered motion controls in respective region.
As preferably, in described drain electrode, load the diode that bias voltage makes described drain region and described substrate be formed in step 2 open, described source electrode loads the diode that bias voltage makes described source region and described substrate be formed and opens.
As preferably, after the diode formed in described drain region and described substrate in step 2 is opened, after the diode formed in described source region and described substrate is opened, then the accumulation in described source region, described drain region is at earth terminal.
As preferably, discharge the method for electric charge in step 2 for described source electrode, described drain electrode, described grid are connected ground wire with each pin of described substrate.
As preferably, form conducting channel under making gate oxide in step 3 is on described grid and described drain electrode, load equipotential forward bias or negative bias simultaneously.
As preferably, the accumulation in conducting channel described in step 3 is in described drain electrode.
As preferably, discharge the method for electric charge in step 3 for described source electrode, described drain electrode, described grid are connected ground wire with each pin of described substrate.
As preferably, it is the electric current measuring source electrode, drain electrode in non operating state lower semiconductor device that semiconductor device step 3 obtained in step 4 carries out testing electrical property.
Compared with prior art, the invention has the beneficial effects as follows: the invention provides a kind of semiconductor device electrical property method of testing, comprise the following steps:
Step one: these four pins of the source electrode of semiconductor, drain electrode, grid and substrate are kept equipotential;
Step 2: the diode making successively to be formed between described drain region and described substrate, the diode formed between described source region and described substrate are opened, and discharged electric charge;
Step 3: form conducting channel and discharge electric charge under gate oxide;
Step 4: semiconductor device step 3 obtained carries out testing electrical property.
Semiconductor device electrical property method of testing provided by the invention, its drain electrode and source electrode on load bias voltage after and discharge electric charge, grid with drain electrode on load bias voltage after and discharge electric charge, finally testing electrical property is carried out to the semiconductor device discharging electric charge, namely the mode by loading bias voltage expels the unordered electric charge in semiconductor device, guarantee the electric charge in semiconductor device to be released into the impact of testing electrical property extremely small, therefore this method progressively can get rid of the unordered electric charge in source region in semiconductor device, drain region, well region, improves testing electrical property accuracy.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of unordered electric charge disturbed test in nmos device;
Fig. 2 be method of testing provided by the invention use nmos device on load bias voltage sequential chart;
Fig. 3 be method of testing provided by the invention use PMOS device on load bias voltage sequential chart;
Fig. 4 is the flow chart of method of testing provided by the invention.
In figure: 1-substrate, 2-source electrode, 20-source region, 3-drain electrode, 30-drain region, 4-P type well region, 5-grid, 6-gate oxide, the unordered electric charge of 7-, 8-earth terminal;
V
d-load on voltage, the V of drain electrode
s-load on voltage, the V of source electrode
g-load on grid voltage,
V
bulkthe voltage of-earth terminal.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Embodiment one
Please refer to Fig. 1, for nmos device, gate oxide 6 and polysilicon gate 5 are at source electrode 2 and drain between 3, and source electrode 2, the drain electrode 3 of N-type injection are arranged in P type trap zone 4 and isolate mutually with peripheral devices.When doing electrical detection, with semiconductor device electrical property parameter correlation technique, as active area, gate patterns technique, ion implantation and ion-activated technique all complete, and each individual devices all can normal operation.Therefore semiconductor device is after many FEOL process, between regional, there is many unordered electric charges 7 and produces larger impact to the result of testing electrical property.
In order to discharge unordered electric charge 7 in semi-conducting material as far as possible to get rid of its interference to testing electrical property, need to form conducting loop at semiconductor device inside, unordered electric charge 7 is expelled out semiconductor device service area under the electric field action in conducting loop, single P type/N type junction structure that the present invention utilizes each part of semiconductor device to be formed, devises the combinator of various loading bias voltage before testing to expel the unordered electric charge 7 in semi-conducting material.
For achieving the above object, the invention provides a kind of semiconductor device electrical property method of testing, asking emphasis with reference to Fig. 4, comprising the following steps:
Step one: make the source electrode 2 of semiconductor device, drain electrode 3, grid 5 and these four pin equipotentials of substrate 1, then storeroom electronics and hole in each semiconductor device completely cut off mutually by N-type source (i.e. source region 20), the barrier region that formed between drain region 30 and P type trap zone 4, and the disordered motion of unordered electric charge 7 is limited in respective regional extent;
Step 2: load after diode that negative bias makes drain region 30 and substrate 1 be formed opens in drain electrode 3, under the effect of electric field, unordered electric charge 7 in drain region 30 and substrate 1 is collected in earth terminal under electric field action, then by source electrode 2, drain electrode 3, substrate 1, grid 5 four end ground connection, by the unordered electric charge 7 ground connection release in drain region 30 and substrate 1, please refer to Fig. 2, at 0 ~ t
1in time period, load on negative bias in drain electrode 3 as V
dshown in;
Please refer to Fig. 2,0 ~ t
1in time period, in drain electrode 3 and the time sequencing loading bias voltage on source electrode 2, source electrode 2 loads negative bias, the diode that then source region 20 and substrate 1 are formed is opened, and under the effect of electric field, the unordered electric charge 7 in source region 20 and substrate 1 is collected in earth terminal 8 under electric field action, then by source electrode 2, drain electrode 3, substrate 1, grid 5 four end ground connection, by the unordered electric charge 7 ground connection release in source region 20 and substrate 1, please refer to Fig. 2, at 0 ~ t
1in time period, load on negative bias on source electrode 2 as V
sshown in.
Step 3: the forward bias loading equipotential on grid 5, please refer to Fig. 2, namely at t
1~ t
2in time period, at one time inherent drain electrode 3 also loads the forward bias of equipotential, now current saturation in MOS device, form conducting channel at gate oxide 6, conducting channel is similar to circle, and through drain electrode 3, accumulation then under the effect of electric field in conducting channel in drain electrode 3, then by source electrode 2, drain electrode 3, substrate 1, grid 5 four end ground connection, by the unordered electric charge 7 ground connection release in grid 5 and drain region 30, source region 20, please refer to Fig. 2, at t
1~ t
2in time period, load on grid 5 with the negative bias in drain electrode 3 as V
gand V
dshown in.
Above-mentioned from 0 ~ t
2in time period, earth terminal 8 is for receiving unordered electric charge 7, and after four end ground connection, discharged by unordered electric charge 7, the change in voltage on earth terminal is as the V in Fig. 2
bulkshown in.
Step 4: testing electrical property is carried out to the semiconductor device discharging unordered electric charge 7, the i.e. step of testing electrical property in prior art, as loaded forward bias in drain electrode 3, remaining three ends and source electrode 2, substrate 1, grid 5 ground connection, detect the electric current in non operating state lower semiconductor device source electrode 2 and drain electrode 3, in order to verify the effect of method of testing provided by the invention, the wafer of the constructed parameter of preparation two panels, when the same test time, source electrode 2 under the non operating state measured under testing electrical property condition in use prior art, 3 current values that drain are 30pa/um, and source electrode 2 under the non operating state that the method for testing using the present invention to propose measures, 3 current values that drain are about 2pa/um, therefore the semiconductor device electrical property method of testing that the present invention proposes can make the electric charge in semiconductor device to be released into the impact of testing electrical property extremely small, improve the accuracy of testing electrical property.
Embodiment two
Please refer to Fig. 3, the difference of the present embodiment and embodiment one is, uses method of testing provided by the invention in PMOS device, therefore the corresponding voltage V loading on drain electrode
d, load on the voltage V of source electrode
sand load on the voltage V of grid
gopportunity identical with embodiment one, but voltage direction is contrary; The voltage V of earth terminal
bulkidentical with embodiment one.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.If these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. a semiconductor device electrical property method of testing, is characterized in that, comprises the following steps:
Step one: these four pins of the source electrode of semiconductor, drain electrode, grid and substrate are kept equipotential;
Step 2: the diode make the diode formed between described drain region and described substrate open successively, being formed between described source region and described substrate is opened, and discharges electric charge;
Step 3: discharge electric charge after form conducting channel under gate oxide;
Step 4: semiconductor device step 3 obtained carries out testing electrical property.
2. semiconductor device electrical property method of testing as claimed in claim 1, it is characterized in that, in step one, these four pins of the source electrode of semiconductor, drain electrode, grid and substrate are kept equipotential, then in semiconductor device, in source region, drain region and well region, electric charge disordered motion controls in respective region.
3. semiconductor device electrical property method of testing as claimed in claim 2, it is characterized in that, in described drain electrode, load the diode that bias voltage makes described drain region and described substrate be formed in step 2 open, described source electrode loads the diode that bias voltage makes described source region and described substrate be formed and opens.
4. semiconductor device electrical property method of testing as claimed in claim 3, it is characterized in that, after the diode formed in described drain region and described substrate in step 2 is opened, after the diode formed in described source region and described substrate is opened, then the accumulation in described source region, described drain region is at earth terminal.
5. semiconductor device electrical property method of testing as claimed in claim 4, is characterized in that, discharge the method for electric charge for described source electrode, described drain electrode, described grid are connected ground wire with each pin of described substrate in step 2.
6. semiconductor device electrical property method of testing as claimed in claim 1, it is characterized in that, form conducting channel under making gate oxide in step 3 is on described grid and described drain electrode, load equipotential forward bias or negative bias simultaneously.
7. semiconductor device electrical property method of testing as claimed in claim 6, it is characterized in that, the accumulation in conducting channel described in step 3 is in described drain electrode.
8. semiconductor device electrical property method of testing as claimed in claim 7, is characterized in that, discharge the method for electric charge for described source electrode, described drain electrode, described grid are connected ground wire with each pin of described substrate in step 3.
9. semiconductor device electrical property method of testing as claimed in claim 1, is characterized in that, it is the electric current measuring source electrode, drain electrode in non operating state lower semiconductor device that semiconductor device step 3 obtained in step 4 carries out testing electrical property.
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| CN201510662806.1A CN105185723B (en) | 2015-10-14 | 2015-10-14 | A kind of semiconductor device electrical property test method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113740691A (en) * | 2021-07-27 | 2021-12-03 | 杭州士兰集成电路有限公司 | Method for testing field effect transistor |
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| CN101527313A (en) * | 2008-03-07 | 2009-09-09 | 瑞昱半导体股份有限公司 | Metal oxide semiconductor element and manufacturing method thereof |
| KR20100040470A (en) * | 2008-10-10 | 2010-04-20 | 주식회사 하이닉스반도체 | Complementary metal oxide semiconductor device and fabrication method the same |
| CN103378095A (en) * | 2012-04-18 | 2013-10-30 | 北大方正集团有限公司 | Metal oxide semiconductor electrical parameter testing device and method of manufacture |
| CN104241155A (en) * | 2013-06-07 | 2014-12-24 | 三菱电机株式会社 | Method of testing semiconductor device |
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2015
- 2015-10-14 CN CN201510662806.1A patent/CN105185723B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040108532A1 (en) * | 2002-12-04 | 2004-06-10 | Micron Technology, Inc. | Embedded DRAM gain memory cell |
| CN101527313A (en) * | 2008-03-07 | 2009-09-09 | 瑞昱半导体股份有限公司 | Metal oxide semiconductor element and manufacturing method thereof |
| KR20100040470A (en) * | 2008-10-10 | 2010-04-20 | 주식회사 하이닉스반도체 | Complementary metal oxide semiconductor device and fabrication method the same |
| CN103378095A (en) * | 2012-04-18 | 2013-10-30 | 北大方正集团有限公司 | Metal oxide semiconductor electrical parameter testing device and method of manufacture |
| CN104241155A (en) * | 2013-06-07 | 2014-12-24 | 三菱电机株式会社 | Method of testing semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113740691A (en) * | 2021-07-27 | 2021-12-03 | 杭州士兰集成电路有限公司 | Method for testing field effect transistor |
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