CN111667869B - Nonvolatile semiconductor memory device and erase control circuit and method thereof - Google Patents
Nonvolatile semiconductor memory device and erase control circuit and method thereof Download PDFInfo
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- CN111667869B CN111667869B CN201911134622.2A CN201911134622A CN111667869B CN 111667869 B CN111667869 B CN 111667869B CN 201911134622 A CN201911134622 A CN 201911134622A CN 111667869 B CN111667869 B CN 111667869B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
Abstract
The present invention controls an erase voltage with higher accuracy than the known art when erasing data in a nonvolatile semiconductor memory device. A control circuit for controlling an erase voltage comprising: and a slope adjusting circuit for controlling the slope having a step shape by controlling the step widths of the step voltage, the target voltage, and the erase voltage. For each predetermined clock control signal, the slope adjustment circuit repeatedly increases the erase voltage to the target voltage with the step voltage based on the step voltage and the target voltage, and repeatedly clocks each time interval corresponding to the step width based on the step width, thereby outputting the clock control signal to the erase voltage generation circuit.
Description
Technical Field
The application claims the benefit of priority of Japanese application No. 2019-041682 filed on 3/7 of 2019. The above-mentioned patent applications are incorporated by reference in their entirety and form a part of this specification.
The present invention relates to an erase control circuit and an erase control method for a nonvolatile semiconductor memory device (e.g., an electrically erasable programmable read-only memory (EEPROM)) such as a flash memory, and a nonvolatile semiconductor memory device.
Background
A NAND (NAND) type nonvolatile semiconductor memory device is known in which NAND string (NAND string) is formed by connecting a plurality of memory cell transistors (hereinafter, referred to as memory cells) in series between a bit line and a source line to achieve a high degree of integration.
In a typical NAND-type flash memory, a high voltage, for example, 20 volts (V), is applied to a semiconductor substrate, and 0V is applied to a word line. Thereby, electrons are extracted from the floating gate (floating gate) serving as a charge storage layer made of, for example, polysilicon or the like, and the threshold value is made lower than the erase threshold value (for example, -3 volts). On the other hand, in writing (programming), 0 volts is applied to the semiconductor substrate, and a high voltage, for example, 20 volts, is applied to the control gate. Thus, electrons are injected from the semiconductor substrate into the floating gate to make the threshold higher than the write threshold (e.g., 1 volt). By applying a read voltage (e.g., 0 volts) to the control gate between the write threshold and the read threshold, memory cells that assume these thresholds can determine their state based on whether current is flowing through the memory cell.
In the flash memory configured as described above, when writing is performed on a memory cell to be written by a program operation, electric charge is injected into the floating gate of the memory cell transistor, and the threshold voltage rises. Therefore, even if a voltage equal to or lower than the threshold value is applied to the gate electrode, a current does not flow, and a state of writing data "0" is achieved. In general, the threshold voltage of a memory cell in an erased state varies, and process variations also cause variations in the writing speed. Therefore, when a program operation is carried out by applying a predetermined write voltage and verification (verification) is carried out so that the threshold voltage is equal to or higher than the verification level, the distribution of the threshold voltage of the memory cell after writing reaches the degree of being equal to or higher than the verification level.
In addition, an Incremental Step Pulse Program (ISPP) method is used as a method of more efficiently writing to a memory having a large variation in writing speed due to process variation.
[ Prior art documents ]
[ patent document ]
[ patent document 1] Japanese laid-open publication No. 2017-
[ patent document 2] specification of U.S. Pat. No. 8891308
[ patent document 3] specification of U.S. Pat. No. 8873293
Disclosure of Invention
[ problems to be solved by the invention ]
Meanwhile, the operation of erasing data stored in each memory cell of the NAND-type flash memory is mainly achieved by applying a predetermined high voltage pulse to the P-well of the selected memory block based on the word line of the selected memory block. For current NAND type flash memories, it is necessary to strictly control the shape of the high voltage pulse for erasing, and the memory cell is very sensitive to parameters such as a rise time (rise time), a maximum voltage, and a pulse width of an erase voltage.
Since the NAND type flash memory supports 1-plane operation or 2-plane operation of the memory region, an analog circuit such as a charge pump circuit supplying a programmable voltage and an erase voltage is designed to cope with a worst load condition (worst load condition), and specifically designed for the worst load condition during 2-plane operation. However, this design approach may have some negative impact during 1-plane operation.
Fig. 1 is a block diagram showing a configuration example of a NAND-type flash memory 100 according to a known example, and fig. 2 is a graph showing voltage waveforms showing a problem of an erase pulse according to the known example. In fig. 1, a NAND-type flash memory 100 includes a sequencer 1 that controls the operation of the entire memory, a voltage controller 2, an interface 3, an analog circuit 4 having a charge pumping circuit 5, and a memory array 10. Memory array 10 includes a memory region having two planes (0) and (1), an X decoder circuit 22, and a Y decoder circuit 23 and a Y decoder circuit 24.
Fig. 2 shows a difference between a waveform of an erase voltage Vers applied to a P-well during a 1-plane operation and a waveform of the erase voltage Vers applied to the P-well during a 2-plane operation. The load on the P-well in 1-plane operation is twice less than the load on the P-well in 2-plane operation. Therefore, the rise time of the erase voltage Vers in the 1-plane operation is faster than that in the 2-plane operation. Therefore, as is apparent from fig. 2, there is a problem in that a slight overshoot (overshoot) occurs before the erase voltage Vers is stabilized and the performance of the memory cell is degraded.
In view of the above, the present invention provides an erase control circuit and an erase control method of a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device, which can control an erase voltage with higher accuracy than in the conventional art when erasing data in memory cells of the nonvolatile semiconductor memory device.
[ means for solving the problems ]
An erase control circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention is for controlling an erase voltage for erasing data in a memory cell of the nonvolatile semiconductor memory device. The erase control circuit includes: a Slope Adjustment Circuit (SAC) that controls a step voltage, a target voltage, and a step width of an erase pulse of the erase voltage based on the step voltage, the target voltage, and the step width of the erase pulse of the erase voltage, thereby controlling a slope having a step shape (step shape) to generate the erase voltage.
In an erase control circuit of the nonvolatile semiconductor memory device, the slope adjustment circuit includes: an erase voltage generation circuit repeatedly increasing the erase voltage to a target voltage with a step voltage based on the step voltage and the target voltage for each predetermined clock pulse control signal; and a time counter circuit that repeatedly clocks each time interval corresponding to the step width based on the step width, thereby outputting a clock pulse control signal to the erase voltage generation circuit.
A nonvolatile semiconductor memory device according to an embodiment of the present invention includes an erase control circuit of the nonvolatile semiconductor memory device.
An erase control method of a nonvolatile semiconductor memory device according to an embodiment of the present invention is for controlling an erase voltage for erasing data in a memory cell of the nonvolatile semiconductor memory device. The erasing control method comprises the following steps: controlling a step voltage, a target voltage, and a step width of an erase pulse of the erase voltage based on the step voltage, the target voltage, and the step width of the erase pulse of the erase voltage, thereby controlling a slope having a step shape to generate the erase voltage.
In the erase control method of the nonvolatile semiconductor memory device, the step of generating the erase voltage includes the steps of: repeatedly increasing the erase voltage to a target voltage with a step voltage based on the step voltage and the target voltage for each predetermined clock pulse control signal; and repeatedly timing each time interval corresponding to the step width based on the step width, thereby outputting a clock pulse control signal.
[ Effect of the invention ]
Therefore, according to the present invention, it is possible to control the erase voltage with higher accuracy than the known art when erasing data in the memory cells of the nonvolatile semiconductor memory device. Thereby, it is possible to prevent overshoot from occurring before the erase voltage is stabilized and to prevent the performance degradation of the memory cell.
Drawings
Fig. 1 is a block diagram showing a configuration example of a NAND-type flash memory 100 according to a known example.
Fig. 2 is a graph showing voltage waveforms showing the problem of the erase pulse according to the known example.
Fig. 3 is a block diagram showing a configuration example of the erase voltage generation control circuit according to the embodiment.
Fig. 4 is a circuit diagram showing a detailed configuration of the slope adjustment circuit 6 shown in fig. 3.
Fig. 5 is a graph showing an example of the erase pulse generated by the slope adjustment circuit 6 shown in fig. 4.
Fig. 6 is a graph showing an example of an erase pulse generated by the slope adjustment circuit 6 shown in fig. 4.
Fig. 7 is a block diagram showing a configuration example of the NAND-type flash memory 200 according to the embodiment.
Fig. 8 is a flowchart showing an erase pulse control process performed by the sequencer 1 shown in fig. 7.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same or similar components are denoted by the same reference numerals.
Fig. 3 is a block diagram showing a configuration example of an erase voltage generation control circuit according to the embodiment, and fig. 4 is a circuit diagram showing a detailed configuration of a slope adjustment circuit shown in fig. 3. FIG. 5 is a graph illustrating an example of an erase pulse generated by the slope adjustment circuit shown in FIG. 4. In fig. 5, the pulse having the step shape is the erase pulse according to the present embodiment, and other waveforms are comparative examples.
In fig. 3, the erase voltage generation control circuit includes a sequencer 1, a slope adjustment circuit (hereinafter referred to as SAC)6, and a charge pumping circuit 5. The sequencer 1 is a control circuit that controls the overall operation of the NAND-type flash memory 200 (fig. 7), for example, and the sequencer 1 receives the following SAC parameters (slope control parameters of the erase pulse voltage) and sets the SAC parameters to SAC 6, and then instructs the charge pump circuit 5 to generate an erase voltage when erasing data:
(1) stepping voltage Vers _ step;
(2) a target voltage Vers _ target; and
(3) the step width Vers int.
The erase voltage generation control circuit shown in fig. 3 controls the slope of the erase pulse voltage having a step shape. Specifically, the erase pulse voltage is generated by the SAC 6 for keeping the rising time of the erase pulse voltage constant and preventing the occurrence of overshoot. The sequencer 1 as a main logic controls the SAC 6 to set the time (step width) and voltage (step voltage) of each step. Here, SAC parameters are loaded from memory locations of the fuse data area 10F in the memory array 10, for example, from the sequencer 1 to the SAC 6 in turn-on order when the NAND-type flash memory 200 is turned on or reset. Next, the step voltage and step width during the rising period of the erase voltage Vers are adjusted. In fig. 3, Vers _ d is a digital signal bus that supplies the voltage code Vers _ d to the analog charge pumping circuit 5. The charge pumping circuit 5 generates and outputs a corresponding erase voltage Vers based on the input voltage code Vers _ d.
Fig. 4 is a circuit diagram showing a detailed configuration of the SAC 6 shown in fig. 3.
In fig. 4, the SAC 6 includes an erase voltage generation circuit 30 and a time counter circuit 40. The erase voltage generation circuit 30 includes an adder 31, a comparator 32, an AND (AND) gate 33, AND a delayed flip-flop (delayed film-flop) 34. The time counter circuit 40 includes an AND gate 41, an adder 42, a delay flip-flop 43, AND a comparator 44.
The three SAC parameters from the sequencer 1 are input to the adder 31, the comparator 32, and the comparator 44. That is, the step voltage Vers _ step is input to the adder 31, the target voltage Vers _ target is input to the comparator 32, and the step width Vers _ int is input to the comparator 44.
The time counter circuit 40 is a circuit for generating a step clock for generating an erase pulse voltage. In the time counter circuit 40, the AND gate 41 performs an AND operation on the output data from the delay flip-flop 43 AND the inverted data of the output data from the comparator 44, AND outputs the data of the operation result to the adder 42. The adder 42 adds 1 to the input data, and then outputs the data of the addition result to the delay flip-flop 43. The delay type flip-flop 43 temporarily stores data input from the adder 42 to the input terminal according to the external clock CLK after reset by the external reset signal, and then outputs the data to the comparator 44. When the data from delay flip-flop 43 matches step width Vers _ int, comparator 44 outputs a positive clock pulse control signal to AND gate 33.
In the erase voltage generation circuit 30, the adder 31 adds the output data from the delay flip-flop 34 and the input step voltage Vers _ step, and outputs the data of the addition result to the delay flip-flop 34. Meanwhile, the comparator 32 compares the output data from the delay flip-flop 34 with the input target voltage Vers _ target, AND outputs a positive pulse signal to the AND gate 33 when the former data becomes smaller than the latter data. The AND gate 33 performs an AND operation on the pulse signal from the comparator 32, the clock control signal from the comparator 44, AND the external clock CLK, AND outputs a signal of the operation result to the clock terminal of the delay flip-flop 34. After reset by the external reset signal, the delay flip-flop 34 outputs the input data as a voltage code (Vers _ d) in synchronization with the clock from the AND gate 33.
In the SAC 6 configured as described above, parameters such as the step width Vers _ int, the step voltage Vers _ step, and the target voltage Vers _ target are received from the sequencer 1, and each time the data counted by the time counter circuit 40 is increased by 1, the adder 31 of the step voltage Vers _ step is activated and increments the voltage code Vers _ d until the voltage code Vers _ d reaches the target voltage Vers _ target.
Fig. 6 is a graph showing an example of an erase pulse generated by the SAC 6 shown in fig. 4. Fig. 7 is a block diagram showing a configuration example of the NAND-type flash memory 200 according to the embodiment.
In fig. 7, a NAND-type flash memory 200 includes a sequencer 1 having a parameter memory 1m, an analog circuit 4 having a charge pumping circuit or the like, a SAC 6, a data input/output buffer 7, an input logic 8, a control logic 9, and a memory array 10 having a fuse data region 10F.
In fig. 7, the data input/output buffer 7 outputs data input from an external device to the sequencer 1, and while the data is written to the memory array 10 via the page buffer 25, the data from the memory array 10 is read from the memory array 10 via the page buffer 25, and then output from the data input/output buffer 7 to the external device. The input logic 8 inputs a control signal from an external device, and controls internal circuits such as the sequencer 1 and the control logic 9 based on the control signal. The control logic 9 controls the operation of the memory array 10 and its peripheral circuits based on control signals from the input logic.
The sequencer 1 controls the operation of the SAC 6 based on the SAC parameters stored in the parameter memory 1 m. Specifically, the erase voltage Vers is adjusted by controlling the SAC 6 based on the step voltage Vers _ step, the target voltage Vers _ target, and the step width Vers _ int, which are SAC parameters. SAC parameters are configured to be variable during the rise time of each step pulse.
Next, SAC parameters will be described in detail below.
The evaluation of the erase operation is carried out in the early product development stage of the flash memory, and at the time of the evaluation, various SAC parameters are directly input and stored in the parameter memory 1m of the sequencer 1 through the data input/output buffer 7 by using the test mode, and then the optimum SAC parameters are determined. Next, once the optimum SAC parameters are determined, the optimum SAC parameters are written from the parameter memory 1m to the fuse data region 10F in the memory array 10 via the page buffer 25 using the test pattern. Here, SAC parameters are assumed to be set to cope with the worst load (case of selecting multiple planes) and then applied to all cases (until a single plane is selected). In the normal user mode, SAC parameters are automatically loaded from the fuse data area 10F in the memory array 10 to the parameter memory 1m of the sequencer 1 via the page buffer 25 every time the NAND-type flash memory 200 is turned on.
Fig. 8 is a flowchart showing an erase pulse control process performed by the sequencer 1 shown in fig. 7.
In step S1 shown in fig. 8, predetermined SAC parameters are set from the parameter memory 1m of the sequencer 1, and the operation of the SAC 6 is started based on the set SAC parameters in step S2. In step S3, it is determined whether the voltage of the voltage code (Vers _ d) reaches the final target voltage Vers _ target (referred to as the target voltage Vers _ target of the period T3 in the example shown in fig. 6). If the result is yes, the process proceeds to step S4, whereas if the result is no, the process returns to step S1 and the processing of steps S1 to S3 is repeated. Here, the processing of steps S1 to S3 is the processing of the period T1 shown in fig. 6, and is divided into three divided periods, for example, Ta, Tb, and Tc. By setting different SAC parameters to make the stepped erase voltage substantially close to the curve of the erase voltage Vers during 2 planes in each of the divided periods Ta, Tb, and Tc, the stepped erase voltage can be set to reduce the rise time without causing overshoot.
Next, in step S4, a predetermined erase voltage is held by performing "erase pulse time loop processing (loop processing of erase pulse time)" corresponding to the period T2 shown in fig. 6. In step S5, by performing "erase pulse discharge processing (discharge of erase pulse)", the voltage is discharged to decrease from the held erase voltage toward 0 volt. In step S6, the data of the erased memory cell is verified by performing "erase verification processing". In step S7, it is determined whether or not the erasing process for the memory has been completed. If the result is yes, the control process of the erase pulse ends, and if the result is no, the process returns to step S1 and the process is repeated from step S1.
As described above, according to the present embodiment, by controlling the step voltage Vers _ step, the target voltage Vers _ target, and the step width Vers _ int of the erase pulse using the SAC 6, the erase voltage can be controlled to generate the erase pulse with higher accuracy than the conventional art to erase the data in the memory cell. Therefore, it is possible to prevent overshoot from occurring before the erase voltage is stabilized and to prevent performance degradation of the memory cell.
[ modified examples ]
The above embodiments show the erase voltage control circuit of the NAND-type flash memory. However, the present invention is not limited thereto, and the present invention can also be applied to other types of nonvolatile semiconductor memory devices.
In the above embodiment, the time counter circuit 40 as a digital circuit is used to notify that the target voltage has been reached. However, the present invention is not limited thereto, and the erase pulse voltage may be gradually increased using an analog feedback signal obtained through digital-to-analog conversion (DA conversion) of a voltage code.
Difference from patent literature
(difference from patent document 2)
In patent document 2, although the gradient (gradient) between program pulses is controlled, there is no disclosure or teaching of controlling the voltage and the like of the erase pulse.
(difference from patent document 3)
In patent document 3, although the gradient of the program voltage is controlled, there is no disclosure or teaching of controlling the voltage of the erase pulse or the like.
[ field of Industrial application ]
As described in detail above, according to the present invention, it is possible to control the erase voltage with higher accuracy than the known art when erasing data in the memory cells of the nonvolatile semiconductor memory device. Therefore, it is possible to prevent overshoot from occurring before the erase voltage is stabilized and to prevent performance degradation of the memory cell.
[ description of symbols ]
1: sequencer
1 m: parameter memory
2: voltage controller
3: interface
4: analog circuit
5: charge pump circuit (analog charge pump circuit)
6: slope Adjusting Circuit (SAC)
7: data input/output buffer
8: input logic
9: control logic
10: memory array
10F: fuse data area
22: x decoder circuit
23. 24: y decoder circuit
25: page buffer
30: erase voltage generation circuit
31. 42: adder
32. 44: comparator with a comparator circuit
33. 41: AND gate
34. 43: delay type flip-flop
40: time counter circuit
100. 200: NAND type flash memory
CLK: external clock
S1, S2, S3, S4, S5, S6, S7: step (ii) of
T1, T2, T3, T4: period of time
Ta, Tb, Tc: divided cycle
Vers: erase voltage
Vers _ d: voltage code
Vers _ int: step width
Vers _ step: step voltage
Vers _ target: target voltage
Claims (3)
1. An erase control circuit of a nonvolatile semiconductor memory device, the erase control circuit controlling an erase voltage for erasing data in a memory cell of the nonvolatile semiconductor memory device, the erase control circuit comprising:
a slope adjustment circuit that controls a step voltage, a target voltage, and a step width of an erase pulse of the erase voltage based on the step voltage, the target voltage, and the step width of the erase pulse of the erase voltage to control a slope having a step shape to generate the erase voltage,
wherein the slope adjustment circuit comprises:
an erase voltage generation circuit that repeatedly increases the erase voltage to the target voltage by the step voltage based on the step voltage and the target voltage for each predetermined clock pulse control signal; and
a time counter circuit that repeatedly clocks each time interval corresponding to the step width based on the step width, thereby outputting the clock pulse control signal to the erase voltage generation circuit.
2. A nonvolatile semiconductor memory device comprising the erase control circuit of the nonvolatile semiconductor memory device according to claim 1.
3. An erase control method of a nonvolatile semiconductor memory device for controlling an erase voltage for erasing data in memory cells of the nonvolatile semiconductor memory device, the erase control method comprising the steps of:
controlling a step voltage, a target voltage, and a step width of an erase pulse of the erase voltage based on the step voltage, the target voltage, and the step width of the erase pulse of the erase voltage, thereby controlling a slope having a step shape to generate the erase voltage,
wherein the step of generating the erase voltage comprises the steps of:
repeatedly increasing the erase voltage to the target voltage by the stepped voltage based on the stepped voltage and the target voltage for each predetermined clock pulse control signal; and
repeatedly clocking each time interval corresponding to the step width based on the step width, thereby outputting the clock pulse control signal.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2019-041682 | 2019-03-07 | ||
| JP2019041682A JP6741811B1 (en) | 2019-03-07 | 2019-03-07 | Erase control circuit and method for nonvolatile semiconductor memory device, and nonvolatile semiconductor memory device |
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| CN111667869A CN111667869A (en) | 2020-09-15 |
| CN111667869B true CN111667869B (en) | 2022-06-14 |
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| US (1) | US11074979B2 (en) |
| JP (1) | JP6741811B1 (en) |
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- 2019-09-18 US US16/574,099 patent/US11074979B2/en active Active
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| CN101154458A (en) * | 2006-09-26 | 2008-04-02 | 三星电子株式会社 | Multi-block memory device erasing methods and related memory devices |
| CN101923901A (en) * | 2010-05-13 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | Programming driving system and driving method for phase change memory |
| CN101964212A (en) * | 2010-08-11 | 2011-02-02 | 上海宏力半导体制造有限公司 | Negative voltage slope control circuit |
| CN102543154A (en) * | 2010-11-18 | 2012-07-04 | 美光科技公司 | Memory instruction including parameter to affect operating condition of memory |
| CN103680622A (en) * | 2012-09-14 | 2014-03-26 | 飞思卡尔半导体公司 | Non-volatile memory (NVM) with adaptive write operations |
| CN104299649A (en) * | 2013-07-16 | 2015-01-21 | 飞思卡尔半导体公司 | Adaptive erase recovery for non-volatile memory (nvm) systems |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6741811B1 (en) | 2020-08-19 |
| CN111667869A (en) | 2020-09-15 |
| US20200286565A1 (en) | 2020-09-10 |
| US11074979B2 (en) | 2021-07-27 |
| TW202034334A (en) | 2020-09-16 |
| JP2020144963A (en) | 2020-09-10 |
| TWI707348B (en) | 2020-10-11 |
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