CN111651398A - Master station M _ BUS BUS interface circuit with sending and receiving state control - Google Patents
Master station M _ BUS BUS interface circuit with sending and receiving state control Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a master station M _ BUS interface circuit with sending and receiving state control, which is used in electric energy meter, water meter, gas meter and heat meter four-meter centralized reading engineering and relates to the master station M _ BUS interface circuit; the M _ BUS sending drive circuit has few and common used devices, and is strong in loading capacity by controlling a power MOS tube and a power voltage stabilizing tube to drive a main node M _ BUS to send a command; the monostable chip is adopted to control the master station M _ BUS to switch the sending/receiving states, the M _ BUS master node is controlled to sample and receive data, the power consumption of the sampling resistor is low, and the receiving error rate is low and reliable.
Description
Technical Field
The invention discloses a master station M _ BUS interface circuit with sending and receiving state control, which is used for a communication interface circuit of an electric energy meter, a water meter, a gas meter, a heat meter-four meter centralized reading terminal, and relates to the technical field of master station M _ BUS interface circuits.
Background
The M _ BUS is a master-slave field BUS, in a four-meter centralized meter reading M _ BUS structure, a water meter, a gas meter and a heat meter are slave station nodes of the M _ BUS, an acquisition terminal is a unique master station communication node and is a key node in the M _ BUS, the acquisition terminal is an initiator of a communication command, and the water meter, the gas meter and the heat meter respond to the acquisition terminal command.
The Texas Instrument (TI) is a cooperative quotient of M _ BUS standard and alliance, and provides a scheme of a related master station circuit and a slave station chip circuit for an M _ BUS physical layer; FIG. 5 shows a main station M _ BUS node recommendation circuit of a Texas Instrument (TI), in practical application, a transmitting driving chip IC201 (TLE 2301) of the TI is a high-voltage power operational amplifier, the same type of chips are few, the chip price is high, and in practical engineering application, the number of driving slave nodes generally cannot meet the field requirement; in a receiving circuit of the TI, it is difficult to precisely set the resistance of R208, the larger the resistance of R208 is, the lower the error rate of decoded received data is, but when the number of driving nodes is fully loaded, R208 consumes large power, and the resistance heats seriously, and if the resistance is reduced to prevent R208 from heating, the received data is easily interfered by power supply and bus noise, so that the error rate is increased, and the correct reception of data is affected, which is a common problem in the practical implementation of the four-meter centralized meter reading project.
Disclosure of Invention
The invention aims to: aiming at an M _ BUS physical layer master station circuit scheme recommended by Texas Instruments (TI), a master station M _ BUS interface circuit with transmitting and receiving state control is provided.
The technical scheme adopted by the invention is as follows: a master station M _ BUS interface circuit with sending and receiving state control comprises an M _ BUS sending drive circuit, an M _ BUS sending/receiving state control circuit electrically connected with the M _ BUS sending drive circuit, and an M _ BUS sampling resistor bypass circuit electrically connected with the M _ BUS sending/receiving state control circuit;
the M _ BUS transmission driving circuit is a master station transmission circuit and is used for transmitting serial data to 2 cable wires of the M _ BUS, and the 2 cable wires are power supply wires and communication wires;
the M _ BUS BUS sending/receiving state control circuit can realize that when data needs to be sent, the sending state is controlled by the circuit, and after the data is sent, the circuit returns to the receiving state after a certain delay is added;
m _ BUS BUS sampling resistance bypass circuit for increase the driving capability, can drive more from the contact.
The working principle of the invention is as follows: the M _ BUS is a control-oriented BUS and is divided into a master contact and a slave contact, the M _ BUS transmission driving circuit is a master station transmission circuit and transmits serial data to 2 cable wires of the M _ BUS, and the 2 cable wires are power supply wires and communication wires; because M _ BUS is not duplex communication, any contact can only be in a sending or receiving state and cannot be in the sending and receiving states at the same time during communication, the states are switched to have appointed delay time, the M _ BUS sending/receiving state control circuit is used for completing the function, when data needs to be sent, the sending state is controlled by the circuit, and after the data is sent, the circuit returns to the receiving state after adding a determined delay; m _ BUS BUS sampling resistance bypass circuit aims at increasing driving capability and driving more slave contacts.
The M _ BUS BUS sending drive circuit comprises an optocoupler E1, a triode V1, a triode V2 and a voltage regulator VD1, wherein the anode of a first pin luminous tube of the optocoupler E1 is connected with one end of a resistor R3, and the other end of the resistor R3 is connected to a 3.3V power supply; a serial transmitting pin TXD of the microcontroller is connected to the cathode of a luminous tube of a second pin of the optocoupler E1; an emitter of a third pin photoelectric receiving tube of the optical coupler E1 is connected with a reference point G; the collector of a photoelectric receiving tube of a fourth pin of the optical coupler E1 is connected to one end of a resistor R1, the other end of the resistor R1 is connected to a 5V power supply, meanwhile, the collector of a photoelectric receiving tube of a fourth pin of the optical coupler E1 is connected to one end of a resistor R5, and the other end of the resistor R5 is connected to the base of a triode V2; the emitter of the transistor V2 is connected to the reference ground G; the collector of the triode V2 is connected to one end of a resistor R4, the other end of the resistor R4 is connected to one end of a resistor R2, the other end of the resistor R2 is connected to a 24V power supply, and meanwhile, the other end of the resistor R4 is connected to the base of a triode V1; the emitter of the triode V1 is connected with a 24V power supply and the anode of an electrolytic capacitor CE1, and the cathode of the electrolytic capacitor is connected with a reference ground G; the collector of the triode V1 is connected with the anode of the diode VD1, the cathode of the diode VD1 is connected with the 24V power supply, and meanwhile, the collector of the triode V1 is connected with the M _ BUS + BUS.
When the microprocessor drives the M _ BUS to send a 'pass' level, the triodes V2 and V1 are conducted, and the 24V power supply provides the 'pass' level for the M _ BUS; when the microprocessor drives the M _ BUS to send 'no-number' level, the triodes V1 and V2 are cut off, and the 24V power supply provides 12V 'no-number' level for the M _ BUS through the voltage regulator VD 1.
The optocoupler E1 selects a model LTV-816S, the triode V1 selects a PNP triode, a model 2SAR514R, the triode V2 selects an NPN triode, a model 2SC2412, the voltage stabilizing diode selects a model SMBJ5349B, the power is 5W, the resistance value of the resistor R1 is 2.2k omega, the resistance value of the resistor R2 is 100k omega, the resistance value of the resistor R4 is 10k omega, the resistance value of the resistor R5 is 20k omega, and the capacitance value of the electrolytic capacitor is 1000 muF 50V.
The M _ BUS BUS transmitting/receiving state control circuit comprises a monostable chip N1, a triode V3, a diode VD2, a collector of a photoelectric receiving tube of a fourth pin of an optocoupler E1 is connected to one end of a resistor R6, and the other end of the resistor R6 is connected to a 5 th pin B1 of the monostable chip N1; a2 nd pin C/R1 of the monostable chip N1 is connected to one end of a resistor R7 and a capacitor C3, the other end of the R7 is connected with a 5V power supply, and the other end of the capacitor C3 is connected with a reference ground G; a 14 th pin C/R2 of the monostable chip N1 is connected to one end of a resistor R8 and a capacitor C4, the other end of the R8 is connected with a 5V power supply, and the other end of the capacitor C4 is connected with a reference ground G; a 16 th pin VCC of the monostable chip N1 is connected to a 5V power supply, a 16 th pin VCC of the N1 is simultaneously connected to one ends of capacitors C1 and C2, and the other ends of the capacitors C1 and C2 are connected to a reference ground G; the 1 st pin GND, the 4 th pin A1, the 8 th pin GND and the 12 th pin A2 of the monostable chip N1 are connected to a reference ground G; a 6 th pin Q1 of the monostable chip N1 is connected to one end of a capacitor C5, the other end of the capacitor C5 is connected to an 11 th pin B2 of the monostable chip N1, and is also connected to one end of a resistor R9 and the anode of a diode VD2, and the other end of the resistor R9 and the cathode of a diode VD2 are connected to a 5V power supply; the 9 th pin Q2 of the monostable chip N1 is not connected to one end of a resistor R10, the other end of the resistor R10 is connected to the base of a triode V3, the emitter of a triode V3 is connected with a reference ground G, the collector of a triode V3 is connected with one end of a resistor R11 and is simultaneously connected to an M _ BUS-BUS, and the other end of the resistor R11 is connected with the reference ground G.
The monostable chip N1 is a two-way monostable unit, when the microcontroller commands to send, the first stage monostable unit is triggered, and when the commands are sent, the first stage monostable unit triggers the second stage monostable unit after the delay t1= R7C 3, and the delay t2= R8C 4.
t1= 20k × 1 μ F =20 mS; command transmission time + delay time for switching from the transmission state to the reception state.
t2=47 k × 2 μ F =94 mS; a receive data latency.
In the t2 (received data latency) state, transistor V3 is turned off and the received data is sampled by sampling resistor R11.
The monostable chip N1 selects a model MC14538, the triode V3 is an NPN triode, the model 2SC514P, the diode VD2 selects a model 1N4148, the resistance values of the resistors R6 and R7 are 20k omega, the resistance value of the resistor R10 is 2.2k omega, the resistance value of the resistor R8 is 47k omega, the resistance value of the resistor R9 is 22k omega, the resistance value of the resistor R5 is 20k omega, the capacitance values of the capacitors C1, C3 and C5 are 1 muF, and the capacitance value of the capacitor C4 is 2 muF.
The M _ BUS BUS sampling resistor bypass circuit comprises an optocoupler E2, a comparator N2, a triode V4, a diode VD3, an M _ BUS BUS M _ BUS-connected triode V3 collector, a diode VD3 cathode, a resistor R11 and one end of a resistor R14, the other end of the resistor R11 and the emitter of the triode V3 are connected with a reference ground G, the other end of the R14 is connected with one end of a1 st pin (+), a capacitor C6 and the other end of the capacitor C6 are connected with a 4 th pin of a comparator N2 and one end of a resistor R15, the other end of the R15 is connected with a triode V4 base, the emitter of the triode V4 is connected with the reference ground G, the collector of the triode V686V 9 is connected with the cathode of a second pin of an optocoupler E2, the anode of a first pin of the optocoupler E2 is connected with one end of a resistor R; the anode of the diode VD3 is connected with one ends of resistors R16, R17, R18 and C8, the other ends of R17, R18 and C8 are connected with a reference ground G, and the other end of the resistor R16 is connected with the 3 rd pin of a comparator N2; the 2 nd pin of the comparator N2 is connected with the reference ground G; the 5 th pin of the comparator N2 is connected with one ends of capacitors C7 and C9 and is also connected with a 5V power supply, and the other ends of the capacitors C7 and C9 are connected with a reference ground G; the collector of a 4 th pin photoelectric tube of the optical coupler E2 is connected with one end of a resistor R13 and is simultaneously connected with a serial receiving pin RXD of the microcontroller, the other end of the resistor R13 is connected with a 3.3V power supply, and the emitter of the photoelectric tube of a 3 rd pin of the optical coupler E2 is connected with a reference ground G.
Under the control of the monostable chip N1, the receiving circuit samples the received data by the sampling resistor R11 only in the state of t2 (waiting time for received data), and the sampling resistor R11 is bypassed in the non-communication state and the command transmission state, so that power is not consumed.
The triode V4 model 2SC2412, the diode VD2 model 1N5819, the comparator N2 model LMV321, the resistance value 100R/3W of the resistor R11, the resistance value 10k omega of the resistor R13, the resistance values 3.3 k omega of the resistors R14 and R16, the resistance values 1k omega of the resistors R12 and R15, the resistance value 33 k omega of the resistor R17, the resistance value 5.1 k omega of the resistor R18, the capacitance value of the capacitor C7 is 0.1uF, and the capacitance values of the capacitors C8 and C9 are 4.7 uF.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
compared with a master station M _ BUS recommendation circuit of a Texas Instrument (TI), the main station M _ BUS recommendation circuit has the advantages that: the M _ BUS BUS transmission driving circuit drives more slave nodes than a power operational amplifier chip, the circuit is simple, and the number of devices is small; the key devices are a triode V1 model 2SAR514R, a triode V2 model 2SC2412 and a zener diode model SMBJ5349B, the devices are ordinary and easy to purchase, and the cost performance is excellent;
the M _ BUS BUS transmitting/receiving state control circuit is formed by a monostable chip MC14538, a bi-monostable trigger unit controls the switching of transmitting and receiving states of a master station, and the state switching logic is clear and definite;
under the control of a transmitting/receiving state control circuit, a receiving sampling resistor R11 resistor value 100R/3W and a receiving resistor R208 resistor value 27R of a Bidezhou instrument (TI) are increased by 3.7 times, data receiving is not influenced by line and power supply interference noise, the success rate of once data acquisition is 100 percent in engineering implementation, the R11 sampling resistor is increased in resistance value, only the high power is instantly borne during data receiving, and the resistance value 100R/3W of the sampling resistor R11 basically does not generate heat or scald in field temperature test.
Drawings
The invention will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of the M _ BUS BUS of the present invention;
FIG. 2 is a diagram of the M _ BUS transmission driving circuit of the present invention;
FIG. 3 is a circuit diagram of the M _ BUS transmission/reception status control circuit of the present invention;
FIG. 4 is a diagram of the M _ BUS BUS receive sampling resistor bypass circuit of the present invention;
FIG. 5 is a Master station M _ BUS node recommendation circuit for Texas Instruments (TI);
labeled as: the device comprises a 1-M _ BUS sending drive circuit, a 2-M _ BUS sending/receiving state control circuit and a 3-M _ BUS receiving sampling resistor bypass circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A master station M _ BUS interface circuit with sending and receiving state control comprises an M _ BUS sending drive circuit 1, an M _ BUS sending/receiving state control circuit 2 electrically connected with the M _ BUS sending drive circuit 1, and an M _ BUS sampling resistor bypass circuit 3 electrically connected with the M _ BUS sending/receiving state control circuit 2;
the M _ BUS transmission driving circuit 1 is a master station transmission circuit and transmits serial data to 2 cable wires of the M _ BUS, wherein the 2 cable wires are power supply wires and communication wires;
the M _ BUS BUS sending/receiving state control circuit 2 can realize that when data needs to be sent, the sending state is controlled by the circuit, and after the data is sent, the receiving state is returned after the circuit adds a certain delay;
m _ BUS BUS sampling resistance bypass circuit 3 for increase the driving capability, can drive more from the contact.
The working principle of the invention is as follows: the M _ BUS of the invention is a control-oriented BUS, divide main contact and slave contact, the M _ BUS of the invention sends the drive circuit 1 to be the sending circuit of the master station, send the serial data to 2 cable wires of M _ BUS, 2 cable wires are power lines as well as communication lines; because M _ BUS is not duplex communication, any contact can only be in a sending or receiving state during communication, and can not be in the sending and receiving states at the same time, the state switching has agreed delay time, the M _ BUS sending/receiving state control circuit 2 has the function of completing the function, when data needs to be sent, the circuit controls the sending state, and after the data is sent, the circuit returns to the receiving state after adding a determined delay; m _ BUS BUS sampling resistor bypass circuit 3 aims to increase the driving capability and drive more slave contacts.
Example 1
As shown in fig. 1 to 4, the present invention includes an M _ BUS transmission driving circuit 1, an M _ BUS transmission/reception state control circuit 2, and an M _ BUS reception sampling resistance bypass circuit 3, wherein:
a first pin (anode of a light emitting tube) of an optical coupler E1 of the M _ BUS BUS transmission driving circuit 1 is connected with one end of a resistor R3, and the other end of the resistor R3 is connected to a 3.3V power supply; a serial transmitting pin TXD of the microcontroller is connected to a second pin (cathode of a luminous tube) of the optical coupler E1; a third pin (an emitter of the photoelectric receiving tube) of the optical coupler E1 is connected with a reference point G; a fourth pin (collector electrode of a photoelectric receiving tube) of the optical coupler E1 is connected to one end of a resistor R1, the other end of the resistor R1 is connected to a 5V power supply, meanwhile, a fourth pin (collector electrode of a photoelectric tube) of the optical coupler E1 is connected to one end of a resistor R5, and the other end of the resistor R5 is connected to a base electrode of a triode V2; the emitter of the transistor V2 is connected to the reference ground G; the collector of the triode V2 is connected to one end of a resistor R4, the other end of the resistor R4 is connected to one end of a resistor R2, the other end of the resistor R2 is connected to a 5V power supply, and meanwhile, the other end of the resistor R4 is connected to the base of a triode V1; the emitter of the triode V1 is connected with a 24V power supply and the anode of an electrolytic capacitor CE1, and the cathode of the electrolytic capacitor is connected with a reference ground G; the collector of the triode V1 is connected with the anode of the diode VD1, the cathode of the diode VD1 is connected with a 24V power supply, and meanwhile, the collector of the triode V1 is connected with an M _ BUS + BUS; the photoelectric detector comprises an optocoupler E1 model LTV-816S, a triode V1 model 2SAR514R, a triode V2 model 2SC2412 and a zener diode model SMBJ5349B, wherein the resistance value of a resistor R1 is 2.2k omega, the resistance value of a resistor R1 is 100k omega, the resistance value of a resistor R4 is 10k omega, the resistance value of a resistor R5 is 20k omega, and the capacitance value of an electrolytic capacitor is 1000 muF 50V.
Example 2
On the basis of embodiment 1, the M _ BUS transmission/reception state control circuit 2 includes a monostable chip N1, a transistor V3, a diode VD2, a fourth pin (collector of a photo-receiving tube) of an optocoupler E1 connected to one end of a resistor R6, and the other end of the resistor R6 connected to a 5 th pin (B1 not) of a monostable chip N1; the 2 nd pin (C/R1) of the monostable chip N1 is connected to one end of a resistor R7 and a capacitor C3, the other end of the R7 is connected with a 5V power supply, and the other end of the capacitor C3 is connected with a reference ground G; the 14 th pin (C/R2) of the monostable chip N1 is connected to one end of a resistor R8 and a capacitor C4, the other end of the R8 is connected with a 5V power supply, and the other end of the capacitor C4 is connected with a reference ground G; the 16 th pin (VCC) of the monostable chip N1 is connected to a 5V power supply, the 16 th pin (VCC) of the N1 is simultaneously connected to one ends of capacitors C1 and C2, and the other ends of the capacitors C1 and C2 are connected to a reference ground G; the 1 st pin (GND), the 4 th pin (A1), the 8 th pin (GND) and the 12 th pin (A2) of the monostable chip N1 are connected to a reference ground G; the 6 th pin (Q1) of the monostable chip N1 is connected to one end of a capacitor C5, the other end of the capacitor C5 is connected to the 11 th pin (B2 NOT) of the monostable chip N1, and is also connected to one end of a resistor R9 and the anode of a diode VD2, and the other end of the resistor R9 and the cathode of a diode VD2 are connected to a 5V power supply; a 9 th pin (Q2 not) of a monostable chip N1 is connected to one end of a resistor R10, the other end of the resistor R10 is connected to a base electrode of a triode V3, an emitter of the triode V3 is connected with a reference ground G, a collector of the triode V3 is connected with one end of a resistor R11 and is simultaneously connected to an M _ BUS-BUS, and the other end of the resistor R11 is connected with the reference ground G; the circuit comprises a monostable chip N1 model MC14538, a triode V3 model 2SC514P and a diode VD2 model 1N4148, wherein the resistance values of a resistor R6 and a resistor R7 are 20k omega, the resistance value of a resistor R10 is 2.2k omega, the resistance value of a resistor R8 is 47k omega, the resistance value of a resistor R9 is 22k omega, the resistance value of a resistor R5 is 20k omega, and the capacitance values of capacitors C1, C3 and C5 are 1 muF. The capacitance C4 has a capacitance of 2 μ F.
Example 3
On the basis of embodiment 2, the M _ BUS receiving and sampling resistor bypass circuit 3 includes an optocoupler E2, a comparator N2, a triode V4, a diode VD3, and an M _ BUS (M _ BUS-) connected to a collector of a triode V3, a cathode of a diode VD3, one ends of resistors R11 and R14, the other end of the resistor R11 and an emitter of the triode V3 are connected to a reference ground G, the other end of R14 is connected to a1 st pin (+) (of the comparator N2) and one end of a capacitor C6, the other end of the capacitor C6 is connected to a 4 th pin of the comparator N2, and is connected to one end of a resistor R15, the other end of R24 is connected to a base of a triode V4, an emitter of the triode V4 is connected to a reference ground G, a collector of the triode V4 is connected to a second pin (cathode) of an E optocoupler 2, a first pin (anode) of the optocoupler E2 is; the anode of the diode VD3 is connected with one ends of resistors R16, R17, R18 and C8, the other ends of R17, R18 and C8 are connected with a reference ground G, and the other end of the resistor R16 is connected with the 3 rd pin of a comparator N2; the 2 nd pin of the comparator N2 is connected with the reference ground G; the 5 th pin of the comparator N2 is connected with one ends of capacitors C7 and C9 and is also connected with a 5V power supply, and the other ends of the capacitors C7 and C9 are connected with a reference ground G; a 4 th pin (a collector of a photoelectric tube) of the optical coupler E2 is connected with one end of a resistor R13 and is simultaneously connected with a serial receiving pin RXD of the microcontroller, the other end of the resistor R13 is connected with a 3.3V power supply, and a 3 rd pin (an emitter of the photoelectric tube) of the optical coupler E2 is connected with a reference ground G; a triode V3 model 2SC514P, a diode VD2 model 1N5819 and a comparator N2 model LMV 321; the resistance of the resistor R11 is 100R/3W, the resistance of the resistor R13 is 10k omega, the resistances of the resistors R14 and R16 are 3.3 k omega, the resistances of the resistors R12 and R15 are 1k omega, the resistance of the resistor R17 is 33 k omega, the resistance of the resistor R18 is 5.1 k omega, the capacitance of the capacitor C7 is 0.1uF, and the capacitances of the capacitors C8 and C9 are 4.7 uF.
The above description is only a preferred embodiment of the present invention, and not intended to limit the present invention, the scope of the present invention is defined by the appended claims, and all structural changes that can be made by using the contents of the description and the drawings of the present invention are intended to be embraced therein.
Claims (7)
1. A master station M _ BUS interface circuit with sending and receiving state control is characterized by comprising an M _ BUS sending drive circuit, an M _ BUS sending/receiving state control circuit electrically connected with the M _ BUS sending drive circuit, and an M _ BUS sampling resistor bypass circuit electrically connected with the M _ BUS sending/receiving state control circuit;
the M _ BUS transmission driving circuit is a master station transmission circuit and is used for transmitting serial data to 2 cable wires of the M _ BUS, and the 2 cable wires are power supply wires and communication wires;
the M _ BUS BUS sending/receiving state control circuit can realize that when data needs to be sent, the sending state is controlled by the circuit, and after the data is sent, the circuit returns to the receiving state after a certain delay is added;
m _ BUS BUS sampling resistance bypass circuit for increase the driving capability, can drive more from the contact.
2. The M _ BUS interface circuit of the main station with the transmitting and receiving state control function of claim 1, wherein the M _ BUS transmitting and driving circuit comprises an optical coupler E1, a triode V1, a triode V2 and a voltage regulator VD1, an anode of a first pin of the optical coupler E1 is connected with one end of a resistor R3, and the other end of the resistor R3 is connected with a 3.3V power supply; a serial transmitting pin TXD of the microcontroller is connected to the cathode of a luminous tube of a second pin of the optocoupler E1; an emitter of a third pin photoelectric receiving tube of the optical coupler E1 is connected with a reference point G; the collector of a photoelectric receiving tube of a fourth pin of the optical coupler E1 is connected to one end of a resistor R1, the other end of the resistor R1 is connected to a 5V power supply, meanwhile, the collector of a photoelectric receiving tube of a fourth pin of the optical coupler E1 is connected to one end of a resistor R5, and the other end of the resistor R5 is connected to the base of a triode V2; the emitter of the transistor V2 is connected to the reference ground G; the collector of the triode V2 is connected to one end of a resistor R4, the other end of the resistor R4 is connected to one end of a resistor R2, the other end of the resistor R2 is connected to a 24V power supply, and meanwhile, the other end of the resistor R4 is connected to the base of a triode V1; the emitter of the triode V1 is connected with a 24V power supply and the anode of an electrolytic capacitor CE1, and the cathode of the electrolytic capacitor is connected with a reference ground G; the collector of the triode V1 is connected with the anode of the diode VD1, the cathode of the diode VD1 is connected with the 24V power supply, and meanwhile, the collector of the triode V1 is connected with the M _ BUS + BUS.
3. The M _ BUS interface circuit of claim 1, wherein the M _ BUS transmitting/receiving state control circuit comprises a monostable chip N1, a triode V3, a diode VD2, a fourth pin photoelectric receiving tube collector of an optical coupler E1 connected to one end of a resistor R6, and the other end of the resistor R6 connected to a 5 th pin B1 of a monostable chip N1; a2 nd pin C/R1 of the monostable chip N1 is connected to one end of a resistor R7 and a capacitor C3, the other end of the R7 is connected with a 5V power supply, and the other end of the capacitor C3 is connected with a reference ground G; a 14 th pin C/R2 of the monostable chip N1 is connected to one end of a resistor R8 and a capacitor C4, the other end of the R8 is connected with a 5V power supply, and the other end of the capacitor C4 is connected with a reference ground G; a 16 th pin VCC of the monostable chip N1 is connected to a 5V power supply, a 16 th pin VCC of the N1 is simultaneously connected to one ends of capacitors C1 and C2, and the other ends of the capacitors C1 and C2 are connected to a reference ground G; the 1 st pin GND, the 4 th pin A1, the 8 th pin GND and the 12 th pin A2 of the monostable chip N1 are connected to a reference ground G; a 6 th pin Q1 of the monostable chip N1 is connected to one end of a capacitor C5, the other end of the capacitor C5 is connected to an 11 th pin B2 of the monostable chip N1, and is also connected to one end of a resistor R9 and the anode of a diode VD2, and the other end of the resistor R9 and the cathode of a diode VD2 are connected to a 5V power supply; the 9 th pin Q2 of the monostable chip N1 is not connected to one end of a resistor R10, the other end of the resistor R10 is connected to the base of a triode V3, the emitter of a triode V3 is connected with a reference ground G, the collector of a triode V3 is connected with one end of a resistor R11 and is simultaneously connected to an M _ BUS-BUS, and the other end of the resistor R11 is connected with the reference ground G.
4. The M _ BUS interface circuit of claim 1, the M _ BUS sampling resistor bypass circuit is characterized by comprising an optocoupler E2, a comparator N2, a triode V4, a diode VD3, an M _ BUS-connected triode V3 collector, a diode VD3 cathode, resistors R11 and R14, the other end of a resistor R11 and an emitter of the triode V3 are connected with a reference ground G, the other end of R14 is connected with a1 st pin (+), one end of a capacitor C6, the other end of a capacitor C6 is connected with a 4 th pin of the comparator N2, meanwhile, one end of a resistor R15 is connected, the other end of the resistor R15 is connected with the base electrode of a triode V4, the emitter of the triode V4 is connected with a reference ground G, the collector of the triode V4 is connected with the cathode of a second pin light-emitting tube of an optocoupler E2, the anode of a first pin light-emitting tube of the optocoupler E2 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with; the anode of the diode VD3 is connected with one ends of resistors R16, R17, R18 and C8, the other ends of R17, R18 and C8 are connected with a reference ground G, and the other end of the resistor R16 is connected with the 3 rd pin of a comparator N2; the 2 nd pin of the comparator N2 is connected with the reference ground G; the 5 th pin of the comparator N2 is connected with one ends of capacitors C7 and C9 and is also connected with a 5V power supply, and the other ends of the capacitors C7 and C9 are connected with a reference ground G; the collector of a 4 th pin photoelectric tube of the optical coupler E2 is connected with one end of a resistor R13 and is simultaneously connected with a serial receiving pin RXD of the microcontroller, the other end of the resistor R13 is connected with a 3.3V power supply, and the emitter of the photoelectric tube of a 3 rd pin of the optical coupler E2 is connected with a reference ground G.
5. The M _ BUS BUS interface circuit of claim 2, wherein the optocoupler E1 is of type LTV-816S, the triode V1 is of PNP type, the triode V35514 514R is of type 2SAR, the triode V2 is of NPN type, the triode V2412 is of type 2SC2412, the zener diode is of type SMBJ5349B, the power is 5W, the resistance value of the resistor R1 is 2.2k Ω, the resistance value of the resistor R2 is 100k Ω, the resistance value of the resistor R4 is 10k Ω, the resistance value of the resistor R5 is 20k Ω, and the capacitance value of the electrolytic capacitor is 1000 μ F50V.
6. The M _ BUS interface circuit of the master station with the state control function of transmitting and receiving of claim 3, wherein the type MC14538 is selected as the monostable chip N1, the NPN triode is selected as the triode V3, the type 2SC514P is selected as the diode VD2, the type 1N4148 is selected as the diode VD2, the resistance values of the resistors R6 and R7 are 20k Ω, the resistance value of the resistor R10 is 2.2k Ω, the resistance value of the resistor R8 is 47k Ω, the resistance value of the resistor R9 is 22k Ω, the resistance value of the resistor R5 is 20k Ω, the capacitance values of the capacitors C1, C3 and C5 are 1 μ F, and the capacitance value of the capacitor C4 is 2 μ F.
7. The M _ BUS interface circuit of claim 4, wherein the transistor V4 model 2SC2412, the diode VD2 model 1N5819, the comparator N2 model LMV321, the resistor R11 100R/3W, the resistor R13 10k Ω, the resistor R14, R16 3 k Ω, the resistor R12, R15 1k Ω, the resistor R17 resistor 33 k Ω, the resistor R18 5.1 k Ω, the capacitor C7 has a capacitance of 0.1uF, and the capacitors C8, C9 have a capacitance of 4.7 uF.
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| CN117498887A (en) * | 2024-01-02 | 2024-02-02 | 湖南慧明谦数字能源技术有限公司 | MBUS master node circuit driven by double-power operational amplifier |
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| CN201886347U (en) * | 2010-12-18 | 2011-06-29 | 重庆市智能水表有限责任公司 | M-BUS controller |
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Address after: 702-704, Building A-1, Media Art Industrial Park, No. 601 Dongfanghong North Road, High tech Development Zone, Changsha City, Hunan Province, 410000 Patentee after: Hunan Huimingqian Digital Energy Technology Co.,Ltd. Address before: U508, 5th floor, incubation, training and logistics building (CHUANGYOU building), No.2 Lujing Road, Changsha hi tech Development Zone, Hunan 410000 Patentee before: HUNAN HUIMINGQIAN INFORMATION TECHNOLOGY Co.,Ltd. |