CN117135142B - Address allocation device and method for performance test of flexible production line of electric automobile motor - Google Patents

Address allocation device and method for performance test of flexible production line of electric automobile motor Download PDF

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Publication number
CN117135142B
CN117135142B CN202311394795.4A CN202311394795A CN117135142B CN 117135142 B CN117135142 B CN 117135142B CN 202311394795 A CN202311394795 A CN 202311394795A CN 117135142 B CN117135142 B CN 117135142B
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address
slave device
addressing
master device
slave
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CN117135142A (en
Inventor
沈建新
严伟灿
王云冲
史丹
朱子昂
于丰源
唐兆鹏
章友豪
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5038—Address allocation for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/34—Testing dynamo-electric machines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Small-Scale Networks (AREA)

Abstract

The invention discloses an address allocation device and a method for performance test of an electric automobile motor flexible production line, which relate to the field of communication transmission, and form slave devices by correspondingly providing communication chips, switch chips, terminal resistors R1, a wire inlet end B port and a wire outlet end B port for each performance test device; meanwhile, the anti-interference capability is strong in the automatic addressing process, the automatically allocated address is not repeated or omitted, the communication is stable, the compatibility is good, the automatic addressing time is short, the cost is low, the space is small, and the address can be correctly set in complex and humid industrial environments.

Description

Address allocation device and method for performance test of flexible production line of electric automobile motor
Technical Field
The invention relates to the technical field of communication transmission, in particular to an address allocation device and method for performance test of a flexible production line of an electric automobile motor.
Background
The electric automobile meets the requirements of users well due to the characteristics of the electric automobile such as dynamic property, economy, braking property, smoothness, reliability, pollution discharge and the like, so that the electric automobile has an increasing demand in recent years. Performance testing equipment on flexible production lines of electric automobile motors is also increasing, and networking is required to realize the internet design requirement. The performance test equipment on the flexible production line is generally connected with a computer by adopting RS485, so that an RS485 address is required to be allocated to each performance test equipment on the flexible production line. The address allocation originally adopts a manual allocation method, such as a dial switch mode, and has extremely low efficiency and is easy to make mistakes. In recent years, there have been proposals for address allocation using an automatic identification algorithm, by which RS485 addresses of each test device can be allocated, but since the algorithm cannot perform address setting in the order of connection from the host to each performance test device, when the performance test device is operated and maintained, particularly when a large number of devices are together, the geographic position of the performance test device cannot be quickly located from the allocated addresses.
Disclosure of Invention
Aiming at the problems in the background art, the invention provides the address allocation device and the method for the performance test of the flexible production line of the electric automobile motor, which can automatically allocate addresses according to the connection sequence of the RS485 lines, so that corresponding performance test equipment can be rapidly positioned according to the allocated addresses when a large number of performance test equipment is operated and maintained, a large amount of labor cost is saved, and the automatic allocation of the addresses of batch equipment and the operation and maintenance efficiency are improved; meanwhile, the anti-interference capability is strong in the automatic addressing process, the address automatically allocated to each performance testing device is not repeated or omitted, the communication is stable, the compatibility is good, the automatic addressing time is short, the cost is low, the space is small, and the address can be correctly set in a complex industrial environment.
In order to achieve the above object, the present invention provides the following solutions:
an address allocation device for testing performance of a flexible production line of an electric automobile motor, comprising: a master device, a plurality of slave devices and a termination resistor R3; each slave device comprises performance testing equipment for the flexible production line of the electric automobile motor, a communication chip, a switch chip, a terminal resistor R1, a wire inlet end B and a wire outlet end B which are correspondingly arranged; each switch chip comprises an analog switch S1 and an analog switch S2;
the RS485 communication line A of the master device is connected with the interface A of the communication chip of each slave device; the inlet B of each slave device is connected with the interface B of the communication chip of the slave device; the inlet B and the outlet B of each slave device are respectively connected with two ends of the analog switch S2 of the slave device; the inlet B of each slave device is also connected with one end of the terminal resistor R1 of the slave device; the other end of the terminal resistor R1 of each slave device is connected with one end of the analog switch S1 of the slave device; the other end of the analog switch S1 of each slave device is connected with the RS485 communication line A of the master device; the RS485 communication line B of the master device is connected with the inlet wire end B of the first slave device;
in a plurality of slave devices except the first slave device and the last slave device, a wire inlet end B of each slave device is connected with a wire outlet end B of the last slave device; the outlet B of each slave device is connected with the inlet B of the next slave device;
the inlet B of the last slave device is connected with the outlet B of the last slave device; the outlet B of the last slave device is connected with one end of a terminal resistor R3; the other end of the terminal resistor R3 is connected with an RS485 communication line A of the main equipment; the resistance value of the termination resistor R3 is 120 ohms.
Optionally, the address allocation device for testing performance of the flexible production line of the electric automobile motor further comprises: a termination resistor R2 arranged at the main equipment end; and two ends of the terminal resistor R2 are respectively connected with an RS485 communication line A and an RS485 communication line B of the main equipment.
An address allocation method for performance test of flexible production line of electric automobile motor is applied to an address allocation device for performance test of flexible production line of electric automobile motor; the address allocation method for the performance test of the flexible production line of the electric automobile motor comprises the following steps: addressing preparation process, addressing error processing process and addressing checking process;
the addressing preparation process comprises the following steps: the master device sends a cancel address command COM_1 to the slave device, wherein the parameters comprise a second timer duration value T2; each slave device connected with the RS485 communication line A and the RS485 communication line B of the master device receives the cancel address command COM_1 and then responds as follows: the analog switch S1 is closed, and the analog switch S2 is opened; the slave device sets a second timer duration value T2 and starts a second timer;
the addressing process comprises a process of sending a set address command by the master device, a process of responding to the master device by the first slave device and a process of responding to the slave device by the first master device;
the process of sending the address setting command by the master device comprises the following steps: the master device sends a set address command COM_2 to the slave device;
the first slave device responding to the master device procedure comprises: each slave device connected with the RS485 communication line A and the RS485 communication line B of the master device responds as follows: when the addressing of the slave equipment is normal, sending a modified command COM_3 of the slave equipment, otherwise, sending an error command COM_4 to the master equipment;
the first master device response slave device process includes: if the master device receives the slave device modified command COM_3, addressing the next address until the addressing process is finished, and jumping to the addressing error processing process; if an error command COM_4 is received, jumping to the addressing error processing process;
the addressing error handling process comprises: the slave device delays until the second timer is overtime, and after the second timer is overtime, the analog switch S1 is opened, and the analog switch S2 is closed; if the main equipment has no addressing error at the moment, jumping to the addressing checking process after jumping out of the addressing error processing process; if the addressing of the main equipment is wrong at the moment, jumping to the addressing preparation process and re-addressing; the addressing verification process comprises an address omission verification process and an address repetition verification process.
Optionally, before the addressing preparation process, the first timer duration value T1 and the second timer duration value T2 are initialized first.
Optionally, the addressing error handling process further includes:
judging whether the first timer of the main equipment is overtime, if the first timer is overtime, assigning the first timer duration value T1 to T1 after increasing the preset proportion K1, assigning the second timer duration value T2 to T2 after increasing the preset proportion K2, jumping to the addressing preparation process, and re-addressing.
Optionally, the preset proportion K1 is greater than or equal to the preset proportion K2.
Optionally, the address omission checking process includes:
the master device sends an address omission check command COM_5 to the slave device, wherein parameters comprise a target address value A1, and a fourth timer is started at the same time;
after receiving the address omission check command COM_5, the slave equipment connected with the RS485 communication line A and the RS485 communication line B of the master equipment responds as follows: if the updated address flag bit of the slave device is 0, an address omission check return command COM_6 is sent to the master device; if the address of the slave device is greater than or equal to the last target address value A1, an address omission check return command COM_6 is sent to the master device;
if the master device acquires an address omission check return command COM_6 or receives error information sent by the slave device in the time range of the fourth timer, the master device jumps to the addressing preparation process and re-addresses; if the fourth timer times out and does not receive any information, the address omission checking process is jumped out, and the address repetition checking process is jumped to.
Optionally, the address repetition verification process includes: the master device sends an address repetition check command process, the second slave device responds to the master device process and the second master device responds to the slave device process;
before the main equipment sends an address repetition check command process, setting a current judgment address A3 to be 1;
the process of sending the address repetition check command by the master device comprises the following steps: the master device sends an address repetition check command COM_7 to the slave device, wherein the parameters comprise a current judgment address A3; starting a fifth timer;
the second slave device responding to the master device procedure comprises: after receiving the address repetition check command COM_7, if the address of the slave device is the same as the current judgment address A3 included in the address repetition check command COM_7, the slave device sends an address repetition check return command COM_8 to the master device;
the second master device response slave device process includes: the master device waits for the response of the slave device, and if the master device does not receive any information of the slave device in the fifth timer time, the master device jumps to the addressing preparation process and re-addresses; if the master device receives the slave device information in the fifth timer time, the master device executes according to the following scheme according to the information difference:
if error information is received, jumping to the addressing preparation process and re-addressing;
if more than one address repetition check return command COM_8 is received, jumping to the addressing preparation process and re-addressing;
if only one address repetition check return command COM_8 is received, the value of the current judgment address A3 is added with 1 and then assigned to A3, when the new current judgment address A3 after assignment is equal to the last target address value A1, the address repetition check process is jumped out, the addressing process is ended, and otherwise, the process of jumping to the process of sending the address repetition check command by the main equipment is finished.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
according to the address allocation device and the method for testing the performance of the flexible production line of the electric automobile motor, which are provided by the invention, each performance testing device is correspondingly provided with the communication chip, the switch chip, the terminal resistor R1, the inlet end B port and the outlet end B port to form the slave device, and the address can be automatically allocated to each performance testing device according to the connection sequence of the RS485 line by combining the address allocation method, so that the corresponding performance testing device can be rapidly positioned according to the allocated address when a large number of performance testing devices are operated and maintained, a large number of labor costs are saved, and the automatic allocation of the addresses of batch devices and the operation and maintenance efficiency are improved. Meanwhile, the performance test system has strong anti-interference capability in the automatic addressing process, the address automatically allocated to each performance test device is not repeated or omitted, the communication is stable, the compatibility is good, the automatic addressing time is short, the cost is low, the space is small, the address can be correctly set in the complex and humid industrial environment, and the application prospect is wide.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an address allocation device for testing performance of a flexible production line of an electric automobile motor;
fig. 2 is a schematic diagram of connection between a communication chip and a switch chip according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a main process of an address allocation method for testing performance of a flexible production line of an electric automobile motor.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide an address allocation device and method for performance test of a flexible production line of an electric automobile motor, which can automatically allocate addresses according to the connection sequence of RS485 lines, so that corresponding performance test equipment can be rapidly positioned according to the allocated addresses when a large number of performance test equipment is operated and maintained, a large amount of labor cost is saved, and automatic allocation of addresses of batch equipment and operation and maintenance efficiency are improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Fig. 1 is a schematic structural diagram of an address allocation device for testing performance of a flexible production line of an electric automobile motor. As shown in fig. 1, the address allocation device for testing the performance of the flexible production line of the electric automobile motor of the invention comprises: master, multiple slaves (slave 1, slave 2, slave 3..slave n.), and termination resistor R3. Each slave device comprises performance testing equipment for the flexible production line of the electric automobile motor, and a communication chip IC1, a switch chip, a terminal resistor R1, a wire inlet end B and a wire outlet end B which are correspondingly arranged. Each of the switch chips includes an analog switch S1 and an analog switch S2.
Referring to fig. 1, an RS485 communication line a of the master device is connected with an interface a of a communication chip IC1 of each slave device. The inlet B of each slave device is connected with the interface B of the communication chip IC1 of the slave device; the inlet B and the outlet B of each slave device are respectively connected with two ends of the analog switch S2 of the slave device; the inlet B of each slave device is also connected with one end of the terminal resistor R1 of the slave device; the other end of the terminal resistor R1 of each slave device is connected with one end of the analog switch S1 of the slave device; the other end of the analog switch S1 of each slave device is connected with the RS485 communication line A of the master device. The RS485 communication line B of the master device is connected with a line inlet end B of a first slave device (the slave device 1 in fig. 1).
In a plurality of slave devices except the first slave device and the last slave device, a wire inlet end B of each slave device is connected with a wire outlet end B of the last slave device; the outlet B of each slave device is connected with the inlet B of the next slave device.
The incoming line port B of the last slave device (the slave device N in fig. 1) is connected with the outgoing line port B of the last slave device; the outlet B of the last slave device is connected with one end of a terminal resistor R3; the other end of the terminal resistor R3 is connected with an RS485 communication line A of the main equipment.
Fig. 2 is a schematic diagram of connection between a communication chip and a switch chip according to an embodiment of the present invention. In some embodiments, communication chip IC1 may employ a MAX485 chip, shown as U1 in FIG. 2; the switch chip may be a TS5a23166 chip, shown as U2 in fig. 2. The sixth pin of the MAX485 chip U1 is an interface A of the communication chip IC1, and the transmission signal is A_IN; the seventh pin of the MAX485 chip U1 is an interface B of the communication chip IC1, namely, the inlet wire end B of each slave device, and the transmission signal is B_IN. In addition, the first pin transmission signal of the MAX485 chip U1 is RX_485, the second and third pin transmission signals are EN_485, and the fourth pin transmission signal is TX_485. An analog switch S1 is arranged between the first pin and the second pin of the TS5a23166 chip U2, and the signal en_120 at the third pin is a control signal of the analog switch S1. An analog switch S2 is arranged between the fifth pin and the sixth pin of the TS5a23166 chip U2, and the signal en_b at the seventh pin is a control signal of the analog switch S2. The sixth pin of the TS5A23166 chip U2 is an outlet B of each slave device, and the transmission signal is B_OUT.
R2 is a terminal resistor arranged at the main equipment end; and two ends of the terminal resistor R2 are respectively connected with an RS485 communication line A and an RS485 communication line B of the main equipment. The resistance values of the termination resistor R1, the termination resistor R2 and the termination resistor R3 are 120 ohms.
The invention also provides an address distribution method of the address distribution device for testing the performance of the flexible production line of the electric automobile motor, which mainly comprises four processes of an addressing preparation process, an addressing error processing process and an addressing verification process, as shown in figure 3.
Before the addressing preparation process, a first timer duration value T1 and a second timer duration value T2 are initialized.
Specifically, the addressing preparation process includes:
the master device sends a cancel address command COM_1 to the slave device, wherein the parameters comprise a second timer duration value T2; setting a first timer duration value T1, starting a first timer, initializing a target address value A1 to be 1, and clearing an error mark to be 0;
each slave device connected with the RS485 communication line A and the RS485 communication line B of the master device receives the cancel address command COM_1 and then responds as follows: the current address of the slave device is modified into a special value A2 and stored in the RAM; the analog switch S1 is closed, and the analog switch S2 is opened; clearing the updated address flag to 0; the slave device sets a second timer duration value T2 and starts a second timer.
When setting, it is required to ensure that the second timer duration value T2 is smaller than the first timer duration value T1. The special value A2 may be set to 247.
Specifically, the addressing procedure includes a master sending a set address command procedure, a first slave responding to the master procedure, and a first master responding to the slave procedure.
The process of sending the address setting command by the master device comprises the following steps: the master device sends a set address command com_2 to the slave device, the parameter comprising the target address value A1, and the master device starts a third timer.
The first slave device responding to the master device procedure comprises: each slave device connected with the RS485 communication line A and the RS485 communication line B of the master device performs the following two response processes:
response 1.1): when the current address of the slave equipment is a special value A2, setting the current address of the slave equipment as a target address value A1, storing the target address value A1 into FLASH, setting an updated address mark as 1, sending a modified command COM_3 of the slave equipment to the master equipment, closing an analog switch S2 of the slave equipment after a delay preset time T3, opening the analog switch S1, exiting the process of the first slave equipment responding to the master equipment and jumping to the process of the first master equipment responding to the slave equipment; the duration setting of the preset time T3 needs to ensure that all the information of the modified command COM_3 is completely sent by each slave device;
response 1.2): when the current address of the slave device is not a special value A2 and the updated address mark of the slave device is 0, an error command COM_4 is sent to the master device; or when the current address of the slave device is not a special value A2 and the current address of the slave device is greater than or equal to the target address value A1, an error command COM_4 is also sent to the master device, the first slave device is exited to respond to the master device process and jumps to the first master device to respond to the slave device process.
The first master device response slave device process includes: the master device performs the following two response processes according to the received slave device information conditions:
response 2.1): if the master device does not receive any information in the third timer time, the master device jumps to the addressing error processing process;
response 2.2): if the master device receives the slave device information in the third timer time, the master device executes according to the following four schemes according to different information:
scheme 1.1): if only one slave device modified command COM_3 is received and no other information exists, the master device adds 1 to the target address value A1 and then assigns the value to A1, and the process of the master device sending the address setting command is skipped; the other information comprises all information which can be analyzed according to a default communication protocol and can not be analyzed according to the default communication protocol, and meanwhile, a condition exists that the received information can be analyzed according to the default communication protocol, but at least two different commands exist, and the received information is considered to be received;
scheme 1.2): if error information sent by the slave device is received, the master device sets an error flag as 1, and jumps to the addressing error processing process; the error information is information which is received by the main equipment but can not be analyzed according to a default communication protocol;
scheme 1.3): if more than one slave device modified command COM_3 is received, the master device sets an error flag as 1, and jumps to the addressing error processing process;
scheme 1.4): if one or more error commands COM_4 are received, the master device sets an error flag to be 1, and jumps to the addressing error processing procedure.
Specifically, the addressing error handling procedure includes:
judging whether a first timer of the main equipment is overtime, if the first timer is overtime, assigning a value T1 to the first timer after increasing a preset proportion K1, assigning a value T2 to the second timer after increasing a preset proportion K2, jumping to the addressing preparation process, and re-addressing; the setting range of the preset proportion K1 and the preset proportion K2 is 10% -100%, preferably 30%; but ensuring that the preset proportion K1 is larger than or equal to the preset proportion K2;
the slave device delays until the second timer is overtime, and after the second timer is overtime, the analog switch S1 is opened, and the analog switch S2 is closed;
the master device delays until the first timer times out;
if the error mark of the main equipment is 0 at the moment, jumping out of the addressing error processing process and then jumping to the addressing checking process;
if the error flag of the master device is 1 at this time, the process is skipped to the addressing preparation process and the addressing is re-performed.
Specifically, the address verification process includes an address omission verification process and an address repetition verification process.
The address omission checking process comprises the following steps:
the master device sends an address omission check command COM_5 to the slave device, wherein parameters comprise a target address value A1, and a fourth timer is started at the same time;
after receiving the address omission check command COM_5, the slave equipment connected with the RS485 communication line A and the RS485 communication line B of the master equipment responds as follows: if the updated address flag bit of the slave device is 0, an address omission check return command COM_6 is sent to the master device; if the updated address flag bit of the slave device is not 0, further judging whether the address of the slave device is greater than or equal to the last target address value A1; if the address of the slave device is greater than or equal to the last target address value A1, an address omission check return command COM_6 is also sent to the master device;
if the master device acquires an address omission check return command COM_6 or receives error information sent by the slave device in the time range of the fourth timer, the master device jumps to the addressing preparation process and re-addresses; if the fourth timer times out and does not receive any information, the address omission checking process is jumped out, and the address repetition checking process is jumped to.
Specifically, the address repetition verification process includes: the master device transmits an address repetition check command procedure, a second slave device responds to the master device procedure, and the second master device responds to the slave device procedure.
And before the process of sending the address repetition check command by the master device is executed, setting the current judgment address A3 to be 1.
The process of sending the address repetition check command by the master device comprises the following steps: the master device sends an address repetition check command COM_7 to the slave device, wherein the parameters comprise a current judgment address A3; the fifth timer is started.
The second slave device responding to the master device procedure comprises: after receiving the address repetition check command com_7, if the address of the slave device is the same as the current judgment address A3 included in the address repetition check command com_7, the slave device sends an address repetition check return command com_8 to the master device.
The second master device response slave device process includes: the master device waits for the response of the slave device, and if the master device does not receive any information of the slave device in the fifth timer time, the master device jumps to the addressing preparation process and re-addresses; if the master device receives the slave device information in the fifth timer time, the master device executes according to the following three schemes according to different information:
scheme 2.1): if error information is received, jumping to the addressing preparation process and re-addressing;
scheme 2.2): if more than one address repetition check return command COM_8 is received, jumping to the addressing preparation process and re-addressing;
scheme 2.3): if only one address repeated checking return command COM_8 is received and no other information exists, the value of the current judgment address A3 is added with 1 and then assigned to A3, when the new current judgment address A3 after assignment is equal to the last target address value A1, the address repeated checking process is jumped out, the addressing process is ended, and otherwise, the address repeated checking command process is jumped to the main equipment.
Compared with the prior art, the address allocation device and the method for testing the performance of the flexible production line of the electric automobile motor have at least the following advantages:
1. according to the invention, two ends of the external terminal resistor R3 are respectively connected to the outlet B of the last slave device and the RS485 communication line A of the master device, so that in the addressing process, the last slave device is disconnected from the analog switch S2, and therefore, the terminal resistor R3 is not connected to the RS485 communication lines A and B, and the terminal resistor R3 is invalid and has no interference to the addressing process. Meanwhile, in the non-addressing process, in the normal operation process of the address automatic allocation completion system, because the analog switch S1 is opened, and meanwhile, the analog switch S2 is closed, which is equivalent to the terminal of the access RS485 communication line A and the terminal of the access RS485 communication line B is the terminal resistor R3, and the resistance value of the terminal resistor is 120 ohms, and because the terminal resistor R3 of 120 ohms is connected, communication interference can be greatly reduced when the line is longer, and communication is more stable and reliable. On the contrary, if one end of the terminal resistor R3 is connected to the line inlet B of the last slave device and the other end is connected to the RS485 communication line a, during the addressing process of the last slave device, the master device does not know whether the slave device is the last slave device or not, and the analog switch S1 must be closed by default, so that the terminal resistor is equivalent to parallel connection of R1 and R3, the actual terminal resistor is equivalent to 60 ohms, and the terminal resistor in communication with the RS485 needs to be inconsistent between 100 ohms to 130 ohms, which may cause instability of the system, or even cause that the master device and the slave device of the whole system cannot communicate.
2. Because the switch chip adopts TS5A23166 analog switch chips, two paths of analog switches S1 and S2 are integrated in 1 chip, and the size is only 2.25mm 3.35mm 1.05mm, the occupied circuit board space is small, and the cost of the circuit board is low; and two paths of analog switches are combined by one chip, so that the cost is lower than that of other switches; the height of the analog switch chip is the normal height of the circuit board chip, so that the glue is easy to fill, and the analog switch chip can normally operate in complex and humid industrial environments and the like through glue filling; meanwhile, an analog switch chip is adopted as a switch, and the on-resistance is in the order of milliohms, so that the on-resistance can be ignored; on the contrary, if a relay is adopted as an analog switch, the on-resistance is 10 ohms, and when the number of slave devices is large, the accumulated resistance of the line is obviously increased; in addition, if a relay is used as a switch, coil EMI in the relay may also cause unnecessary noise and glitches. Meanwhile, each slave device only uses 2 analog switches and one connecting wire to be in control connection with the subsequent slave device, compared with the existing scheme of adopting 3 analog switches to be in control connection with the subsequent slave device, the cost of 1 analog switch can be saved, and when the slave device is applied to batch slave devices, the control cost can be greatly saved.
3. In the response processing process 1 of the slave device, when the current address of the slave device is not a special value A2 and the updated address mark of the slave device is 0, an error command COM_4 is sent to the master device; or when the current address of the slave device is not a special value A2 and the current address of the slave device is greater than or equal to a target address value A1, the slave device also sends an error command COM_4' to the master device; this is because, in the automatic addressing process, a slave device is restarted due to interference, the analog switch S2 is automatically closed after the slave device is restarted, the analog switch S1 is opened, which is equivalent to that after the slave device is restarted, the subsequent slave device of the slave device is also connected to the RS485 communication line B of the master device, so that the master device connects the subsequent slave device of the slave device when the slave device is connected, and the slave device and the subsequent slave device of the slave device simultaneously respond when the master device sends an instruction, and the response includes two situations: the first case, the slave device responds with the following slave device at the same time, so that the master device receives information, but the two slave devices simultaneously return information and a shared bus to the master device, so that the master device receives information but cannot decode according to a communication protocol agreed by the master device and the slave device, namely the master device receives error information; in the second case, the processing procedures of the slave device and the subsequent slave device are different, so that the slave device and the subsequent slave device send the return information in sequence, and the slave device and the subsequent slave device do not send information on the A, B bus of the RS485 at the same time, so that the master device receives two commands, the commands can correctly decode the commands, the subsequent slave device reads the original FLASH address A4 when restarting due to restarting, and the subsequent slave device updates the address mark to default to 0, A4 is not a special value and returns the information to the master device for classification, and the following 3 cases exist: a4 The following slave device return information should be the error command com_4 because of the fact that =a1, A4> A1, A4< A1, and for this purpose, re-automatic addressing is required, ensuring that automatic addressing is not missed and not repeated, and addressing errors are found during addressing rather than by checking after waiting for addressing to end, so that the automatic addressing process can be completed in a minimum time. Further, the interference may also include that the slave device receives the master device transmission cancel address command com_1 during the automatic addressing preparation process, the analog switch S1 is normally closed, and the analog switch S2 is opened, however, if the slave device is interfered at this time, the analog switch S2 is not opened but is in a closed state, then the subsequent slave device of the interfered slave device and the interfered slave device are simultaneously connected or disconnected with the master device, the master device only transmits an instruction to the interfered slave device, but since the analog switch S2 of the interfered slave device is closed, the master device also corresponds to transmitting an instruction to the subsequent slave device of the interfered slave device, and the subsequent slave device of the interfered slave device also responds to the master device.
4. Through the setting of the second timer, when the second timer time delay of the slave device arrives, the analog switch S1 is opened, the analog switch S2 is closed, the terminal resistor R3 is equivalent to the terminal, and the whole slave device is equivalent to the connection state when being restored to normal use, so that the condition that the slave device is missed due to the fact that the slave device is not on the line or the condition that the terminal resistor is not on the terminal can not occur when the addressing verification process is finally carried out. By setting the time length of the first timer to be longer than the second timer, i.e. T1> T2, it is further ensured that the slave device has recovered to the normal use connection state when the master device performs the addressing check. In the addressing error processing process, whether the first timer of the main equipment overtime is judged first, if the first timer overtime, the time length value T1 of the first timer and the time length value T2 of the second timer are increased and then the addressing is re-addressed again, so that even if the initially set time length value T1 of the first timer and the time length value T2 of the second timer are too small, the follow-up remedial measures still remain, and the time length value T1 of the first timer can be set to be a smaller value at the beginning, so that the automatic addressing process can be ensured to be completed in the shortest time.
5. In the addressing process, some slave devices already automatically encode addresses through addressing, when the master device addresses the following slave devices, if the analog switch S2 of a certain slave device is interfered, the analog switch S2 is disconnected, the interfered following slave devices cannot be connected with the master device until the third timer of the master device is overtime, that is, the interfered following slave devices cannot respond to the master device, that is, no information is returned to the master device, the master device can mistakenly consider that the interfered following slave device is the last slave device, therefore, the addressing process is finished, however, in fact, the slave device is not addressed at the moment, and then the addressing error can be caused if the addressing verification process is not performed. In the addressing verification process, the address omission verification process finds out the slave equipment without the coded address by updating the address flag bit 0 or the current address is greater than or equal to the last target address value A1; the address repetition checking process sequentially sends an address repetition checking command COM_7 to each slave device from small to large according to the address value (the previous value of the target address value A1, namely the difference between A1 and 1), the master device only has an address repetition checking return command COM_8 sent by the slave device and has no other information after acquiring each time, otherwise, the slave device address code repetition can be judged; thus, the address verification process ensures that the address automatically allocated for each performance test apparatus is neither repeated nor missed. And the addressing can be automatically readdressed once being disturbed, so the invention has very strong anti-interference capability and ensures the stability of the addressing process.
6. Setting the information which does not conform to the data frame format as error information as long as the information is found in the third timer time, and considering addressing errors; in the third timer time, if a plurality of pieces of information are found to be returned to the main device, namely the second response case of the advantage 3, addressing errors are also considered; due to the existence of the third timer, the master device can jump to the next operation without receiving a correct frame data, and the problem that some error information is comprehensively captured due to interference of the system is further solved. The effect of the fifth timer is similar to that of the third timer, and in the fifth timer, the judgment that the master device does not receive any information of the slave device in the time of the fifth timer, jumps to the addressing preparation process and re-addresses is added, so that the system addressing is further ensured to be neither repeated nor missed.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.

Claims (6)

1. The address allocation method for the performance test of the flexible production line of the electric automobile motor is characterized by being applied to an address allocation device for the performance test of the flexible production line of the electric automobile motor; the address allocation device for the performance test of the flexible production line of the electric automobile motor comprises: a master device, a plurality of slave devices and a termination resistor R3; each slave device comprises performance testing equipment for the flexible production line of the electric automobile motor, a communication chip, a switch chip, a terminal resistor R1, a wire inlet end B and a wire outlet end B which are correspondingly arranged; each switch chip comprises an analog switch S1 and an analog switch S2;
the RS485 communication line A of the master device is connected with the interface A of the communication chip of each slave device; the inlet B of each slave device is connected with the interface B of the communication chip of the slave device; the inlet B and the outlet B of each slave device are respectively connected with two ends of the analog switch S2 of the slave device; the inlet B of each slave device is also connected with one end of the terminal resistor R1 of the slave device; the other end of the terminal resistor R1 of each slave device is connected with one end of the analog switch S1 of the slave device; the other end of the analog switch S1 of each slave device is connected with the RS485 communication line A of the master device; the RS485 communication line B of the master device is connected with the inlet wire end B of the first slave device;
in a plurality of slave devices except the first slave device and the last slave device, a wire inlet end B of each slave device is connected with a wire outlet end B of the last slave device; the outlet B of each slave device is connected with the inlet B of the next slave device;
the inlet B of the last slave device is connected with the outlet B of the last slave device; the outlet B of the last slave device is connected with one end of a terminal resistor R3; the other end of the terminal resistor R3 is connected with an RS485 communication line A of the main equipment; the resistance value of the terminal resistor R3 is 120 ohms;
the address allocation method for the performance test of the flexible production line of the electric automobile motor comprises the following steps: addressing preparation process, addressing error processing process and addressing checking process;
the addressing preparation process comprises the following steps: the master device sends a cancel address command COM_1 to the slave device, wherein the parameters comprise a second timer duration value T2; each slave device connected with the RS485 communication line A and the RS485 communication line B of the master device receives the cancel address command COM_1 and then responds as follows: the analog switch S1 is closed, and the analog switch S2 is opened; the slave device sets a second timer duration value T2 and starts a second timer;
the addressing process comprises a process of sending a set address command by the master device, a process of responding to the master device by the first slave device and a process of responding to the slave device by the first master device;
the process of sending the address setting command by the master device comprises the following steps: the master device sends a set address command COM_2 to the slave device;
the first slave device responding to the master device procedure comprises: each slave device connected with the RS485 communication line A and the RS485 communication line B of the master device responds as follows: when the addressing of the slave equipment is normal, sending a modified command COM_3 of the slave equipment, otherwise, sending an error command COM_4 to the master equipment;
the first master device response slave device process includes: if the master device receives the slave device modified command COM_3, addressing the next address until the addressing process is finished, and jumping to the addressing error processing process; if an error command COM_4 is received, jumping to the addressing error processing process;
the addressing error handling process comprises: the slave device delays until the second timer is overtime, and after the second timer is overtime, the analog switch S1 is opened, and the analog switch S2 is closed; if the main equipment has no addressing error at the moment, jumping to the addressing checking process after jumping out of the addressing error processing process; if the addressing of the main equipment is wrong at the moment, jumping to the addressing preparation process and re-addressing; the addressing verification process comprises an address omission verification process and an address repetition verification process.
2. The address allocation method for testing the performance of the flexible production line of the electric automobile motor according to claim 1, wherein the address preparation process is preceded by initializing a first timer duration value T1 and a second timer duration value T2.
3. The address allocation method for testing the performance of the flexible production line of the electric automobile motor according to claim 2, wherein the addressing error processing procedure further comprises:
judging whether the first timer of the main equipment is overtime, if the first timer is overtime, assigning the first timer duration value T1 to T1 after increasing the preset proportion K1, assigning the second timer duration value T2 to T2 after increasing the preset proportion K2, jumping to the addressing preparation process, and re-addressing.
4. The address allocation method for testing the performance of the flexible production line of the electric automobile motor according to claim 3, wherein the preset proportion K1 is larger than or equal to the preset proportion K2.
5. The address allocation method for testing the performance of the flexible production line of the electric automobile motor according to claim 1, wherein the address omission checking process comprises the following steps:
the master device sends an address omission check command COM_5 to the slave device, wherein parameters comprise a target address value A1, and a fourth timer is started at the same time;
after receiving the address omission check command COM_5, the slave equipment connected with the RS485 communication line A and the RS485 communication line B of the master equipment responds as follows: if the updated address flag bit of the slave device is 0, an address omission check return command COM_6 is sent to the master device; if the address of the slave device is greater than or equal to the last target address value A1, an address omission check return command COM_6 is sent to the master device;
if the master device acquires an address omission check return command COM_6 or receives error information sent by the slave device in the time range of the fourth timer, the master device jumps to the addressing preparation process and re-addresses; if the fourth timer times out and does not receive any information, the address omission checking process is jumped out, and the address repetition checking process is jumped to.
6. The address allocation method for testing the performance of the flexible production line of the electric automobile motor according to claim 5, wherein the address repetition verification process comprises: the master device sends an address repetition check command process, the second slave device responds to the master device process and the second master device responds to the slave device process;
before the main equipment sends an address repetition check command process, setting a current judgment address A3 to be 1;
the process of sending the address repetition check command by the master device comprises the following steps: the master device sends an address repetition check command COM_7 to the slave device, wherein the parameters comprise a current judgment address A3; starting a fifth timer;
the second slave device responding to the master device procedure comprises: after receiving the address repetition check command COM_7, if the address of the slave device is the same as the current judgment address A3 included in the address repetition check command COM_7, the slave device sends an address repetition check return command COM_8 to the master device;
the second master device response slave device process includes: the master device waits for the response of the slave device, and if the master device does not receive any information of the slave device in the fifth timer time, the master device jumps to the addressing preparation process and re-addresses; if the master device receives the slave device information in the fifth timer time, the master device executes according to the following scheme according to the information difference:
if error information is received, jumping to the addressing preparation process and re-addressing;
if more than one address repetition check return command COM_8 is received, jumping to the addressing preparation process and re-addressing;
if only one address repetition check return command COM_8 is received, the value of the current judgment address A3 is added with 1 and then assigned to A3, when the new current judgment address A3 after assignment is equal to the last target address value A1, the address repetition check process is jumped out, the addressing process is ended, and otherwise, the process of jumping to the process of sending the address repetition check command by the main equipment is finished.
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