CN111650988A - Voltage stabilizer - Google Patents

Abstract

The invention discloses a voltage stabilizer, and belongs to the field of electronics. The voltage stabilizer comprises a bias circuit, a voltage stabilizing circuit and an output circuit; the voltage stabilizer can start to work and realize the voltage stabilizing function when the power supply voltage exceeds the preset stable voltage of the chip; when the internal main power supply works normally, the voltage stabilizer can assist the main power supply to output current, and when the main power supply in the chip is abnormal, the voltage stabilizer provides stable voltage to keep the internal data of the chip from losing. The voltage stabilizer can provide continuous and stable voltage for certain circuits under the condition that the main power supply in the chip is not started, and the condition that the chip is abnormally powered down or data is lost before starting due to the main power supply in the chip is avoided.

Description

Voltage stabilizer

Technical Field

The invention relates to the field of electronics, in particular to a sub-microampere voltage stabilizer.

Background

Currently, most power management chips generally use a low dropout regulator (LDO) for voltage stabilization, and a conventional LDO is generally configured as shown in fig. 1, where an output terminal VOUT is fed back to an input terminal of an amplifier through a voltage divider resistor to complete closed-loop control, and such LDO usually consumes relatively large power consumption (e.g., over 5 uA). However, in some application scenarios requiring low power consumption (e.g., the electronic device is in a standby state), although the LDO does not need to operate continuously, in order to prevent some modules from losing data due to power failure, an ultra-low power consumption voltage regulator module is still needed to supply power to the modules continuously. The existing low dropout linear regulator cannot meet the requirements of the scenes.

Disclosure of Invention

In view of the above problems, a voltage regulator is provided, which is capable of providing a continuous and stable voltage for some circuits under power consumption and without turning on the main power supply inside the chip.

The present invention provides a voltage regulator including:

the bias circuit comprises two first output ends and two second output ends and is used for converting an input voltage into a first bias voltage signal and a second bias voltage signal;

the voltage stabilizing circuit comprises a first input end, a second input end and a third output end, wherein the first input end is connected with the first output end, the second input end is connected with the second output end, and the voltage stabilizing circuit is used for outputting a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal;

and the output circuit comprises a third input end, a fourth input end and a fourth output end, the third input end is connected with the third output end, the fourth input end is connected with the second output end, and the output circuit is used for generating a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal and outputting the second voltage signal.

Preferably, the bias circuit further includes:

the source electrode of the first PMOS tube is connected with a power supply end, and the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube;

a source electrode of the second PMOS tube is connected with a source electrode of the first PMOS tube and the power supply end, and a grid electrode of the second PMOS tube is connected with a grid electrode of the first PMOS tube and a drain electrode of the first PMOS tube;

the drain electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube to form a first output end of the bias circuit;

the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the second PMOS tube are connected to form a second output end of the bias circuit;

one end of the first resistor is connected with the source electrode of the first NMOS tube, and the other end of the first resistor is connected with the source electrode of the second NMOS tube and grounded.

Preferably, the voltage stabilizing circuit further comprises:

a grid electrode of the third PMOS tube forms a first input end of the voltage stabilizing circuit, and a source electrode of the third PMOS tube is connected with a power supply end;

the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the third PMOS tube is grounded;

a grid electrode of the fourth NMOS tube forms a second input end of the voltage stabilizing circuit, and a source electrode of the fourth NMOS tube is grounded;

a grid electrode of the sixth NMOS tube is connected with a drain electrode of the third PMOS tube and a drain electrode of the third NMOS tube, and the drain electrode of the sixth NMOS tube is connected with a source electrode of the third PMOS tube;

one end of the second resistor is connected with the grid electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube, and the other end of the second resistor is connected with the source electrode of the sixth NMOS tube to form a third output end of the voltage stabilizing circuit.

Preferably, the output circuit further includes:

a grid electrode of the fifth NMOS tube forms a fourth input end of the output circuit, and a source electrode of the fifth NMOS tube is grounded;

and the grid electrode of the seventh NMOS tube forms a third input end of the output circuit, the drain electrode of the seventh NMOS tube is connected with a power supply end, and the source electrode of the seventh NMOS tube and the drain electrode of the fifth NMOS tube are connected to form a fourth output end of the output circuit.

The beneficial effects of the above technical scheme are that:

in the technical scheme, the voltage stabilizer comprises a bias circuit, a voltage stabilizing circuit and an output circuit; the voltage stabilizer can start to work and realize the voltage stabilizing function when the power supply voltage exceeds the preset stable voltage of the chip; when the internal main power supply works normally, the voltage stabilizer can assist the main power supply to output current, and when the main power supply in the chip is abnormal, the voltage stabilizer provides stable voltage to keep the internal data of the chip from losing. The voltage stabilizer can provide continuous and stable voltage for certain circuits under the condition that the main power supply in the chip is not started, and the condition that the chip is abnormally powered down or data is lost before starting due to the main power supply in the chip is avoided.

Drawings

FIG. 1 is a circuit diagram of a conventional LDO;

FIG. 2 is a circuit diagram of one embodiment of the bias circuit of the present invention;

FIG. 3 is a circuit diagram of one embodiment of a voltage regulator circuit according to the present invention;

FIG. 4 is a circuit diagram of one embodiment of a voltage regulator according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

As shown in fig. 2 to 4, the present invention provides a voltage regulator including: a bias circuit 1, a voltage stabilizing circuit 2 and an output circuit 3; wherein the content of the first and second substances,

a bias circuit 1 including two first and second output terminals VB1 and VB2 for converting an input voltage into first and second bias voltage signals;

further, as shown in fig. 2 and 4, the bias circuit 1 may further include: the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1, the second NMOS tube MN2 and the first resistor R1;

a first PMOS transistor MP1, wherein a source of the first PMOS transistor MP1 is connected to a power supply terminal VCC, and a gate of the first PMOS transistor MP1 is connected to a drain of the first PMOS transistor MP 1;

a second PMOS transistor MP2, wherein a source of the second PMOS transistor MP2 is connected to a source of the first PMOS transistor MP1 and the power supply terminal VCC, and a gate of the second PMOS transistor MP2 is connected to a gate of the first PMOS transistor MP1 and a drain of the first PMOS transistor MP 1;

a first NMOS transistor MN1, a drain of the first NMOS transistor MN1 is connected to a gate of the first PMOS transistor MP1, a drain of the first PMOS transistor MP1 and a gate of the second PMOS transistor MP2 to form a first output terminal VB1 of the bias circuit 1;

a second NMOS transistor MN2, a source of the second NMOS transistor MN2 is grounded, and a gate of the second NMOS transistor MN2 is connected with a drain of the second NMOS transistor MN2, a gate of the first NMOS transistor MN1, and a drain of the second PMOS transistor MP2 to form a second output terminal VB2 of the bias circuit 1;

one end of the first resistor R1 is connected to the source of the first NMOS transistor MN1, and the other end of the first resistor R1 is connected to the ground to the source of the second NMOS transistor MN 2.

The voltage stabilizing circuit 2 comprises a first input end, a second input end and a third output end VB3, the first input end is connected with the first output end VB1, the second input end is connected with the second output end VB2, and the voltage stabilizing circuit 2 is used for outputting a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal;

further, as shown in fig. 3 and 4, the voltage stabilizing circuit 2 may further include: a third PMOS transistor MP3, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a sixth NMOS transistor MN6, and a second resistor RM;

a third PMOS transistor MP3, a gate of the third PMOS transistor MP3 forming a first input terminal of the voltage regulator circuit 2, and a source of the third PMOS transistor MP3 connected to a power supply terminal VCC;

a third NMOS transistor MN3, a drain of the third PMOS transistor MP3 is connected to the drain of the third PMOS transistor MP3, and a source of the third PMOS transistor MP3 is grounded;

a fourth NMOS transistor MN4, a gate of the fourth NMOS transistor MN4 forming a second input terminal of the voltage regulator circuit 2, and a source of the fourth NMOS transistor MN4 being grounded;

a sixth NMOS transistor MN6, a gate of the sixth NMOS transistor MN6 is connected to the drain of the third PMOS transistor MP3 and the drain of the third NMOS transistor MN3, and a drain of the sixth NMOS transistor MN6 is connected to the source of the third PMOS transistor MP 3;

one end of the second resistor RM is connected with the gate of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4, and the other end of the second resistor RM is connected with the source of the sixth NMOS transistor MN6 to form a third output end VB3 of the voltage stabilizing circuit 2.

The second resistor RM is a trimming resistor.

And the output circuit 3 comprises a third input end, a fourth input end and a fourth output end, the third input end is connected with the third output end VB3, the fourth input end is connected with the second output end VB2, and the output circuit 3 is used for generating a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal and outputting the second voltage signal.

Further, as shown in fig. 3 and 4, the output circuit 3 may further include: a fifth NMOS transistor MN5 and a seventh NMOS transistor MN 7;

a fifth NMOS transistor MN5, a gate of the fifth NMOS transistor MN5 forms a fourth input terminal of the output circuit 3, and a source of the fifth NMOS transistor MN5 is grounded;

a seventh NMOS transistor MN7, a gate of the seventh NMOS transistor MN7 forms a third input terminal of the output circuit 3, a drain of the seventh NMOS transistor MN7 is connected to a power supply terminal VCC, and a source of the seventh NMOS transistor MN7 and a drain of the fifth NMOS transistor MN5 are connected to form a fourth output terminal of the output circuit 3.

In the bias circuit 1, the current flowing through the first PMOS transistor MP1 is defined by the ratio of the gate-source voltage difference between the second NMOS transistor MN2 and the first NMOS transistor MN1 to the first resistor R1, and the first PMOS transistor MP1 mirrors the current value to the third PMOS transistor MP3 by means of a current mirror. As shown in fig. 3, the gate quiescent point of the sixth NMOS transistor MN6 is determined by the current flowing through the third PMOS transistor MP3, the gate quiescent point of the third NMOS transistor MN3 is determined by the current flowing through the fourth NMOS transistor MN4, and meanwhile, the third NMOS transistor MN3 and the sixth NMOS transistor MN6 form a negative feedback, when the drain voltage of the third PMOS transistor MP3 rises, the gate-source voltage difference of the sixth NMOS transistor MN6 increases, so that the gate voltage of the third NMOS transistor MN3 decreases, thereby lowering the drain voltage of the third PMOS transistor MP3, and achieving the purpose of rapidly stabilizing the operating point. Because the fourth NMOS transistor MN4 mirrors the drain current of the second NMOS transistor MN2 in a current mirror manner, the gate quiescent operating points of the third NMOS transistor MN3 and the sixth NMOS transistor MN6 can be effectively adjusted by adjusting the second resistor RM while the width-to-length ratio of the fourth NMOS transistor MN4 remains unchanged. As shown in fig. 4, there are: VOUT is equal to V_G7-V_GS7Therefore, the voltage stabilizing function can be realized under the condition of small load current.

In this embodiment, the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, the second NMOS transistor MN2, and the first resistor R1 generate a dc bias, and the static operating points of the third NMOS transistor MN3, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7 are stabilized by changing the resistance of the second resistor RM, so as to stabilize the output voltage. The third PMOS transistor MP3, the sixth NMOS transistor MN6 and the third NMOS transistor MN3 form a negative feedback structure, and the working point can be quickly stabilized when the power supply voltage suddenly changes. The circuit has the advantages of novel structure, adjustable output voltage, no need of capacitance compensation, small occupied chip area, cost saving and the like.

In the embodiment, when the power supply voltage exceeds the preset stable voltage of the chip, the voltage stabilizer starts to work and realizes the voltage stabilizing function; when the internal main power supply works normally, the voltage stabilizer can assist the main power supply to output current, and when the main power supply in the chip is abnormal, the voltage stabilizer provides stable voltage to keep the internal data of the chip from losing. The voltage stabilizer can provide continuous and stable voltage for certain circuits under the condition that the main power supply in the chip is not started, and the condition that the chip is abnormally powered down or data is lost before starting due to the main power supply in the chip is avoided. The voltage stabilizer has the advantages of novel structure, adjustable output voltage, no need of capacitance compensation, small occupied chip area, cost saving and the like.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (4)

1. A voltage regulator, comprising:

the bias circuit comprises two first output ends and two second output ends and is used for converting an input voltage into a first bias voltage signal and a second bias voltage signal;

the voltage stabilizing circuit comprises a first input end, a second input end and a third output end, wherein the first input end is connected with the first output end, the second input end is connected with the second output end, and the voltage stabilizing circuit is used for outputting a first voltage signal according to the input voltage, the first bias voltage signal and the second bias voltage signal;

and the output circuit comprises a third input end, a fourth input end and a fourth output end, the third input end is connected with the third output end, the fourth input end is connected with the second output end, and the output circuit is used for generating a second voltage signal according to the input voltage, the first voltage signal and the second bias voltage signal and outputting the second voltage signal.

2. The voltage regulator of claim 1, wherein the bias circuit further comprises:

the source electrode of the first PMOS tube is connected with a power supply end, and the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube;

a source electrode of the second PMOS tube is connected with a source electrode of the first PMOS tube and the power supply end, and a grid electrode of the second PMOS tube is connected with a grid electrode of the first PMOS tube and a drain electrode of the first PMOS tube;

the drain electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube to form a first output end of the bias circuit;

the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the second PMOS tube are connected to form a second output end of the bias circuit;

one end of the first resistor is connected with the source electrode of the first NMOS tube, and the other end of the first resistor is connected with the source electrode of the second NMOS tube and grounded.

3. The voltage regulator of claim 1, wherein the voltage regulation circuit further comprises:

a grid electrode of the third PMOS tube forms a first input end of the voltage stabilizing circuit, and a source electrode of the third PMOS tube is connected with a power supply end;

the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the third PMOS tube is grounded;

a grid electrode of the fourth NMOS tube forms a second input end of the voltage stabilizing circuit, and a source electrode of the fourth NMOS tube is grounded;

a grid electrode of the sixth NMOS tube is connected with a drain electrode of the third PMOS tube and a drain electrode of the third NMOS tube, and the drain electrode of the sixth NMOS tube is connected with a source electrode of the third PMOS tube;

one end of the second resistor is connected with the grid electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube, and the other end of the second resistor is connected with the source electrode of the sixth NMOS tube to form a third output end of the voltage stabilizing circuit.

4. The voltage regulator of claim 1, wherein the output circuit further comprises:

a grid electrode of the fifth NMOS tube forms a fourth input end of the output circuit, and a source electrode of the fifth NMOS tube is grounded;

and the grid electrode of the seventh NMOS tube forms a third input end of the output circuit, the drain electrode of the seventh NMOS tube is connected with a power supply end, and the source electrode of the seventh NMOS tube and the drain electrode of the fifth NMOS tube are connected to form a fourth output end of the output circuit.

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