CN111628060A - Gallium nitride epitaxial chip and preparation method thereof - Google Patents

Gallium nitride epitaxial chip and preparation method thereof Download PDF

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Publication number
CN111628060A
CN111628060A CN202010548161.XA CN202010548161A CN111628060A CN 111628060 A CN111628060 A CN 111628060A CN 202010548161 A CN202010548161 A CN 202010548161A CN 111628060 A CN111628060 A CN 111628060A
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gallium nitride
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lattice
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李东键
叶宏伦
钟健
刘崇志
张本义
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Aksu Silicon Card Semiconductor Technology R & D Co ltd
Xinjiang Can Ke Semiconductor Material Manufacturing Co ltd
Can Long Technology Development Co Ltd
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Aksu Silicon Card Semiconductor Technology R & D Co ltd
Xinjiang Can Ke Semiconductor Material Manufacturing Co ltd
Can Long Technology Development Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials

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Abstract

The invention relates to a gallium nitride epitaxial chip and a preparation method thereof, wherein the gallium nitride epitaxial chip comprises a substrate, a seed layer, a buffer layer and a gallium nitride epitaxial layer, wherein the seed layer is arranged on the substrate, and the buffer layer is arranged between the seed layer and the gallium nitride epitaxial layer; the buffer layer comprises more than two groups of super lattice layers, each group of super lattice layers is formed by compounding an aluminum nitride layer and a gallium nitride layer, and the aluminum nitride layers and the gallium nitride layers are alternately stacked from the seed layers to the direction of the gallium nitride epitaxial layer; the thickness ratio of the aluminum nitride layer to the gallium nitride layer in the super lattice layer is x, and the x of each super lattice layer in the buffer layer is gradually reduced from the seed layer to the gallium nitride epitaxial layer. The invention can improve the growth thickness of the gallium nitride under the condition of ensuring the dislocation density of the gallium nitride lattice arrangement.

Description

Gallium nitride epitaxial chip and preparation method thereof
Technical Field
The invention relates to the field of semiconductor materials, in particular to a gallium nitride epitaxial chip and a preparation method thereof.
Background
At present, the group III/V nitride semiconductor materials mainly include GaN (gallium nitride), InGaN (indium gallium nitride), and AlGaN (aluminum gallium nitride). Such materials are used in optoelectronic devices, semiconductor laser devices, light emitting diodes, high electron mobility transistors, etc. The energy gap characteristic of the nitride semiconductor material can be continuously modulated (non-step) between 1.9 to 6.2 eV. It has excellent physical and chemical stability and high saturated electron mobility, and is ideal material for high power, high frequency and light emitting device.
Gallium nitride single crystals do not exist in the natural world and cannot be obtained from the natural world, and therefore, they are produced by manual methods. The current manufacturing method is to find a single crystal material as the base, called substrate, and then grow gan film on the substrate. Because of the different substrate materials, there is no perfect match. Cracking easily occurs during thermal expansion, and dislocations in the substrate material are carried into the gallium nitride layer and then amplified. Therefore, a problem has been solved by growing an aluminum nitride AlN buffer layer of one more layer using another material.
The existing buffer layer is difficult to grow gallium nitride GaN with the thickness of 1 micron or more, and the arrangement dislocation density (dislocation density) of atoms in the gallium nitride GaN crystal lattice layer is 5x108/cm2The following mass.
Disclosure of Invention
In view of the problems in the prior art, an object of the present invention is to provide a gallium nitride crystal epitaxial wafer and a method for manufacturing the same, which can increase the growth thickness of gallium nitride while ensuring the dislocation density of the gallium nitride lattice arrangement.
In order to achieve the purpose, the invention adopts the technical scheme that:
a gallium nitride epitaxial chip comprises a substrate, a seed layer, a buffer layer and a gallium nitride epitaxial layer, wherein the seed layer is arranged on the substrate, and the buffer layer is arranged between the seed layer and the gallium nitride epitaxial layer;
the buffer layer comprises more than two groups of super lattice layers, each group of super lattice layers is formed by compounding an aluminum nitride layer and a gallium nitride layer, and the aluminum nitride layers and the gallium nitride layers are alternately stacked from the seed layers to the direction of the gallium nitride epitaxial layer; the thickness ratio of the aluminum nitride layer to the gallium nitride layer in the super lattice layer is x, and the x of each super lattice layer in the buffer layer is gradually reduced from the seed layer to the gallium nitride epitaxial layer.
In the super lattice layer, the aluminum nitride layer and an adjacent gallium nitride layer form an aluminum-gallium pair, each super lattice layer comprises a plurality of aluminum-gallium pairs, and the thickness ratio of the aluminum nitride layer to the gallium nitride layer of each aluminum-gallium pair is the same and is x.
The thickness of each super-lattice layer of the buffer layer is gradually reduced from the seed layer to the gallium nitride epitaxial layer.
The thickness ratio x of the aluminum nitride layer to the gallium nitride layer in the super lattice layer is 0.2-1.9.
The number of stacked layers of aluminum nitride and gallium nitride in the superlattice layer is more than 20.
The thickness of the buffer layer is 200-300nm, and the thickness of the super-lattice layer is 50-150 nm.
The seed layer is an AlN layer with the thickness of 100-200 nm.
A preparation method of a gallium nitride epitaxial chip comprises the following steps:
growing a seed layer, a buffer layer and a gallium nitride epitaxial layer on a substrate in sequence, wherein the buffer layer comprises N groups of super lattice layers; the specific growth process is as follows:
growing an aluminum nitride seed layer on the substrate;
alternately stacking more than 20 aluminum nitride layers and gallium nitride layers on the seed layer to form a first group of super lattice layers;
continuously and alternately stacking more than 20 layers of aluminum nitride and gallium nitride on the first group of superlattice layers to form a second group of superlattice layers;
continuing to grow the aluminum nitride layer and the gallium nitride layer to form an Nth group of super lattice layers;
and finally, growing a gallium nitride epitaxial layer on the Nth group of super-lattice layers.
The growth method of the seed layer, the buffer layer and the gallium nitride epitaxial layer is a hydride vapor phase epitaxy method, a molecular beam epitaxy method or an organic metal chemical vapor deposition method.
After the scheme is adopted, the seed layer and the buffer layer are additionally arranged between the substrate and the gallium nitride epitaxial layer, so that the matching performance of characteristics such as lattice coefficient, thermal expansion coefficient and the like between the gallium nitride and the substrate is improved. Specifically, the aluminum nitride ratio in the super-lattice layer of the buffer layer between the substrate and the gallium nitride epitaxial layer is changed, so that the aluminum nitride ratio is gradually reduced, and the gallium nitride ratio is gradually increased, thereby improving the lattice coefficient matching degree of the substrate and the gallium nitride, and improving the growth thickness of the gallium nitride under the condition of ensuring the dislocation density of the lattice arrangement of the gallium nitride.
Drawings
FIG. 1 is a schematic view of a GaN epitaxial chip according to the present invention.
Description of reference numerals:
a substrate 1; a seed layer 2; a gallium nitride epitaxial layer 3; a buffer layer 4; a superlattice layer 41.
Detailed Description
As shown in FIG. 1, the present invention discloses a GaN epitaxial chip, which can be high-insulation GaN, P-type GaN or N-type GaN. The gallium nitride epitaxial chip comprises a substrate 1, a seed layer 2, a buffer layer 4 and a gallium nitride epitaxial layer 3, wherein the seed layer 2 is arranged on the substrate 1, and the buffer layer 4 is arranged between the seed layer 2 and the gallium nitride epitaxial layer 3.
The buffer layer 4 comprises more than two groups of super lattice layers 41, each group of super lattice layers 41 is formed by compounding an aluminum nitride layer and a gallium nitride layer, and the aluminum nitride layer and the gallium nitride layer are alternately stacked from the seed layer 2 to the gallium nitride epitaxial layer 3; the thickness ratio of the aluminum nitride layer to the gallium nitride layer in the super-lattice layer 41 is x, and the x of each super-lattice layer 41 in the buffer layer 4 is gradually reduced from the seed layer 2 to the gallium nitride epitaxial layer 3.
Further, the thickness of each superlattice layer 41 of the buffer layer 4 gradually decreases from the seed layer 2 to the gallium nitride epitaxial layer 3, and the number of stacked layers of aluminum nitride and gallium nitride in each superlattice layer 41 is more than 20.
Further, in the super-lattice layer 41, the aluminum nitride layer and an adjacent gallium nitride layer form an aluminum-gallium pair, each group of super-lattice layer 41 includes a plurality of aluminum-gallium pairs, the thickness ratio of the aluminum nitride layer to the gallium nitride layer of each aluminum-gallium pair in the same super-lattice layer 41 is the same, and x is 0.2-1.9.
The thickness of the buffer layer 4 is 200-300nm, and the thickness of the super-lattice layer 41 is 50-150 nm. And the seed layer 2 is an AlN layer having a thickness of 100-200 nm.
Based on the same inventive concept, the invention also discloses a method for preparing the gallium nitride epitaxial chip, which comprises the following steps: a seed layer 2, a buffer layer 4 and a gallium nitride epitaxial layer 3 are sequentially grown on a substrate 1, wherein the buffer layer 4 comprises N groups of super lattice layers 41; the specific growth process is as follows:
growing an aluminum nitride seed layer 2 on a substrate 1; substrate 1 may be Al2O3 substrate 1, SiC substrate 1, or Si substrate 1.
Alternately stacking more than 20 aluminum nitride layers and gallium nitride layers on the seed layer 2 to form a first group of super-lattice layers 41;
continuously and alternately stacking more than 20 layers of aluminum nitride and gallium nitride on the first group of superlattice layers 41 to form a second group of superlattice layers 41;
continuing to grow the aluminum nitride layer and the gallium nitride layer to form an Nth group of super-lattice layers 41;
finally, a gallium nitride epitaxial layer 3 is grown on the nth set of superlattice layers 41.
The growth method of the seed layer 2, the buffer layer 4 and the gallium nitride epitaxial layer 3 is hydride vapor phase epitaxy, molecular beam epitaxy or organic metal chemical vapor deposition.
For the purpose of elaborating the present invention, the following description will be made by referring to several examples in which the seed layer 2, the buffer layer 4 and the gallium nitride epitaxial layer 3 are grown by using an organometallic chemical vapor deposition method M0 CVD.
Example one
In this embodiment, the gan epitaxial chip includes a substrate 1, a seed layer 2, a buffer layer 4 and a gan epitaxial layer 3, wherein the buffer layer 4 includes two sets of super lattice layers 41, i.e., a first super lattice layer and a second super lattice layer, the first super lattice layer is connected to the seed layer 2, the second super lattice layer is connected to the gan epitaxial layer 3, the first super lattice layer has a thickness of 90nm and the second super lattice layer has a thickness of 60nm, the number of stacked layers of aluminum nitride and gallium nitride in the first super lattice layer and the second super lattice layer is 30, the thickness ratio of aluminum nitride and gallium nitride in the first super lattice layer is 1.9, and the thickness ratio of aluminum nitride and gallium nitride in the second super lattice layer is 1.4.
The growth thickness of the gallium nitride epitaxial layer 3 in this example was 1 μm, and the dislocation defect density was 5 × 108/cm2No cracks and other phenomena occurred.
Example two
Unlike the first embodiment, the buffer layer 4 in this embodiment includes three super-lattice layers 41, namely, a first super-lattice layer, a second super-lattice layer and a third super-lattice layer, the first super-lattice layer is connected to the seed layer 2, the third super-lattice layer is connected to the gallium nitride epitaxial layer 3, and the second super-lattice layer is disposed between the first super-lattice layer and the third super-lattice layer. The thickness of the first superlattice layer is 90nm, the thickness of the second superlattice layer is 80nm, and the thickness of the third superlattice layer is 50 nm; the number of stacked aluminum nitride layers and gallium nitride layers in the three groups of super-lattice layers is 20, wherein the thickness ratio of the aluminum nitride to the gallium nitride of the first super-lattice layer is 1.9, the thickness ratio of the aluminum nitride to the gallium nitride of the second super-lattice layer is 1.4, and the thickness ratio of the aluminum nitride to the gallium nitride of the third super-lattice layer is 1.0.
In this example, the growth of the gallium nitride epitaxial layer 3Length and thickness of 1.15 μm, 5X108/cm2No cracks and other phenomena appear.
EXAMPLE III
Different from the first embodiment, in the present embodiment, the buffer layer 4 includes four groups of super-lattice layers 41, that is, a first super-lattice layer, a second super-lattice layer, a third super-lattice layer, and a fourth super-lattice layer, the first super-lattice layer is connected to the seed layer 2, the fourth super-lattice layer is connected to the gallium nitride epitaxial layer 3, and the second super-lattice layer and the third super-lattice layer are sequentially disposed between the first super-lattice layer and the fourth super-lattice layer. The thickness of the first superlattice layer is 90nm, the thickness of the second superlattice layer is 80nm, the thickness of the third superlattice layer is 50nm, and the thickness of the fourth superlattice layer is 30 nm; the number of stacked aluminum nitride layers and gallium nitride layers in the four super-lattice layers is 20, wherein the thickness ratio of the aluminum nitride to the gallium nitride of the first super-lattice layer is 1.9, the thickness ratio of the aluminum nitride to the gallium nitride of the second super-lattice layer is 1.4, the thickness ratio of the aluminum nitride to the gallium nitride of the third super-lattice layer is 1.0, and the thickness ratio of the aluminum nitride to the gallium nitride of the fourth super-lattice layer is 0.6.
In this example, the gallium nitride epitaxial layer 3 was grown to a thickness of 1.3 μm, 5 × 108/cm2No cracks and other phenomena appear.
The above examples were compared with the prior art (comparative example 1 and comparative example 2), and the comparison results are shown in table 1.
Figure DEST_PATH_IMAGE001
TABLE 1
As can be seen from table 1, comparative examples 1 and 2, which are existing gallium nitride epitaxial chips having only the seed layer 2 provided between the substrate 1 and the gallium nitride epitaxial layer 3, were found to have dislocation defect densities of 5x10 when the gallium nitride epitaxial layer 3 was grown to a thickness of 0.05 μm, as seen from comparative examples 1 and 210/cm2(ii) a When the growth thickness of the gallium nitride epitaxial layer 3 was increased to 0.15 μm, cracks occurred in the gallium nitride epitaxial layer 3.
The first embodiment and the second embodiment of the invention have three kindsThe gallium nitride epitaxial chip has a gallium nitride growth thickness of 1 μm or more and a dislocation defect density of 5x108/cm2No cracks appeared. Compared with the prior art, the growth thickness of the gallium nitride epitaxial layer 3 and the quality of the dislocation density of the lattice arrangement of the gallium nitride epitaxial layer are both effectively improved.
The above description is only exemplary of the present invention and is not intended to limit the technical scope of the present invention, so that any minor modifications, equivalent changes and modifications made to the above exemplary embodiments according to the technical spirit of the present invention are within the technical scope of the present invention.

Claims (9)

1. A gallium nitride epitaxial chip is characterized in that: the gallium nitride epitaxial layer buffer layer is arranged between the seed layer and the gallium nitride epitaxial layer;
the buffer layer comprises more than two groups of super lattice layers, each group of super lattice layers is formed by compounding an aluminum nitride layer and a gallium nitride layer, and the aluminum nitride layers and the gallium nitride layers are alternately stacked from the seed layers to the direction of the gallium nitride epitaxial layer; the thickness ratio of the aluminum nitride layer to the gallium nitride layer in the super lattice layer is x, and the x of each super lattice layer in the buffer layer is gradually reduced from the seed layer to the gallium nitride epitaxial layer.
2. A gallium nitride epitaxial chip according to claim 1, wherein: in the super lattice layer, the aluminum nitride layer and an adjacent gallium nitride layer form an aluminum-gallium pair, each super lattice layer comprises a plurality of aluminum-gallium pairs, and the thickness ratio of the aluminum nitride layer to the gallium nitride layer of each aluminum-gallium pair is the same and is x.
3. A gallium nitride epitaxial chip according to claim 1, wherein: the thickness of each super-lattice layer of the buffer layer is gradually reduced from the seed layer to the gallium nitride epitaxial layer.
4. A gallium nitride epitaxial chip according to claim 1, wherein: the thickness ratio x of the aluminum nitride layer to the gallium nitride layer in the super lattice layer is 0.2-1.9.
5. A gallium nitride epitaxial chip according to claim 1, wherein: the number of stacked layers of aluminum nitride and gallium nitride in the superlattice layer is more than 20.
6. A gallium nitride epitaxial chip according to claim 1, wherein: the thickness of the buffer layer is 200-300nm, and the thickness of the super-lattice layer is 50-150 nm.
7. A gallium nitride epitaxial chip according to claim 1, wherein: the seed layer is an AlN layer with the thickness of 100-200 nm.
8. A preparation method of a gallium nitride epitaxial chip is characterized by comprising the following steps:
growing a seed layer, a buffer layer and a gallium nitride epitaxial layer on a substrate in sequence, wherein the buffer layer comprises N groups of super lattice layers; the specific growth process is as follows:
growing an aluminum nitride seed layer on the substrate;
alternately stacking more than 20 aluminum nitride layers and gallium nitride layers on the seed layer to form a first group of super lattice layers;
continuously and alternately stacking more than 20 layers of aluminum nitride and gallium nitride on the first group of superlattice layers to form a second group of superlattice layers;
continuing to grow the aluminum nitride layer and the gallium nitride layer to form an Nth group of super lattice layers;
and finally, growing a gallium nitride epitaxial layer on the Nth group of super-lattice layers.
9. A method for preparing a gallium nitride epitaxial chip according to claim 8, characterized in that: the growth method of the seed layer, the buffer layer and the gallium nitride epitaxial layer is a hydride vapor phase epitaxy method, a molecular beam epitaxy method or an organic metal chemical vapor deposition method.
CN202010548161.XA 2020-06-16 2020-06-16 Gallium nitride epitaxial chip and preparation method thereof Pending CN111628060A (en)

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