CN111627939A

CN111627939A - CMOS image sensor packaging module, forming method thereof and camera device

Info

Publication number: CN111627939A
Application number: CN201910147015.3A
Authority: CN
Inventors: 向阳辉
Original assignee: China Core Integrated Circuit Ningbo Co Ltd
Current assignee: China Core Integrated Circuit Ningbo Co Ltd
Priority date: 2019-02-27
Filing date: 2019-02-27
Publication date: 2020-09-04
Anticipated expiration: 2039-02-27
Also published as: WO2020173059A1; CN111627939B

Abstract

The invention provides a CMOS image sensor packaging module, a forming method thereof and an image pickup device. The CMOS image sensor packaging module comprises a pixel circuit substrate and a chip combination structure connected with the pixel circuit substrate, wherein a signal processing chip and a DRAM chip are embedded in a chip forming layer in the chip combination structure, and the signal processing chip and the DRAM chip are electrically connected through a chip interconnection layer. In addition, the packaging module further comprises an interconnection structure and a wiring layer, wherein the interconnection structure is electrically connected with the circuit interconnection end of the reading circuit in the pixel circuit substrate, the signal processing chip and the DRAM chip, and the wiring layer is electrically connected with the interconnection structure. The camera device comprises the CMOS image sensor packaging module.

Description

CMOS image sensor packaging module, forming method thereof and camera device

Technical Field

The invention relates to the field of image sensors, in particular to a CMOS image sensor packaging module, a forming method thereof and an image pickup device.

Background

Due to the requirement of shooting scenes, digital cameras are also arranged on equipment such as notebook computers, tablet computers, smart phones, smart toys and the like at present. The common digital camera projects a generated optical image onto the surface layer of the photosensitive element through a camera lens, light rays are decomposed into different color lights by filters on the surface layer of the photosensitive element, each color light is sensed by a pixel unit corresponding to each filter, analog signals with different intensities are generated, then the signals are collected by a circuit of the photosensitive element, the analog signals are converted into digital signals through a digital-to-analog converter, then the digital signals are processed by an Image Signal Processor (ISP), then the digital signals are sent to a mobile phone processor for processing, and then the digital signals are transmitted to a memory card for storage to form an image which can be viewed on a screen.

A commonly used photosensitive element is a back-illuminated CMOS (Complementary Metal oxide semiconductor) image sensor. Compared with a CCD image sensor, a CMOS image sensor enables more flexible image capturing, higher sensitivity, wider dynamic range, higher resolution, lower power consumption, and more excellent system integration, etc. In addition, light is incident from the back of the CMOS image sensor and does not need to penetrate through an interconnection layer on the photosensitive element, namely, the light is emitted to the photosensitive element, light loss is reduced, and in unit time, light energy which can be acquired by a single pixel unit is larger, so that the picture quality is obviously improved.

However, as the requirements for the size and imaging quality of the CMOS image sensor are increased, the structure of the CMOS image sensor package module needs to be further optimized.

Disclosure of Invention

In view of the above problems, the present invention provides a CMOS image sensor package module and a method for forming the same, so as to optimize the structure of the CMOS image sensor package module and improve the imaging quality when shooting with the CMOS image sensor package module.

According to an aspect of the present invention, there is provided a CMOS image sensor package module including:

the CMOS image sensor comprises a pixel circuit substrate and a pixel circuit substrate, wherein the pixel circuit substrate comprises a photosensitive area and a read-out circuit area, a pixel array of the CMOS image sensor is arranged in the photosensitive area, the read-out circuit is arranged in the read-out circuit area and is provided with a circuit interconnection end, and the pixel circuit substrate comprises a first surface and a second surface which are opposite; the bonding layer is laid on the first surface; the chip combination structure is arranged on the first surface at intervals of the bonding layer and comprises a chip forming layer, a dielectric layer and a chip interconnection layer which are sequentially overlapped, wherein a signal processing chip and a DRAM (dynamic random access memory) chip are embedded in the chip forming layer, the signal processing chip is provided with a first connecting end and a second connecting end, the DRAM chip is provided with a third connecting end and a fourth connecting end, and the chip interconnection layer is electrically connected with the first connecting end and the third connecting end respectively through a first electric connecting piece and a second electric connecting piece which are arranged in the dielectric layer; an interconnection structure disposed in the pixel circuit substrate and the bonding layer, the interconnection structure being electrically connected to the circuit interconnection terminal, the second connection terminal, and the fourth connection terminal; and a rewiring layer laid on the second surface, the rewiring layer being electrically connected to the interconnect structure.

Optionally, the chip interconnection layer is interposed between the bonding layer and the chip molding layer, or the chip molding layer is interposed between the bonding layer and the chip interconnection layer.

Optionally, the interconnection structure includes a first conductive plug disposed in the pixel circuit substrate, and the first conductive plug is electrically connected to the circuit interconnection end and the redistribution layer.

Optionally, the circuit interconnection terminal includes a first circuit interconnection terminal and a second circuit interconnection terminal, and the second interconnection structure includes two first conductive plugs to electrically connect the first circuit interconnection terminal and the redistribution layer and the second circuit interconnection terminal and the redistribution layer, respectively.

Optionally, the interconnect structure includes a second conductive plug penetrating through the pixel circuit substrate and the bonding layer, and the second conductive plug electrically connects the signal processing chip and the rewiring layer.

Optionally, the interconnect structure includes a third conductive plug penetrating through the pixel circuit substrate and the bonding layer, the third conductive plug electrically connecting the DRAM chip and the rewiring layer.

Optionally, the redistribution layer includes a redistribution layer and a pad electrically connected to the redistribution layer.

Optionally, the CMOS image sensor package module further includes: and the dummy chip is arranged on the first surface through the bonding layer.

Optionally, the chip combination structure is disposed on the first surface corresponding to the readout circuit region, incident light is set to enter the pixel array from the second surface side, and the dummy chip is disposed on the first surface corresponding to the photosensitive region.

Optionally, the CMOS image sensor is a back-illuminated CMOS image sensor.

Optionally, the bonding layer comprises an adhesive material.

Optionally, the first electrical connector and the second electrical connector are conductive plugs.

According to another aspect of the present invention, there is provided an image pickup apparatus including the above-described CMOS image sensor package module.

According to still another aspect of the present invention, there is provided a method of forming a CMOS image sensor package module, including the steps of:

forming a chip combined structure, wherein the chip combined structure comprises a chip forming layer, a dielectric layer and a chip interconnection layer which are sequentially overlapped, a signal processing chip and a DRAM chip are embedded in the chip forming layer, the signal processing chip is provided with a first connecting end and a second connecting end, the DRAM chip is provided with a third connecting end and a fourth connecting end, and the chip interconnection layer is respectively and electrically connected with the first connecting end and the third connecting end through a first electric connecting piece and a second electric connecting piece which are arranged in the dielectric layer; bonding the chip combination structure and a pixel circuit substrate, wherein the pixel circuit substrate comprises a photosensitive area and a reading circuit area, a pixel array of the CMOS image sensor is arranged in the photosensitive area, the reading circuit is arranged in the reading circuit area, the reading circuit is provided with a circuit interconnection end, the pixel circuit substrate comprises a first surface and a second surface which are opposite, and the chip combination structure is arranged on the first surface in a spaced bonding mode; forming an interconnection structure disposed in the pixel circuit substrate and the bonding layer, the interconnection structure being electrically connected to the circuit interconnection terminal, the second connection terminal, and the fourth connection terminal; and forming a rewiring layer on the second surface, wherein the rewiring layer is electrically connected with the interconnection structure.

Optionally, the method for forming the chip combination structure includes:

providing a temporary carrier plate, and parallelly jointing the signal processing chip and the DRAM chip on the temporary carrier plate, wherein the first connecting end and the third connecting end face the jointing surface of the temporary carrier plate; forming a chip molding layer including the signal processing chip, the DRAM chip, and an encapsulation material covering the signal processing chip, the DRAM chip, and the temporary carrier; removing the temporary carrier plate to expose the first connection end and the third connection end; forming a dielectric layer on the chip forming layer, wherein the dielectric layer covers the first connecting end and the third connecting end; forming a first electrical connector and a second electrical connector in the dielectric layer, the first electrical connector being electrically connected with the first connection end, the second electrical connector being electrically connected with the third connection end; and forming a chip interconnection layer on the dielectric layer, wherein the chip interconnection layer is electrically connected with the first electric connecting piece and the second electric connecting piece, so that the chip combined structure is obtained.

Optionally, the method for forming the chip combination structure includes:

providing a temporary carrier plate, and parallelly jointing the signal processing chip and the DRAM chip on the temporary carrier plate, wherein the first connecting end and the third connecting end face to one side far away from the jointing surface of the temporary carrier plate; forming a chip molding layer including the signal processing chip, the DRAM chip, and an encapsulation material covering the signal processing chip, the DRAM chip, and the temporary carrier; forming a dielectric layer on the chip forming layer, wherein the dielectric layer covers the first connecting end and the third connecting end; forming a first electrical connector and a second electrical connector in the dielectric layer, the first electrical connector being electrically connected with the first connection end, the second electrical connector being electrically connected with the third connection end; and forming a chip interconnection layer on the dielectric layer, wherein the chip interconnection layer is electrically connected with the first electric connecting piece and the second electric connecting piece, so that the chip combined structure is obtained.

Optionally, the temporary carrier board is removed before or after the step of bonding the chip combining structure and the pixel circuit substrate.

Optionally, the chip combining structure is a bonding unit of chip scale size.

Optionally, in the step of bonding the chip combination structure and the pixel circuit substrate, a dummy chip is further bonded on the first surface.

Optionally, the chip combining structure and the pixel circuit substrate are both wafer-level structures, and when the chip combining structure and the pixel circuit substrate are bonded, the chip combining structure and the pixel circuit substrate are opposite and bonded according to the wafer-level size.

Optionally, the chip combination structure further includes a dummy chip embedded in the chip molding layer.

Optionally, the method for forming the interconnect structure includes performing a hole etching process and a hole filling process from the second surface side to form a plurality of conductive plugs.

Optionally, the plurality of conductive plugs include a first conductive plug, and the first conductive plug is formed in the pixel circuit substrate and electrically connects the circuit interconnection terminal and the rewiring layer.

Optionally, the plurality of conductive plugs include a second conductive plug, and the second conductive plug passes through the pixel circuit substrate and the bonding layer and electrically connects the second connection terminal and the redistribution layer.

Optionally, the plurality of conductive plugs includes a third conductive plug, and the third conductive plug passes through the pixel circuit substrate and the bonding layer and electrically connects the fourth connection terminal and the redistribution layer.

The CMOS image sensor packaging module provided by the invention comprises a pixel circuit substrate and a chip combined structure connected with the pixel circuit substrate, wherein the chip combined structure comprises a chip forming layer, a dielectric layer and a chip interconnection layer which are sequentially overlapped, a signal processing chip and a DRAM chip are embedded in the chip forming layer, the signal processing chip is provided with a first connecting end and a second connecting end, the DRAM chip is provided with a third connecting end and a fourth connecting end, the chip interconnection layer is respectively and electrically connected with the first connecting end and the third connecting end through a first electric connecting piece and a second electric connecting piece which are arranged in the dielectric layer, in addition, the CMOS image sensor packaging module also comprises an interconnection structure arranged in the pixel circuit substrate and the connection layer and a rewiring layer arranged on the other side of the pixel circuit substrate, the interconnection structure and the circuit interconnection end of a reading circuit, The second connecting end of the signal processing chip and the fourth connecting end of the DRAM chip are electrically connected, and the wiring layer is electrically connected with the interconnection structure, so that the electrical interconnection among the pixel circuit substrate, the signal processing chip and the DRAM chip is realized, the structure of the packaging module is optimized, the digital image signals output by the reading circuit are conveniently buffered in the DRAM chip and then transmitted to the signal processing chip by the DRAM chip for processing, and when the CMOS image sensor packaging module is used for image shooting, the processing speed of the transmitted data and the digital image signals is favorably improved, and the image quality is further improved.

The camera device provided by the invention comprises the CMOS image sensor packaging module, thereby having the same or similar advantages with the CMOS image sensor packaging module.

The CMOS image sensor packaging module can be formed by the method for forming the CMOS image sensor packaging module. The chip combination structure is formed firstly, wherein the chip combination structure comprises a chip forming layer embedded with a signal processing chip and a DRAM chip and a chip interconnection layer for interconnecting a first connecting end of the signal processing chip and a third connecting end of the DRAM chip, then the chip combination structure is jointed with a pixel circuit substrate, and further an interconnection structure electrically connected with a circuit interconnection end of a reading circuit, a second connecting end of the signal processing chip and a fourth connecting end of the DRAM chip is formed in the pixel circuit substrate and a jointing layer, a rewiring layer is formed on a second surface (the surface opposite to the chip combination structure) of the pixel circuit substrate, and the rewiring layer is electrically connected with the interconnection structure, so that the integration among the chips and the integration of the chip combination structure and the pixel circuit substrate are realized, the process is simple, and the cost is low. The DRAM chip can be used as a cache element in a CMOS image sensor packaging module, and is beneficial to improving the processing speed of transmitted data and digital image signals when being used for image shooting, thereby improving the image quality.

Drawings

Fig. 1 is a schematic cross-sectional view illustrating a signal processing chip and a DRAM chip bonded on a temporary carrier in a method for forming a CMOS image sensor package module according to an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view illustrating a dielectric layer and first and second electrical connectors formed in a method for forming a CMOS image sensor package module according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view illustrating a chip interconnection layer formed in a method for forming a CMOS image sensor package module according to an embodiment of the invention.

Fig. 4 is a schematic cross-sectional view illustrating a chip connection structure bonded on a pixel circuit substrate in a method for forming a CMOS image sensor package module according to an embodiment of the invention.

Fig. 5 is a schematic cross-sectional view illustrating a CMOS image sensor package module after an interconnect structure is formed according to a method for forming the CMOS image sensor package module according to an embodiment of the invention.

Fig. 6 is a schematic cross-sectional view illustrating a redistribution layer formed in a method for forming a CMOS image sensor package module according to an embodiment of the invention.

Description of reference numerals:

100-pixel circuit substrate; 100 a-a first surface; 100 b-a second surface; 101-a first circuit interconnect; 102-a second circuit interconnect; 10-a dummy chip; 110-an interconnect structure; 111-a first conductive plug; 112-a second conductive plug; 113-a third conductive plug;

200-chip combination structure; 210-a chip molding layer; 220-a dielectric layer; 230-chip interconnect layer; 201 — a first electrical connection; 202-a second electrical connection;

20-a signal processing chip; 21-a first connection end; 22-a second connection end; 30-DRAM chips; 31-a third connection end; 32-a fourth connection end; 300-a bonding layer; 400-rewiring layer; 40-a temporary carrier plate; 500-encapsulation layer.

Detailed Description

The current CMOS image signal processor is often integrated on a pixel circuit substrate provided with a photosensitive element by an soc (system on chip) technology, or is bonded with the pixel circuit substrate provided with the photosensitive element by a wafer-level bonding method (usually, metal and oxide mixed bonding is adopted), which has great process difficulty and high cost, and the wafer-level bonding method has great difficulty in processing a defective chip on a signal processing wafer, for example, and also increases the cost. In addition, when the package module of the CMOS image sensor is applied to digital image capturing, digital signals obtained through the pixel circuits (or readout circuits) on the pixel circuit substrate are directly output to the image signal processor for processing, and then stored in the memory card through the mobile phone processor, the speed (for example, frame rate) at which the photosensitive element and the pixel circuits process data is limited by the processing speed of the image signal processor and the processing speed of the mobile phone processor, which easily affects the image capturing quality. As the requirements for the size of the package module of the CMOS image sensor, the imaging quality, and the like increase, the package structure and the packaging method of the CMOS image sensor still need to be improved.

Based on the above research, the present invention provides a CMOS image sensor package module, in which a chip combination structure including a signal processing chip and a DRAM chip is bonded to a first surface of a pixel circuit substrate, wherein the chip combination structure includes a chip molding layer in which the signal processing chip and the DRAM chip are embedded, a dielectric layer, and a chip interconnection layer interconnecting a first connection end of the signal processing chip and a third connection end of the DRAM chip, a circuit interconnection end of an interconnection structure and a readout circuit disposed in the pixel circuit substrate and the bonding layer, a second connection end of the signal processing chip, and a fourth connection end of the DRAM chip are electrically connected, and a wiring layer is disposed on a side surface of the pixel circuit substrate opposite to the chip combination structure, thereby achieving electrical interconnection among the pixel circuit substrate, the signal processing chip, and the DRAM chip, optimizing a structure of the package module, and facilitating buffering of a digital image signal output from the readout circuit to the DRAM chip, and the DRAM chip is transmitted to the signal processing chip for processing, and when the CMOS image sensor packaging module is used for image shooting, the processing speed of transmitted data and digital image signals is favorably improved, and the image quality is further improved.

The CMOS image sensor package module, the method for forming the same, and the image pickup apparatus according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be understood that the following examples are merely illustrative of specific embodiments to which the present invention may be applied and are not to be construed as limiting the scope of the present invention.

It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Corresponding numerals and symbols in the different drawings generally refer to corresponding parts unless otherwise specified. Also, the terms "first," "second," and the like in the following description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.

The present embodiment first describes a CMOS image sensor package module. Referring to fig. 6, the CMOS image sensor package module of the present embodiment includes a pixel circuit substrate 100, a photosensitive area i and a readout circuit area ii (fig. 5 illustrates positions of the photosensitive area i and the readout circuit area ii, and ranges of the photosensitive area i and the readout circuit area ii may not be limited to the areas illustrated in the drawings) are disposed in the pixel circuit substrate 100, a pixel array of the CMOS image sensor is disposed in the photosensitive area i, where the pixel array of the CMOS image sensor refers to an array of pixel units including photodiodes of the CMOS image sensor, and a readout circuit is disposed in the readout circuit area ii, and the photodiodes and the readout circuit are formed in the pixel circuit substrate 100 in the corresponding area by using a semiconductor process. The readout circuit has circuit interconnect terminals for interconnection. For convenience of description, the pixel circuit substrate 100 of the present embodiment includes a first surface 100a and a second surface 100b that are opposite.

The pixel circuit substrate 100 may be a substrate (e.g., a wafer) for fabricating a CMOS image sensor on a substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and the material of the substrate may further include germanium, silicon carbide, gallium arsenide, indium gallium or other iii or v compounds. The CMOS image sensor in this embodiment is preferably a back-illuminated CMOS image sensor because of known advantages. In a back-illuminated CMOS image sensor, a planarization layer for planarization, a color filter layer (not shown) for obtaining light of different colors, and a lens layer (not shown) for increasing the incident amount of light are usually thinned and disposed on a back side of a substrate (i.e., an opposite side of the substrate when a photodiode is formed), and on a front side of the substrate (i.e., a side on which the photodiode is formed), a pixel circuit substrate includes a photosensitive layer in which a plurality of photodiodes are disposed, and millions of pixel cells (pixel or pixel units) are disposed in the photosensitive layer, each pixel cell including, for example, a photodiode and a plurality of MOS transistors serving as a driving circuit, and in operation, light is incident from the lens layer, enters the pixel cells in the photosensitive layer through the color filter layer and the medium layer, and forms a photocurrent. In the pixel circuit substrate, a plurality of different areas may be provided according to different functions, and the pixel units distributed in an array are usually provided in the photosensitive region i, and peripheral circuits are provided around the photosensitive region i, so that the photosensitive region i and the readout circuit region ii also correspond to different areas of the surface of the pixel circuit substrate 100. The interconnection layer formed on the photosensitive layer may include a plurality of interconnection metal layers stacked together and a plug layer connecting adjacent two interconnection metal layers, the interconnection layer being for electrically connecting the photodiode, the driving circuit and the peripheral circuit to process a photocurrent signal of the photodiode. The peripheral circuit may further include an analog Signal processing circuit, an analog-to-digital conversion circuit, a digital logic circuit, a readout circuit, and the like, where the readout circuit is disposed in the readout circuit region ii, and in the readout circuit region ii, the digital Image Signal processed on the pixel circuit substrate 100 is output or used to transmit other signals, and the output digital Image Signal enters an Image Signal Processor (ISP) or an Image Signal processing chip for further processing. The specific structure of the pixel array substrate can also be implemented with reference to the disclosed technology. In another embodiment, the CMOS image sensor may also employ a front-illuminated CMOS image sensor, or employ a stacked CMOS image sensor.

In this embodiment, for example, a side surface of the pixel circuit substrate 100 on which an interconnection layer is formed is used as the first surface 100a, a side surface on which light is incident is used as the second surface 100b, the pixel circuit substrate 100 may sequentially include a planarization layer, a circuit layer and an interconnection layer (which may also include a lens layer and a color filter layer, not shown) along the second surface 100b toward the first surface 100a corresponding to the readout circuit region ii, the planarization layer may be used to planarize the surface of the substrate and serve as an electrical isolation layer, the circuit layer includes the readout circuit, the circuit layer may be the same process layer as the photosensitive layer of the photosensitive region i, the interconnection layer is laminated on the circuit layer and the circuit interconnection terminals of the readout circuit are disposed therein, the circuit interconnection terminals may specifically include a plurality of connection terminals for different connection purposes, and include, for example, a first circuit interconnection terminal 101 and a second circuit interconnection terminal 102, the first circuit interconnection 101 and the second circuit interconnection 102 may transmit image digital signals or other signals by being connected to an external chip or circuit.

Referring to fig. 5, in the CMOS image sensor package module of the present embodiment, the bonding layer 300 is laid on the first surface 100a of the pixel circuit substrate 100. The material of the bonding layer 300 may include an oxide or other suitable material. For example, the signal processing chip and the DRAM chip may be bonded to the first surface 100a of the pixel circuit substrate 100 by fusion bonding, vacuum bonding, or the like. The bonding layer 300 may further include an adhesive material, such as a Die Attach Film (DAF) or a dry film (dry film), for bonding the signal processing chip and the DRAM chip to the first surface 100a of the pixel circuit substrate 100 by bonding. The material of the bonding layer 300 in this embodiment is, for example, a dry film.

The chip combining structure 200 is bonded to the pixel circuit substrate 100, and in the embodiment, the bonding on the first surface 100a is taken as an example for description, and correspondingly, a redistribution layer may be disposed on the second surface 100 b. It should be understood that in another embodiment, the chip combination structure may be bonded to the second surface 100b, and a redistribution layer may be disposed on the first surface 100 a.

Referring to fig. 5, the chip assembly structure 200 is disposed on the first surface 100a of the pixel circuit substrate 100 with the bonding layer 300 interposed therebetween, the chip assembly structure 200 includes a chip molding layer 210, a dielectric layer 220, and a chip interconnection layer 230 sequentially stacked, wherein the chip molding layer 210 has a signal processing chip 20 and a DRAM chip 30 embedded therein, the signal processing chip 20 has a first connection end 21 and a second connection end 22, the DRAM chip 30 has a third connection end 31 and a fourth connection end 32, and the chip interconnection layer 230 is electrically connected to the first connection end 21 and the third connection end 31 through a first electrical connector 201 and a second electrical connector 202 disposed in the dielectric layer 220, respectively.

The chip combining structure 200 can be flexibly bonded to the pixel circuit substrate 100 in a suitable orientation as required, for example, in an embodiment, the chip interconnection layer 230 can be bonded toward the first surface 100a of the pixel circuit substrate 100 as shown in fig. 6, with the chip interconnection layer 230 interposed between the bonding layer 300 and the chip molding layer 210, and in another embodiment, the chip interconnection layer 230 can be bonded in a direction away from the first surface 100a of the pixel circuit substrate 100, with the chip molding layer 210 interposed between the bonding layer 300 and the chip interconnection layer 230.

Specifically, the chip molding layer 210 may embed the signal processing chip 20 and the DRAM chip 30 with an encapsulating material such as a molding material, for example, one of thermosetting resins such as phenol resin, urea resin, formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, polyimide, and the like. Dielectric layer 220 may be an insulating material such as an oxide, nitride, oxynitride, etc. to provide electrical connections therein. The first electrical connection members 201 and the second electrical connection members 202 function as electrical connections between the signal processing chip 20 and the chip interconnection layer 230, and between the DRAM chip 30 and the chip interconnection layer 230, respectively, and in the present embodiment, the first electrical connection members 201 and the second electrical connection members 202 are, for example, conductive plugs.

The above-described die attach structure 200 is preferably formed using a fan-out (fan out) process that provides a more economical multi-chip integration solution that facilitates high-density routing and smaller and thinner packages. In this embodiment, the chip combination structure 200 packages the signal processing chip 20 and the DRAM chip 30 into an integrated structure, so that the process is more convenient and the cost is lower when the integrated structure is bonded to a pixel circuit substrate. In a preferred embodiment, the chip combining structure 200 may be a bonding unit of a chip scale size after being cut, so as to be bonded to an appropriate area of the pixel circuit substrate 100 in a chip scale (die level) manner, and the chip combining structure 200 may also be a wafer scale structure, so as to be bonded to the pixel circuit substrate 100 in a wafer scale (wafer level) manner. In the case of a chip-scale bonding unit, the chip combination structure 200 may be disposed on the readout circuit region ii (e.g., on one side or the other side where light is incident) of the pixel circuit substrate 100 to avoid the influence on the photosensitive region i. But not limited thereto, the die attach structure 200 may be bonded to other areas on the first surface 100a without affecting the pixel array where light is incident on the photosensitive area.

The signal processing chip 20 may be an Image Signal Processor (ISP) or a Digital Signal Processor (DSP). Taking the image signal processor as an example, it may process the output data of the pixel circuit substrate 100, for example, perform processing such as Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), color correction, Lens correction (Lens Shading), Gamma (Gamma) correction, dead pixel removal, and Auto black balance (Auto black level). In addition, the DRAM chip 30 is a Dynamic Random Access Memory (DRAM) chip, which is a common system Memory device, and the DRAM chip stores data using a capacitor and is refreshed at intervals, and if a Memory cell is not refreshed, the stored information is lost, so that the DRAM chip can be used as a cache of a system. The present embodiment provides the DRAM chip 30 in the chip combining structure 200, wherein one purpose is that through its interconnection with the signal processing chip 20 and the pixel circuit substrate 100, when the CMOS image sensor package module of the present embodiment is used in an image capturing device (e.g., a camera of a mobile phone), the DRAM chip 30 can be used to store captured high-speed image information and output at an optimum rate of an input interface according to a system design.

The signal processing chip 20 and the DRAM chip 30 may be chips that are designed and manufactured independently (with respect to a signal processing circuit integrated on a pixel circuit substrate), and specifically may be bare chips to be packaged (different from chips that are not cut on a wafer), and with respect to a signal processing circuit integrated on a pixel circuit substrate, the independent signal processing chip has better operational capability and imaging quality, and when used in a mobile device such as a mobile phone, the independent signal processing chip may be customized by a mobile phone vendor to a chip vendor, which is helpful for achieving better fitting with other components of a camera, and by being longitudinally bonded on the pixel circuit substrate 100, the size of the pixel circuit substrate 100 in the transverse direction is reduced, thereby reducing the size of the whole package module. It is to be understood that the present embodiment focuses on the CMOS image sensor package module including the pixel circuit substrate 100 and the chip combination structure 200, but does not mean that the CMOS image sensor package module of the present embodiment includes only the above components, and other chips (such as an analog signal processing chip, an analog-to-digital conversion chip, a logic chip, and the like) or other devices (such as a power device, a bipolar device, a resistor, a capacitor, and the like) may be disposed/bonded on the pixel circuit substrate 100, and the devices and connection relationships known in the art may also be included therein.

Referring to fig. 6, the CMOS image sensor package module of the present embodiment further includes an interconnection structure 110, and the interconnection structure 110 is disposed in the pixel circuit substrate 100 and the bonding layer 300 to interconnect the readout circuitry of the pixel circuit substrate 100 with the signal processing chip 20 and the DRAM chip 30. Specifically, the interconnect structure 110 is electrically connected to the circuit interconnect terminals (including the first circuit interconnect terminal 101 and the second circuit interconnect terminal 102 in the present embodiment) of the readout circuit, the second connection terminal 22 of the signal processing chip 20, and the fourth connection terminal 32 of the DRAM chip 30. Since the DRAM chip 30 and the signal processing chip 20 in the chip combining structure 200 are already interconnected by the chip interconnection layer 230, the CMOS image sensor package module of the present embodiment may implement interconnection between the DRAM chip 30 and any two of the signal processing chip 200 and the pixel circuit substrate 100 through the chip combining structure 200 and the interconnection structure 110, and optimize the package structure. Through the design of the transmission signal, when the CMOS image sensor package module is used for image shooting, for example, the digital image signal output by the readout circuit is buffered in the DRAM chip 30, and then transmitted to the signal processing chip 20 by the DRAM chip 30 for processing, which is beneficial to improving the processing speed of the transmitted data and the digital image signal, and further improving the image quality.

The end portions (or electrical contacts) of the interconnection structure 110 may extend to the second surface 100b of the pixel circuit substrate 100 to reroute the signal terminals connected thereto. Referring to fig. 6, the CMOS image sensor package module of the present embodiment may further include a re-wiring layer 400 (or a re-wiring layer, RDL) laid on the second surface 100b, wherein the re-wiring layer 400 is electrically connected to the interconnection structure 110. The re-wiring layer 400 may include a re-wiring and a pad (I/Opad) electrically connected to the re-wiring. In order to avoid the influence of light incident on the photosensitive region i, the rewiring layer 500 is preferably laid on the second surface 100b corresponding to the peripheral area of the pixel circuit substrate 100.

The interconnection structure 110 may include one or more electrical contacts, electrical connections, and electrical connection lines formed between the pixel circuit substrate 100 and the bonding layer 300. Specifically, in an embodiment of the present invention, the interconnect structure 110 may include a first conductive plug 111 disposed in the pixel circuit substrate 100, one end of the first conductive plug 111 contacts a circuit interconnect terminal (for example, the first circuit interconnect terminal 101 or the second circuit interconnect terminal 102 is connected) of an electrically connected readout circuit, and the other end faces the second surface 100b and is electrically connected to the redistribution layer 400. In an embodiment of the present invention, the interconnect structure 110 includes a second conductive plug 112, one end of the second conductive plug 112 contacts the second connection terminal 22 of the signal processing chip 20, and the other end faces the second surface 100b and is electrically connected to the redistribution layer 400. In an embodiment of the present invention, the interconnect structure 110 further includes a third conductive plug 113, one end of the third conductive plug 113 contacts the fourth connection terminal 32 electrically connected to the DRAM chip 30, and the other end faces the second surface 100b and is electrically connected to the redistribution layer 400. Referring to fig. 6, in the present embodiment, the interconnect structure 110 includes the first conductive plug 111, the second conductive plug 112, and the third conductive plug 113. Further, the first conductive plug 111 may be more than one in order to correspond to different circuit interconnection terminals connecting the readout circuit. In this embodiment, the interconnect structure 110 includes two first conductive plugs 111 to electrically connect the first circuit interconnect terminal 101 and the second circuit interconnect terminal 102 with the redistribution layer 400, respectively.

It should be noted that the interconnect structure 110 and the redistribution layer 400 in the drawings are only examples, for example, in some embodiments, the redistribution layer 400 may also be connected to each conductive plug (or electrical connector) of the interconnect structure 110. Each of the interconnect structure 110 and the re-routing layer 400 and the electrical connections therebetween may be designed according to a specific circuit to achieve a predetermined function, and are not limited to those shown in the drawings.

Generally, in the first surface 100a of the pixel circuit substrate 100, the area corresponding to the photosensitive region i is larger, and the area corresponding to the peripheral circuit is smaller, so in order to optimize the packaging effect, the CMOS image sensor package module may include a dummy chip (dummy chip)10 to control the warpage of the package module, the dummy chip 10 is, for example, a silicon chip, and is selected according to the specific situation of the pixel circuit substrate 100 and the size of the dummy chip, for example, one or more dummy chips may be bonded to the pixel array region i (the side opposite to the light incident surface), and the dummy chip 10 may be embedded in the chip combining structure 200 to be bonded to the pixel circuit substrate 100, or may be bonded to the pixel circuit substrate 100 alone.

The CMOS image sensor package module of the present embodiment includes a pixel circuit substrate 100, a chip combination structure 200 bonded on a first surface 100a of the pixel circuit substrate 100, an interconnection structure 110 disposed in the pixel circuit substrate 100 and the bonding layer 300, and a rewiring layer 400 laid on a second surface 100b of the pixel circuit substrate 100, wherein in the chip combination structure 200, a signal processing chip 20 and a DRAM chip 30 are interconnected through a chip interconnection layer 230, and in addition, the signal processing chip 20, the DRAM chip 30, and a readout circuit of the pixel circuit substrate 100 are all electrically connected to the interconnection structure 110, and the interconnection structure 110 is also electrically connected to the rewiring layer 400, thereby realizing electrical interconnection among the pixel circuit substrate 100, the signal processing chip 20, and the DRAM chip 30, optimizing the structure of the package module, and facilitating buffering a digital image signal output by the readout circuit in the DRAM chip 30, and the data is transmitted to the signal processing chip 20 by the DRAM chip 30 for processing, so that when the CMOS image sensor packaging module is used for image shooting, the processing speed of the transmitted data and the digital image signals is improved, and the image quality is further improved.

The embodiment also comprises a forming method of the CMOS image sensor packaging module, which is used for manufacturing the CMOS image sensor packaging module.

The method for forming the CMOS image sensor package module of the present embodiment first includes a step of forming a chip bonding structure. Forming the die attach structure may utilize a fan out (fan out) process. First, a method of forming a chip bonding structure will be described below.

Fig. 1 is a schematic cross-sectional view illustrating a signal processing chip and a DRAM chip bonded on a temporary carrier in a method for forming a CMOS image sensor package module according to an embodiment of the present invention. Referring to fig. 1, the method for forming the chip combination structure of the present embodiment includes: providing a temporary carrier board 40, and bonding the signal processing chip 20 and the DRAM chip 30 on the temporary carrier board 40 in parallel, wherein the signal processing chip 20 has a first connection end 21 and a second connection end 22, and the DRAM chip 30 has a third connection end 31 and a fourth connection end 32.

The temporary carrier 40 may be a silicon wafer or a substrate made of glass, ceramic, or polymer material. The signal processing chip 20 and the DRAM chip 30 may be temporarily fixed on the surface (i.e., the bonding surface) of the temporary carrier board 40 by means of bonding or adhesion, for example, a dry film or an adhesive tape may be disposed on the surface of the temporary carrier board 40 to function as a fixed chip, and in another embodiment, the signal processing chip 20 and the DRAM chip 30 may be adhered on the surface of the temporary carrier board 40 by means of a hot melt adhesive to facilitate the removal of the temporary carrier board 40 by heating. For the features of the signal processing chip 20 and the DRAM chip 30, reference may be made to the description of the CMOS image sensor package module.

To facilitate interconnecting the first connection end 21 of the signal processing chip 20 and the third connection end 31 of the DRAM chip 30, as an example, the first connection end 21 and the second connection end 22 of the signal processing chip 20 and the third connection end 31 and the fourth connection end 32 of the DRAM chip 30 may all face toward or away from the bonding surface of the temporary carrier board 40 when bonded to the temporary carrier board 40. The distance between the signal processing chip 20 and the DRAM chip 30 may be set according to the pitch in the package module later.

Next, a chip molding layer 210 is formed on the temporary carrier 40, wherein the chip molding layer 210 includes the signal processing chip 20, the DRAM chip 30, and an encapsulating material covering a bonding surface of the signal processing chip 20, the DRAM chip 30, and the temporary carrier 40. The encapsulating material may include one or more of thermosetting resins such as phenol resin, urea resin, formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, polyimide, etc., and may also include various additives.

The embodiment is described by taking the example that the first connection end 21 and the third connection end 31 both face away from the bonding surface of the temporary carrier plate 40, so that after the chip forming layer 210 is formed, the interconnection process (part of the material of the chip forming layer 210 may be removed) may be performed directly above the first connection end 21 and the third connection end 31, as shown in fig. 1. It is understood that the temporary carrier plate 40 may be removed before the interconnection process or after the interconnection process. In another embodiment, the first connection terminals 21 and the third connection terminals 31 face the joint surface of the temporary carrier plate 40, and in order to expose the first connection terminals 21 and the third connection terminals 21 to be electrically connected for interconnection, after the chip molding layer 210 is formed, the temporary carrier plate 40 needs to be removed (the joint material remained on the surfaces of the first connection terminals 21 and the third connection terminals 21 can be removed as required) and then an interconnection process needs to be performed.

Fig. 2 is a schematic cross-sectional view illustrating a dielectric layer and first and second electrical connectors formed in a method for forming a CMOS image sensor package module according to an embodiment of the present invention. Referring to fig. 2, the method for forming the chip combination structure of the present embodiment may further include: forming a dielectric layer 220 on the chip molding layer 210, wherein the dielectric layer 220 covers the first connection end 21 and the third connection end 31; and forming a first electric connector 201 and a second electric connector 202 in the dielectric layer 220, wherein the first electric connector 201 is in contact and electric connection with the first connection end 21, and the second electric connector 202 is in contact and electric connection with the third connection end 31.

The dielectric layer 220 is an insulating material such as oxide, for example, and other insulating materials applied to the interconnect process in the art may be used. In this embodiment, the first electrical connector 201 and the second electrical connector 202 are, for example, conductive plugs formed in the dielectric layer 220, and one end of each of the conductive plugs is electrically connected to a corresponding connection terminal on the chip, and the other end of each of the conductive plugs is exposed on the surface of the dielectric layer 220 so as to be interconnected on the dielectric layer 220.

Fig. 3 is a schematic cross-sectional view illustrating a chip interconnection layer formed in a method for forming a CMOS image sensor package module according to an embodiment of the invention. Referring to fig. 3, the method for forming the chip combining structure of the present embodiment may further include: forming a chip interconnection layer 230 on the dielectric layer 220, wherein the chip interconnection layer 230 is electrically connected with both the first electrical connector 201 and the second electrical connector 202, so as to obtain the chip combination structure 200 of the present embodiment, the chip combination structure 200 includes a chip molding layer 210 (in which the signal processing chip 20 and the DRAM chip 30 are embedded), a dielectric layer (in which the first electrical connector 201 and the second electrical connector 202 are embedded), and a chip interconnection layer 230, which are sequentially stacked, wherein the chip interconnection layer 230 is electrically connected with the first connection end 21 of the signal processing chip 20 and the third connection end 31 of the DRAM chip 30 through the first electrical connector 201 and the second electrical connector 202.

For bonding with the pixel circuit substrate, the above-mentioned chip combining structure 200 may be formed as a chip-scale-sized bonding unit, for example, after the chip interconnection layer 230 is formed, the structure is cut by using a chip cutting process disclosed in the art to form a chip-scale-sized bonding unit. But not limited thereto, the chip combining structure 200 may be formed in a wafer-level size, that is, a wafer-level structure is formed, so that when the chip combining structure 200 and the pixel circuit substrate are bonded, the chip combining structure 200 and the pixel circuit substrate may be opposed and bonded according to the wafer-level size, in addition, a dummy chip may be embedded in the chip combining structure 200, and when the chip combining structure 200 and the pixel circuit substrate 100 are subsequently bonded, the signal processing chip 20, the DRAM chip 30, and the dummy chip respectively correspond to appropriate positions on the pixel circuit substrate 100, and the warpage of the formed package module may be controlled. It is to be understood that the dummy chip may be bonded to the pixel circuit substrate 100 alone when the bonding is performed in a chip scale.

The method for forming the CMOS image sensor package module of the present embodiment then includes a step of bonding the chip combining structure 200 and the pixel circuit substrate 100.

Fig. 4 is a schematic cross-sectional view illustrating a chip connection structure bonded on a pixel circuit substrate in a method for forming a CMOS image sensor package module according to an embodiment of the invention. Referring to fig. 4, the method for forming the CMOS image sensor package module of the present embodiment includes: the chip combination structure 200 and the pixel circuit substrate 100 are bonded, the pixel circuit substrate 100 includes a photosensitive area i and a readout circuit area ii, a pixel array of the CMOS image sensor is disposed in the photosensitive area i, the readout circuit is disposed in the readout circuit area ii, the readout circuit has circuit interconnection terminals (in this embodiment, a first circuit interconnection terminal 101 and a second circuit interconnection terminal 102 are included), the pixel circuit substrate 100 includes a first surface 100a and a second surface 100b which are opposite to each other, and the chip combination structure 200 is located on the first surface 100a through a bonding layer 300.

As for the pixel circuit substrate 100, reference may be made to the description in the foregoing CMOS image sensor package module. In this embodiment, the incident light is set to enter the pixel unit from the second surface 100b side. The chip united structure 200 is bonded on the first surface 100a by a bonding layer 300. The first surface 100a may also have a dummy chip 10 bonded thereto. As described above, the die attach structure 200 may be a die-scale bonding unit (die) or a wafer-scale structure, so that different bonding methods may be used. Specifically, the chip combining structure 200 may be bonded to the pixel circuit substrate 100 by a bonding method or an adhering method. The bonding layer 300 is formed between the chip combining structure 200 and the pixel circuit substrate 100.

Since the signal processing chip 20 and the DRAM chip 30 in the chip combining structure 200 are already interconnected, the bonding is flexible, and after the bonding, the chip interconnection layer 230 of the chip combining structure 200 may be interposed between the bonding layer 300 and the dielectric layer 220, or may be located on a side of the chip combining structure 200 away from the bonding layer 300. In a preferred embodiment, the second interconnection terminal 22 of the signal processing chip 20 and the fourth interconnection terminal 32 of the DRAM chip 30 are bonded in a direction toward the first surface 100a so as to be electrically connected to the readout circuitry in the pixel circuit substrate 100.

After the chip combining structure 200 and the pixel circuit substrate 100 are bonded, in order to prevent the package module from being affected by external factors (such as moisture, oxygen, vibration, impact, etching, etc.), after the chip combining structure 200 and the dummy chip 10 are bonded to the pixel circuit substrate 100, an encapsulation layer 500 may be further formed to cover the chip combining structure 200 (in fig. 4, a chip-scale bonding unit) and the dummy chip 10. The encapsulation layer 500 may also cover other areas of the pixel circuit substrate 100 as needed. The encapsulation layer 500 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like, may also include a thermoplastic resin such as polycarbonate, polyethylene terephthalate, polyether sulfone, polyphenylene oxide, polyamide, polyetherimide, methacrylic resin, or cyclic polyolefin resin, may also include a thermosetting resin such as epoxy resin, phenol resin, urea resin, formaldehyde resin, polyurethane, acryl resin, vinyl ester resin, imide resin, urea resin, or melamine resin, and may also include an organic insulating material such as polystyrene, polyacrylonitrile, or the like. The encapsulation layer 500 may be formed by, for example, a chemical vapor deposition process or an injection molding process. In another embodiment, the chip combining structure 200 is a wafer level structure, which is opposite to and bonded to the pixel circuit substrate 100 according to the wafer level dimension, and may not be covered with an additional packaging material.

The method of forming the CMOS image sensor package module of the present embodiment then includes the step of forming an interconnect structure.

Fig. 5 is a schematic cross-sectional view illustrating a CMOS image sensor package module after an interconnect structure is formed according to a method of forming the CMOS image sensor package module according to an embodiment of the present invention. Referring to fig. 5, the method for forming the CMOS image sensor package module of the present embodiment includes: an interconnection structure 110 is formed, the interconnection structure 110 is disposed in the pixel circuit substrate 100 and the bonding layer 300, and the interconnection structure 110 is electrically connected to the circuit interconnection terminal of the readout single, the second connection terminal 22 of the signal processing chip 20, and the fourth connection terminal 32 of the DRAM chip 30.

The interconnect structure 110 may include one or more electrical contacts, electrical connections, and electrical connection lines formed between the pixel circuit substrate 100 and the bonding layer 300. In this embodiment, the method for forming the interconnect structure 110 may include performing a hole etching process and a hole filling process from the second surface 100b side to form a plurality of conductive plugs (filling holes with a conductive material such as a metal). Optionally, the plurality of conductive plugs include a first conductive plug 111 electrically connected to a circuit interconnection terminal of the readout circuitry, and the first conductive plug 111 is disposed in the pixel circuit substrate 100. Alternatively, the plurality of conductive plugs may include a second conductive plug 112 for electrically connecting the second connection terminal 22 of the signal processing chip 20, and/or a third conductive plug 113 for electrically connecting the fourth connection terminal 32 of the DRAM chip 30, and both the second conductive plug 112 and the third conductive plug 113 pass through the pixel circuit substrate 100 and the bonding layer 300. Also, the conductive plugs may include end portions exposed at the second surface 100b to be electrically connected to a re-wiring layer formed later. The plurality of conductive plugs may also be formed using methods disclosed in the art.

Referring to fig. 5, in the present embodiment, the plurality of conductive plugs includes a first conductive plug 111, a second conductive plug 112, and a third conductive plug 113, the first conductive plug 111 contacts a circuit interconnection terminal (e.g., the first circuit interconnection terminal 101 and the second circuit interconnection terminal 102 in fig. 4) electrically connecting the readout circuit, the second conductive plug 112 contacts the second connection terminal 22 electrically connecting the signal processing chip 20, and the third conductive plug 113 contacts the fourth connection terminal 32 electrically connecting the DRAM chip 30.

The method for forming the CMOS image sensor package module of the present embodiment further includes a step of forming a re-wiring layer.

Fig. 6 is a schematic cross-sectional view illustrating a redistribution layer formed in a method for forming a CMOS image sensor package module according to an embodiment of the invention. Referring to fig. 6, the method for forming the CMOS image sensor package module of the present embodiment includes: a redistribution layer 400 is formed on the second surface 100b of the pixel circuit substrate 100, and the redistribution layer 400 is electrically connected to the interconnection structure 110.

Specifically, the rewiring layer 400 may be formed on the planarization layer on the second surface 100a side of the pixel circuit substrate 100, and may be in contact with the plurality of conductive plugs of the interconnection structure 110, so as to be electrically connected to the interconnection structure 110. The rewiring layer 400 is formed by, for example, depositing a metal layer on the second surface 100b of the pixel circuit substrate 100 by using a Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like, and then performing a patterning process to form the rewiring layer 400. The redistribution layer 400 may also be fabricated using the disclosed method.

The re-wiring layer 400 may further include re-wirings and pads (I/opads) electrically connected to the re-wirings, and the re-wiring layer 400 may re-lay the electrical connections of the interconnection structure 110 (and thus the signal processing chip 20, the DRAM chip 30, and the pixel circuit substrate 100) according to design requirements. The pads electrically connected to the rewiring may be used for connection of the rewiring layer to external signals or devices of the package module to process or control the electrical signals transmitted by the rewiring.

Through the above steps, the method for forming the CMOS image sensor package module of the present embodiment first forms the chip combination structure 200 by using the fan-out process such as described above, wherein the chip combination structure 200 includes the chip molding layer 210 embedding the signal processing chip 20 and the DRAM chip 30, and the chip interconnection layer 230 interconnecting the first connection terminal 21 of the signal processing chip 20 and the third connection terminal 31 of the DRAM chip 30, and then bonds the chip combination structure 200 to the pixel circuit substrate 100, and further forms the interconnection structure 110 electrically connected to the circuit interconnection terminal of the readout circuit, the second connection terminal 22 of the signal processing chip, and the fourth connection terminal 32 of the DRAM chip 30 in the pixel circuit substrate 100 and the bonding layer 300, and forms the wiring layer 400 electrically connected to the interconnection structure 110 on the second surface 100b (the surface opposite to the chip combination structure 200) of the pixel circuit substrate 100, thereby realizing the integration between chips and the integration between the chip combination structure 200 and the pixel circuit substrate 100, the process is simple and the cost is low. The DRAM chip can be used as a cache element in a CMOS image sensor packaging module, and is beneficial to improving the processing speed of transmitted data and digital image signals when being used for image shooting, thereby improving the image quality. In addition, the signal processing chip 20 and the DRAM chip 30 are vertically bonded to the pixel circuit substrate 100, so that the design margin of the pixel array substrate 100 is large and the overall module size is small.

The embodiment of the invention also provides a camera device which is provided with the CMOS image sensor packaging module. The camera device of the embodiment of the invention can be a miniature camera, a digital camera, or various electronic devices with the functions of the miniature camera, such as a mobile phone, a tablet, a notebook computer, intelligent glasses, a digital helmet, a monitor and the like. The camera device of the embodiment of the invention is beneficial to realizing smaller size and better image quality due to the adoption of the CMOS image sensor packaging module of the embodiment of the invention.

The method and structure in this embodiment are described in a progressive manner, and the following method and structure focus on illustrating the differences from the previous method and structure, and the relevant points can be understood by reference.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims

1. A CMOS image sensor package module, comprising:

the CMOS image sensor comprises a pixel circuit substrate and a pixel circuit substrate, wherein the pixel circuit substrate comprises a photosensitive area and a read-out circuit area, a pixel array of the CMOS image sensor is arranged in the photosensitive area, the read-out circuit is arranged in the read-out circuit area and is provided with a circuit interconnection end, and the pixel circuit substrate comprises a first surface and a second surface which are opposite;

the bonding layer is laid on the first surface;

the chip combination structure is arranged on the first surface at intervals of the bonding layer and comprises a chip forming layer, a dielectric layer and a chip interconnection layer which are sequentially overlapped, wherein a signal processing chip and a DRAM (dynamic random access memory) chip are embedded in the chip forming layer, the signal processing chip is provided with a first connecting end and a second connecting end, the DRAM chip is provided with a third connecting end and a fourth connecting end, and the chip interconnection layer is electrically connected with the first connecting end and the third connecting end respectively through a first electric connecting piece and a second electric connecting piece which are arranged in the dielectric layer;

an interconnection structure disposed in the pixel circuit substrate and the bonding layer, the interconnection structure being electrically connected to the circuit interconnection terminal, the second connection terminal, and the fourth connection terminal; and a rewiring layer laid on the second surface, the rewiring layer being electrically connected to the interconnect structure.

2. The CMOS image sensor package module of claim 1, wherein the chip interconnect layer is interposed between the bonding layer and the chip molding layer, or the chip molding layer is interposed between the bonding layer and the chip interconnect layer.

3. The CMOS image sensor package module of claim 1, wherein the interconnect structure includes a first conductive plug disposed in the pixel circuit substrate, the first conductive plug electrically connecting the circuit interconnect and the re-routing layer.

4. The CMOS image sensor package module according to claim 3, wherein the circuit interconnection terminal includes a first circuit interconnection terminal and a second circuit interconnection terminal, and the second interconnection structure includes two of the first conductive plugs to electrically connect the first circuit interconnection terminal and the re-wiring layer and the second circuit interconnection terminal and the re-wiring layer, respectively.

5. The CMOS image sensor package module of claim 1, wherein the interconnect structure includes a second conductive plug passing through the pixel circuit substrate and the bonding layer, the second conductive plug electrically connecting the signal processing chip and the re-wiring layer.

6. The CMOS image sensor package module of claim 1, wherein the interconnect structure includes a third conductive plug through the pixel circuit substrate and the bonding layer, the third conductive plug electrically connecting the DRAM chip and the re-wiring layer.

7. The CMOS image sensor package module of claim 1, wherein the rewiring layer includes rewirings and pads electrically connected to the rewirings.

8. The CMOS image sensor package module of claim 1, further comprising: and the dummy chip is arranged on the first surface through the bonding layer.

9. The CMOS image sensor package module according to claim 8, wherein the chip association structure is disposed on the first surface in correspondence with the readout circuit region, incident light is set to enter the pixel array from the second surface side, and the dummy chip is disposed on the first surface in correspondence with the photosensitive region.

10. The CMOS image sensor package module of claim 1, wherein the CMOS image sensor is a backside illuminated CMOS image sensor.

11. The CMOS image sensor package module of claim 1, wherein the bonding layer comprises an adhesive material.

12. The CMOS image sensor package module of claim 1, wherein the first electrical connections and the second electrical connections are conductive plugs.

13. An image pickup apparatus comprising the CMOS image sensor package module according to any one of claims 1 to 12.

14. A method for forming a CMOS image sensor package module, comprising:

forming a chip combined structure, wherein the chip combined structure comprises a chip forming layer, a dielectric layer and a chip interconnection layer which are sequentially overlapped, a signal processing chip and a DRAM chip are embedded in the chip forming layer, the signal processing chip is provided with a first connecting end and a second connecting end, the DRAM chip is provided with a third connecting end and a fourth connecting end, and the chip interconnection layer is respectively and electrically connected with the first connecting end and the third connecting end through a first electric connecting piece and a second electric connecting piece which are arranged in the dielectric layer;

bonding the chip combination structure and a pixel circuit substrate, wherein the pixel circuit substrate comprises a photosensitive area and a reading circuit area, a pixel array of the CMOS image sensor is arranged in the photosensitive area, the reading circuit is arranged in the reading circuit area, the reading circuit is provided with a circuit interconnection end, the pixel circuit substrate comprises a first surface and a second surface which are opposite, and the chip combination structure is arranged on the first surface in a spaced bonding mode;

forming an interconnection structure disposed in the pixel circuit substrate and the bonding layer, the interconnection structure being electrically connected to the circuit interconnection terminal, the second connection terminal, and the fourth connection terminal; and

and forming a rewiring layer on the second surface, wherein the rewiring layer is electrically connected with the interconnection structure.

15. The method of forming a CMOS image sensor package module of claim 14, wherein the method of forming the die attach structure comprises:

providing a temporary carrier plate, and parallelly jointing the signal processing chip and the DRAM chip on the temporary carrier plate, wherein the first connecting end and the third connecting end face the jointing surface of the temporary carrier plate;

forming a chip molding layer including the signal processing chip, the DRAM chip, and an encapsulation material covering the signal processing chip, the DRAM chip, and the temporary carrier;

removing the temporary carrier plate to expose the first connection end and the third connection end;

forming a dielectric layer on the chip forming layer, wherein the dielectric layer covers the first connecting end and the third connecting end;

forming a first electrical connector and a second electrical connector in the dielectric layer, the first electrical connector being electrically connected with the first connection end, the second electrical connector being electrically connected with the third connection end; and

and forming a chip interconnection layer on the dielectric layer, wherein the chip interconnection layer is electrically connected with the first electric connecting piece and the second electric connecting piece, so that the chip combined structure is obtained.

16. The method of forming a CMOS image sensor package module of claim 14, wherein the method of forming the die attach structure comprises:

providing a temporary carrier plate, and parallelly jointing the signal processing chip and the DRAM chip on the temporary carrier plate, wherein the first connecting end and the third connecting end face to one side far away from the jointing surface of the temporary carrier plate;

17. The method of forming a CMOS image sensor package module of claim 16, wherein the temporary carrier plate is removed before or after the step of bonding the die attach structure to the pixel circuit substrate.

18. The method of forming a CMOS image sensor package module of claim 14, wherein the die attach structure is a die-scale bonding unit.

19. The method of claim 18, wherein in the step of bonding the die attach structure to the pixel circuit substrate, a dummy die is further bonded to the first surface.

20. The method of claim 14, wherein the die attach structure and the pixel circuit substrate are wafer level structures, and wherein the die attach structure and the pixel circuit substrate are bonded together in a wafer level dimension.

21. The method of claim 20, wherein the die attach structure further comprises a dummy die embedded in the die molding layer.

22. The method of forming a CMOS image sensor package module of claim 14, wherein the method of forming the interconnect structure includes performing a hole etching process and a hole filling process from the second surface side to form a plurality of conductive plugs.

23. The method of forming a CMOS image sensor package module of claim 22, wherein the plurality of conductive plugs includes a first conductive plug formed in the pixel circuit substrate and electrically connecting the circuit interconnect and the re-wiring layer.

24. The method of forming a CMOS image sensor package module of claim 22, wherein the plurality of conductive plugs includes a second conductive plug that passes through the pixel circuit substrate and the bonding layer and electrically connects the second connection terminal and the re-wiring layer.

25. The method of forming a CMOS image sensor package module of claim 22, wherein the plurality of conductive plugs includes a third conductive plug that passes through the pixel circuit substrate and the bonding layer and electrically connects the fourth connection terminal and the re-wiring layer.