WO2020173059A1

WO2020173059A1 - Cmos image sensor package module and forming method thereof and imaging device thereof

Info

Publication number: WO2020173059A1
Application number: PCT/CN2019/102255
Authority: WO
Inventors: 向阳辉
Original assignee: 中芯集成电路（宁波）有限公司
Priority date: 2019-02-27
Filing date: 2019-08-23
Publication date: 2020-09-03
Also published as: CN111627939A; CN111627939B

Abstract

Provided are a complementary metal-oxide semiconductor (CMOS) image sensor package module and forming method thereof, and an imaging device comprising the CMOS image sensor package module. The CMOS image sensor package module comprises a pixel circuit substrate (100) and a chip joint structure (200) engaged therewith; a chip forming layer (210) in the chip joint structure (200) is embedded with a signal processing chip (20) and a dynamic random access memory (DRAM) chip (30); a chip interconnection layer (230) is electrically connected to the signal processing chip (20) and the DRAM chip (30). The package module also comprises an interconnection structure (110) and re-wiring layer (400) electrically connected to circuit interconnection terminals (101, 102), signal processing chip (20), and DRAM chip (30) of a read-out circuit in a pixel circuit substrate (100); the re-wiring layer (400) is electrically connected to an interconnection structure (110); the package module facilitates the buffering, in the DRAM chip (30), of a digital image signal outputted by the read-out circuit, and the signal is then transmitted from the DRAM chip (30) to the signal processing chip (20) for processing, which is advantageous to increasing the processing speed of transmitted data and digital image signals.

Description

CMOS image sensor package module and its forming method and camera device

Technical field

The present invention relates to the field of image sensors, in particular to a CMOS image sensor package module and its forming method, and a camera device.

Background technique

Due to the need to shoot sceneries, digital cameras are also currently installed on devices such as laptops, tablets, smart phones, and smart toys. Commonly used digital cameras project the generated optical image onto the surface of the photosensitive element through the camera lens. The light is decomposed into different colors by the filter on the surface of the photosensitive element, and each color light is sensed by the pixel unit corresponding to each filter and produces a difference. The intensity of the analog signal is collected by the circuit of the photosensitive element. The analog signal is converted into a digital signal by a digital-to-analog converter, and then the image signal processor (ISP, image signal processor) processes these digital signals. It is sent to the mobile phone processor for processing, and then transferred to the memory card for storage and becomes a viewable image on the screen.

Currently, the commonly used photosensitive element is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor, complementary metal-oxide-semiconductor) image sensor. Compared with CCD image sensors, CMOS image sensors can achieve more flexible image capture, higher sensitivity, wider dynamic range, higher resolution, lower power consumption, and better system integration. In addition, the light is incident from the back of the CMOS image sensor and is directed to the photosensitive element without passing through the interconnection layer on the photosensitive element, which reduces the light loss. In unit time, a single pixel unit can obtain more light energy, which is more effective for painting. The quality has improved significantly.

However, as the requirements for the size and imaging quality of the CMOS image sensor increase, it is still necessary to further optimize the structure of the CMOS image sensor package module.

Summary of the invention

In view of the above-mentioned problems, the present invention provides a CMOS image sensor package module and a forming method thereof to optimize the structure of the CMOS image sensor package module and facilitate the improvement of imaging quality when the CMOS image sensor package module is used for shooting.

According to an aspect of the present invention, there is provided a CMOS image sensor package module, including:

The pixel circuit substrate includes a photosensitive area and a readout circuit area, the pixel array of the CMOS image sensor is arranged in the photosensitive area, the readout circuit is arranged in the readout circuit area, and the readout circuit has a circuit interconnection terminal, The pixel circuit substrate includes a first surface and a second surface opposite to each other; a bonding layer is laid on the first surface; a chip joint structure, which is arranged on the first surface at intervals from the bonding layer, the chip joint structure It includes a chip molding layer, a dielectric layer, and a chip interconnection layer that are sequentially stacked, wherein the chip molding layer is embedded with a signal processing chip and a DRAM chip, and the signal processing chip has a first connection end and a second connection end, so The DRAM chip has a third connection end and a fourth connection end, and the chip interconnection layer is respectively connected to the first connection end and the second connection end through a first electrical connection piece and a second electrical connection piece arranged in the dielectric layer. The third connection terminal is electrically connected; an interconnection structure is disposed in the pixel circuit substrate and the bonding layer, the interconnection structure is connected to the circuit interconnection terminal, the second connection terminal and the fourth The connection ends are electrically connected; and a rewiring layer is laid on the second surface, and the rewiring layer is electrically connected to the interconnection structure.

Optionally, the chip interconnection layer is between the bonding layer and the chip molding layer, or the chip molding layer is between the bonding layer and the chip interconnection layer.

Optionally, the interconnection structure includes a first conductive plug disposed in the pixel circuit substrate, and the first conductive plug is electrically connected to the circuit interconnection end and the rewiring layer.

Optionally, the circuit interconnection terminal includes a first circuit interconnection terminal and a second circuit interconnection terminal, and the second interconnection structure includes two of the first conductive plugs to electrically connect the first conductive plugs respectively. A circuit interconnection terminal and the rewiring layer, and the second circuit interconnection terminal and the rewiring layer.

Optionally, the interconnect structure includes a second conductive plug passing through the pixel circuit substrate and the bonding layer, and the second conductive plug electrically connects the signal processing chip and the rewiring layer.

Optionally, the interconnect structure includes a third conductive plug passing through the pixel circuit substrate and the bonding layer, and the third conductive plug electrically connects the DRAM chip and the rewiring layer.

Optionally, the rewiring layer includes rewiring and bonding pads electrically connected to the rewiring.

Optionally, the CMOS image sensor packaging module further includes a dummy chip, which is arranged on the first surface with the bonding layer interposed therebetween.

Optionally, the chip joint structure corresponds to that the readout circuit area is arranged on the first surface, the incident light is set to enter the pixel array from the second surface side, and the dummy chip Corresponding to the photosensitive area is provided on the first surface.

Optionally, the CMOS image sensor is a back-illuminated CMOS image sensor.

Optionally, the bonding layer includes an adhesive material.

Optionally, the first electrical connector and the second electrical connector are conductive plugs.

According to another aspect of the present invention, there is provided an imaging device including the above-mentioned CMOS image sensor package module.

According to another aspect of the present invention, there is provided a method for forming a CMOS image sensor package module, including the following steps:

A chip joint structure is formed, and the chip joint structure includes a chip molding layer, a dielectric layer, and a chip interconnection layer that are sequentially stacked, wherein the chip molding layer is embedded with a signal processing chip and a DRAM chip, and the signal processing chip has a first A connection end and a second connection end, the DRAM chip has a third connection end and a fourth connection end, the chip interconnection layer passes through a first electrical connection piece and a second electrical connection piece arranged in the dielectric layer Are respectively electrically connected to the first connection terminal and the third connection terminal; to join the chip joint structure and the pixel circuit substrate, the pixel circuit substrate includes a photosensitive area and a readout circuit area, the pixel array of the CMOS image sensor is arranged In the photosensitive area, the readout circuit is arranged in the readout circuit area, the readout circuit has circuit interconnection ends, the pixel circuit substrate includes a first surface and a second surface opposed to each other, and the chip joint structure The spacer bonding layer is located on the first surface; an interconnection structure is formed, the interconnection structure is disposed in the pixel circuit substrate and the bonding layer, the interconnection structure is connected to the circuit interconnection end, the second Both the connection terminal and the fourth connection terminal are electrically connected; and a rewiring layer is formed on the second surface, and the rewiring layer is electrically connected to the interconnect structure.

Optionally, the method of forming the chip joint structure includes:

Provide a temporary carrier board, join the signal processing chip and the DRAM chip on the temporary carrier board in parallel, and both the first connection end and the third connection end face the bonding surface of the temporary carrier board; A chip molding layer is formed, the chip molding layer includes the signal processing chip, the DRAM chip, and packaging materials covering the signal processing chip, the DRAM chip, and the temporary carrier; removing the temporary carrier , To expose the first connection end and the third connection end; forming a dielectric layer on the chip molding layer, the dielectric layer covering the first connection end and the third connection end; A first electrical connection piece and a second electrical connection piece are formed in the dielectric layer, the first electrical connection piece is electrically connected to the first connection end, and the second electrical connection piece is electrically connected to the third connection end And forming a chip interconnection layer on the dielectric layer, and the chip interconnection layer is electrically connected to the first electrical connection member and the second electrical connection member, thereby obtaining the chip joint structure.

Optionally, the method of forming the chip joint structure includes:

A temporary carrier board is provided, and the signal processing chip and the DRAM chip are joined in parallel on the temporary carrier board, and the first connection end and the third connection end are both facing away from the joint surface of the temporary carrier board Forming a chip molding layer, the chip molding layer including the signal processing chip, the DRAM chip and packaging materials covering the signal processing chip and the DRAM chip and the temporary carrier; in the A dielectric layer is formed on the chip molding layer, the dielectric layer covers the first connection end and the third connection end; a first electrical connection piece and a second electrical connection piece are formed in the dielectric layer, the first The electrical connection member is electrically connected to the first connection terminal, the second electrical connection member is electrically connected to the third connection terminal; and a chip interconnection layer is formed on the dielectric layer, and the chip interconnection layer is Both the first electrical connection member and the second electrical connection member are electrically connected, thereby obtaining the chip joint structure.

Optionally, before or after the step of joining the chip joint structure and the pixel circuit substrate, the temporary carrier is removed.

Optionally, the chip joint structure is a chip-level size bonding unit.

Optionally, in the step of bonding the chip joint structure and the pixel circuit substrate, a dummy chip is also bonded on the first surface.

Optionally, the chip joint structure and the pixel circuit substrate are both wafer-level structures. When the chip joint structure and the pixel circuit substrate are joined, the chip joint structure and the pixel circuit substrate are arranged in accordance with the wafer The level size is opposite and joined.

Optionally, the chip joint structure further includes a dummy chip, and the dummy chip is embedded in the chip molding layer.

Optionally, the method of forming the interconnect structure includes performing a hole etching process and a hole filling process from one side of the second surface to form a plurality of conductive plugs.

Optionally, the plurality of conductive plugs includes a first conductive plug formed in the pixel circuit substrate and electrically connected to the circuit interconnection terminal and the rewiring layer.

Optionally, the plurality of conductive plugs includes a second conductive plug, the second conductive plug passes through the pixel circuit substrate and the bonding layer, and electrically connects the second connection terminal and the Rewiring layer.

Optionally, the plurality of conductive plugs includes a third conductive plug, the third conductive plug passes through the pixel circuit substrate and the bonding layer, and electrically connects the fourth connection terminal and the Rewiring layer.

The CMOS image sensor package module provided by the present invention includes a pixel circuit substrate and a chip joint structure bonded thereto. The chip joint structure includes a chip molding layer, a dielectric layer, and a chip interconnection layer that are sequentially stacked, wherein the chip molding layer A signal processing chip and a DRAM chip are embedded therein, the signal processing chip has a first connection end and a second connection end, the DRAM chip has a third connection end and a fourth connection end, and the chip interconnection layer is arranged in The first electrical connection member and the second electrical connection member in the dielectric layer are electrically connected to the first connection terminal and the third connection terminal, respectively. In addition, the CMOS image sensor package module further includes The pixel circuit substrate and the interconnection structure in the bonding layer and the rewiring layer provided on the other side of the pixel circuit substrate, the circuit interconnection end of the interconnection structure and the readout circuit, the second connection end of the signal processing chip, and The fourth connection ends of the DRAM chip are all electrically connected, and the wiring layer is electrically connected to the interconnection structure, thereby realizing the electrical interconnection between the pixel circuit substrate, the signal processing chip and the DRAM chip, and optimizing the packaging module Structure, and it is convenient to buffer the digital image signal output by the readout circuit in the DRAM chip, and then transmit it from the DRAM chip to the signal processing chip for processing. When the CMOS image sensor package module is used for image shooting, it is beneficial to improve the transmission The processing speed of the data and digital image signal, thereby improving the image quality.

The camera device provided by the present invention includes the above-mentioned CMOS image sensor package module, and thus has the same or similar advantages as the above-mentioned CMOS image sensor package module.

The method for forming a CMOS image sensor package module provided by the present invention can form the above-mentioned CMOS image sensor package module. Among them, a chip joint structure is first formed, which includes a chip molding layer embedded with a signal processing chip and a DRAM chip, and a chip interconnection layer that interconnects the first connection end of the signal processing chip and the third connection end of the DRAM chip, and then The chip assembly structure is joined to the pixel circuit substrate, and then the pixel circuit substrate and the joining layer are formed in the pixel circuit substrate and the joining layer to be electrically connected to the circuit interconnection end of the readout circuit, the second connection end of the signal processing chip and the fourth connection end of the DRAM chip. Connecting structure, and forming a rewiring layer on the second surface of the pixel circuit substrate (the side opposite to the chip joint structure), and the rewiring layer is electrically connected to the interconnection structure, thereby realizing the integration between the chips and the chip joint structure and the pixel The integration of the circuit substrate has simple process and low cost. The DRAM chip can be used as a buffer element in the CMOS image sensor package module. When used for image shooting, it is beneficial to increase the processing speed of the transmitted data and digital image signals, thereby improving the image quality.

Description of the drawings

FIG. 1 is a schematic cross-sectional view of a signal processing chip and a DRAM chip after bonding a signal processing chip and a DRAM chip on a temporary carrier in a method for forming a CMOS image sensor package module according to an embodiment of the present invention.

2 is a schematic cross-sectional view after forming a dielectric layer, a first electrical connection member and a second electrical connection member in a method for forming a CMOS image sensor package module according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view after forming a chip interconnection layer in the method for forming a CMOS image sensor package module according to an embodiment of the present invention.

4 is a schematic cross-sectional view of a pixel circuit substrate after bonding a chip assembly structure in a method for forming a CMOS image sensor package module according to an embodiment of the present invention.

5 is a schematic cross-sectional view after forming an interconnection structure in the method for forming a CMOS image sensor package module according to an embodiment of the present invention.

6 is a schematic cross-sectional view after forming a rewiring layer in the method for forming a CMOS image sensor package module according to an embodiment of the present invention.

Description of reference signs:

100-pixel circuit substrate; 100a-first surface; 100b-second surface; 101-first circuit interconnection terminal; 102-second circuit interconnection terminal; 10-pseudo chip; 110-interconnect structure; 111-th A conductive plug; 112-second conductive plug; 113-third conductive plug;

200-chip united structure; 210-chip molding layer; 220-dielectric layer; 230-chip interconnection layer; 201-first electrical connector; 202-second electrical connector;

20-signal processing chip; 21-first connection terminal; 22-second connection terminal; 30-DRAM chip; 31-third connection terminal; 32-fourth connection terminal; 300-bonding layer; 400-rewiring layer; 40-temporary carrier board; 500-encapsulation layer.

detailed description

The current CMOS image signal processor is often integrated on the pixel circuit substrate with the photosensitive element through SOC (system on chip) technology, or through the wafer-level bonding method (usually using metal and oxide hybrid bonding) and the photosensitive element Pixel circuit substrates are bonded together, the process is difficult, and the cost is high, and the wafer-level bonding method is very difficult to process defective chips on the signal processing wafer, and it will also increase the cost. In addition, when the packaged module of CMOS image sensor is applied to digital camera, the digital signal obtained through the pixel circuit (or readout circuit) on the pixel circuit substrate is directly output to the image signal processor for processing and then stored in the storage through the mobile phone processor, for example. The data processing speed (such as frame rate) of the card, photosensitive element, and pixel circuit is limited by the processing speed of the image signal processor and the processing speed of the mobile phone processor, which easily affects the shooting quality. As the requirements for the size and imaging quality of the CMOS image sensor packaging module increase, the packaging structure and packaging method of the CMOS image sensor still need to be improved.

Based on the above research, the present invention provides a CMOS image sensor package module in which a chip joint structure including a signal processing chip and a DRAM chip is bonded on the first surface of a pixel circuit substrate, including a chip embedded with a signal processing chip and a DRAM chip Molding layer, dielectric layer, and chip interconnection layer interconnecting the first connection terminal of the signal processing chip and the third connection terminal of the DRAM chip, the interconnection structure and the circuit of the readout circuit arranged in the pixel circuit substrate and the bonding layer The interconnection terminal is electrically connected to the second connection terminal of the signal processing chip and the fourth connection terminal of the DRAM chip, and the rewiring layer is arranged on the surface of the pixel circuit substrate opposite to the chip joint structure, thereby realizing the pixel circuit substrate, The electrical interconnection between the signal processing chip and the DRAM chip optimizes the structure of the package module, and it is convenient to cache the digital image signal output by the readout circuit in the DRAM chip, and then transmit it from the DRAM chip to the signal processing chip for processing When the CMOS image sensor package module is used for image shooting, it is beneficial to increase the processing speed of the transmitted data and digital image signals, thereby improving the image quality.

The CMOS image sensor package module, its forming method, and the imaging device of the present invention will be described in detail below with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the following embodiments are only exemplary specific implementations for applying the present invention, and do not constitute a limitation on the protection scope of the present invention.

It should be noted that the drawings are in a very simplified form and all use imprecise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. Unless otherwise specified, corresponding numbers and signs in different drawings generally refer to corresponding components. In addition, the terms “first”, “second”, etc. below are used to distinguish between similar elements, and are not necessarily used to describe a specific order or time sequence. It is to be understood that, under appropriate circumstances, these terms so used can be replaced, for example, to enable the embodiments of the present invention described herein to be operated in other sequences than described or illustrated herein. Similarly, if the method described herein includes a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the described steps may be omitted and/or some not described herein The other steps can be added to the method.

This embodiment first introduces a CMOS image sensor packaging module. 6, the CMOS image sensor package module of this embodiment includes a pixel circuit substrate 100, and the pixel circuit substrate 100 is arranged with a photosensitive area I and a readout circuit area II (FIG. 5 shows the photosensitive area I and the readout circuit area The position of the photosensitive area I and the readout circuit area II may not be limited to the area shown in the figure), the pixel array of the CMOS image sensor is arranged in the photosensitive area I, where the pixel array of the CMOS image sensor refers to The CMOS image sensor consists of an array of pixel units including photodiodes, the readout circuit is arranged in the readout circuit area II, and the photodiodes and readout circuits are formed in the pixel circuit substrate 100 in the corresponding area by semiconductor technology. The readout circuit has a circuit interconnection terminal for interconnection. For the convenience of description, the pixel circuit substrate 100 of this embodiment includes a first surface 100a and a second surface 100b opposite to each other.

The pixel circuit substrate 100 may specifically be a substrate (such as a wafer) for manufacturing a CMOS image sensor on a substrate. The substrate is, for example, a silicon substrate or a silicon-on-insulator (SOI) substrate. The material of the substrate may also include Germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium or other III and V group compounds. Due to the known advantages, the CMOS image sensor in this embodiment is preferably a back-illuminated CMOS image sensor. The back-illuminated CMOS image sensor is on the back side of the substrate (that is, the opposite side when the photodiode is made on the substrate), which is usually thinned and provided with a planarization layer for planarization to obtain light of different colors The color filter layer (not shown in the figure) and a lens layer (not shown in the figure) used to increase the amount of light incident on the front side of the substrate (that is, the side where the photodiode is made), the pixel circuit substrate includes A photosensitive layer provided with numerous photodiodes, millions of pixel cells or pixel units can be arranged in the photosensitive layer, each pixel unit includes, for example, a photodiode and a plurality of MOS transistors used as driving circuits When working, light enters from the lens layer and enters the pixel unit in the photosensitive layer through the color filter layer and the medium layer to form a photocurrent. In the pixel circuit substrate, a number of different areas can be set according to different functions. Usually, the pixel units distributed in an array are arranged in the photosensitive area I, and peripheral circuits are arranged around the photosensitive area I, so that the photosensitive area I and the readout circuit area II also corresponds to different areas on the surface of the pixel circuit substrate 100. The interconnection layer formed on the photosensitive layer may include a multilayer interconnection metal layer stacked together and a plug layer connecting two adjacent interconnection metal layers. The interconnection layer is used to electrically connect the photodiode, the driving circuit, and Peripheral circuit to process the photocurrent signal of the photodiode. Peripheral circuits may specifically include analog signal processing circuits, analog-to-digital conversion circuits, digital logic circuits, and readout circuits, etc. The readout circuits are arranged in readout circuit area II, and processed on the pixel circuit substrate 100 in readout circuit area II. The completed digital image signal is output or used to transmit other signals, and the output digital image signal enters an image signal processing circuit (Image Signal Processor, ISP) or an image signal processing chip for further processing. The specific structure of the pixel array substrate can also be implemented with reference to the disclosed technology. In another embodiment, the CMOS image sensor may also be a front-illuminated CMOS image sensor, or a stacked CMOS image sensor.

In this embodiment, for example, the side surface of the pixel circuit substrate 100 where the interconnection layer is formed is used as the first surface 100a, and the side surface where light is incident is used as the second surface 100b, which corresponds to the readout circuit area II. The pixel circuit substrate 100 may include a planarization layer, a circuit layer, and an interconnection layer (may also include a lens layer and a color filter layer, not shown in the figure), a planarization layer, a circuit layer, and an interconnection layer in the direction from the second surface 100b to the first surface 100a. It can be used to planarize the surface of the substrate and serve as an electrical isolation layer. The circuit layer includes the above-mentioned readout circuit. The circuit layer can be the same process layer as the photosensitive layer of the photosensitive area I. The interconnection layer is superimposed on the circuit layer and the readout The circuit interconnection terminal of the circuit, the circuit interconnection terminal may specifically include a plurality of connection terminals for different connection purposes, for example, including the first circuit interconnection terminal 101 and the second circuit interconnection terminal 102, the first circuit The interconnection terminal 101 and the second circuit interconnection terminal 102 can transmit image digital signals or other signals by being connected to external chips or circuits.

Referring to FIG. 5, in the CMOS image sensor package module of this embodiment, the bonding layer 300 is laid on the first surface 100 a of the pixel circuit substrate 100. The material of the bonding layer 300 may include oxide or other suitable materials. For example, it may be a bonding material, that is, a signal processing chip and a DRAM chip are bonded to the first surface 100a of the pixel circuit substrate 100 by means of fusion bonding or vacuum bonding. The bonding layer 300 may also include an adhesive material, such as die attach film (DAF) or dry film (dry film), that is, the signal processing chip and the DRAM chip are bonded to the first pixel circuit substrate 100 by bonding. Surface 100a. The material of the bonding layer 300 in this embodiment is, for example, a dry film.

The chip assembly structure 200 is bonded to the pixel circuit substrate 100. Here, in this embodiment, it is bonded to the first surface 100a as an example for description. Correspondingly, a rewiring layer may be provided on the second surface 100b. However, it should be understood that, in another embodiment, the chip joint structure may also be bonded to the second surface 100b, and a rewiring layer is provided on the first surface 100a.

5, the above-mentioned chip joint structure 200 is arranged on the first surface 100a of the pixel circuit substrate 100 with the bonding layer 300 spaced apart. The chip joint structure 200 includes a chip molding layer 210, a dielectric layer 220, and a chip interconnection that are sequentially stacked. Layer 230, wherein a signal processing chip 20 and a DRAM chip 30 are embedded in the chip molding layer 210, the signal processing chip 20 has a first connection terminal 21 and a second connection terminal 22, and the DRAM chip 30 has a third Connecting end 31 and fourth connecting end 32, the chip interconnection layer 230 is respectively connected to the first connecting end 21 and the first connecting end 21 and the fourth connecting end 32 through the first electrical connector 201 and the second electrical connector 202 disposed in the dielectric layer 220 The third connecting end 31 is electrically connected.

The chip joint structure 200 can be flexibly joined to the pixel circuit substrate 100 in a suitable orientation as required. For example, in one embodiment, the chip interconnection layer 230 can be joined toward the first surface 100a of the pixel circuit substrate 100 as shown in FIG. At this time, the chip interconnection layer 230 is interposed between the bonding layer 300 and the chip molding layer 210. In another embodiment, the chip interconnection layer 230 may also be formed in a direction away from the first surface 100a of the pixel circuit substrate 100. Bonding, at this time, the chip molding layer 210 is interposed between the bonding layer 300 and the chip interconnection layer 230.

Specifically, the chip molding layer 210 may be embedded in the signal processing chip 20 and the DRAM chip 30 using packaging materials such as molding materials, such as phenol resin, urea resin, formaldehyde resin, epoxy resin, unsaturated resin, and polyurethane. , Polyimide and other thermosetting resins. The dielectric layer 220 may be an insulating material such as oxide, nitride, oxynitride, etc., to provide electrical connections therein. The first electrical connector 201 and the second electrical connector 202 respectively act as electrical connections between the signal processing chip 20 and the chip interconnection layer 230, and between the DRAM chip 30 and the chip interconnection layer 230. In this embodiment The first electrical connector 201 and the second electrical connector 202 are, for example, conductive plugs.

The above-mentioned chip joint structure 200 is preferably formed by a fan-out process, which provides a more economical multi-chip integration solution, which helps to achieve high-density wiring and smaller and thinner packages. In this embodiment, the chip joint structure 200 encapsulates the signal processing chip 20 and the DRAM chip 30 into an integrated structure first, and the process is more convenient and the cost is lower when joining with the pixel circuit substrate. In a preferred solution, the chip joint structure 200 may be a diced chip-level size bonding unit, so that it may be bonded to an appropriate area of the pixel circuit substrate 100 in a die-level manner. The chip joint structure 200 may also be The wafer-level structure can be bonded to the pixel circuit substrate 100 in the form of a wafer level. If it is a chip-level bonding unit, the chip joint structure 200 can be arranged in the readout circuit area II of the pixel circuit substrate 100 (for example, it can be arranged on the side or the other side where light is incident) to avoid the influence on the photosensitive area I . But it is not limited to this. Under the premise of not affecting the light incident on the pixel array of the photosensitive area, the chip joint structure 200 may also be bonded to other areas on the first surface 100a.

The aforementioned signal processing chip 20 may be an image signal processor (ISP) or a digital signal processor (DSP) or the like. Taking the image signal processor as an example, it can process the output data of the pixel circuit substrate 100, such as automatic exposure control (AEC), automatic gain control (AGC), automatic white balance (AWB), color correction, lens correction (Lens Shading) ), Gamma correction, bad pixel removal, and Auto Black Level processing. In addition, the above-mentioned DRAM chip 30 refers to a dynamic random access memory chip. DRAM (Dynamic Random Access Memory) is a common system memory device. DRAM uses capacitors to store data and refreshes it at intervals. If the unit is not refreshed, the stored information will be lost, which can be used as a system cache. In this embodiment, the DRAM chip 30 is arranged in the chip joint structure 200. One of the purposes is to use the CMOS image sensor package module of this embodiment in an image capturing device through its interconnection with the signal processing chip 20 and the pixel circuit substrate 100. (Such as a mobile phone camera), the DRAM chip 30 can be used to store the captured high-speed image information, and output at the optimal rate of the input interface according to the system design.

The signal processing chip 20 and the DRAM chip 30 may be independently designed and manufactured chips (as opposed to the signal processing circuit integrated on the pixel circuit substrate), and specifically may be bare chips to be packaged (different from uncut chips on the wafer) Compared with the signal processing circuit integrated on the pixel circuit substrate, the independent signal processing chip has better computing power and imaging quality. For example, when it is used in camera equipment such as mobile phones, the independent signal processing chip can be purchased from the mobile phone Provider customization helps to achieve a better fit with other components of the camera, and the vertical bonding on the pixel circuit substrate 100 facilitates the reduction of the lateral size of the pixel circuit substrate 100, thereby reducing the overall size of the package module. It can be understood that this embodiment focuses on the CMOS image sensor package module including the pixel circuit substrate 100 and the chip joint structure 200, but it does not mean that the CMOS image sensor package module of this embodiment only includes the above-mentioned components. Other chips (such as analog signal processing chips, analog-to-digital conversion chips, logic chips, etc.) can also be provided/joined, or other devices (such as power devices, bipolar devices, resistors, capacitors, etc.) can be provided. Well-known devices and connection relationships can also be included.

6, the CMOS image sensor package module of this embodiment further includes an interconnection structure 110, which is disposed in the pixel circuit substrate 100 and the bonding layer 300 to connect the readout circuit of the pixel circuit substrate 100 and the signal processing chip 20 and DRAM chip 30 are interconnected. Specifically, the interconnection structure 110 and the circuit interconnection end of the readout circuit (this embodiment includes the first circuit interconnection end 101 and the second circuit interconnection end 102), the second connection end 22 of the signal processing chip 20, and the DRAM The fourth connection ends 32 of the chip 30 are electrically connected. Since the DRAM chip 30 and the signal processing chip 20 in the chip union structure 200 have been interconnected through the chip interconnection layer 230, the CMOS image sensor package module of this embodiment can realize the DRAM chip 30 through the chip union structure 200 and the interconnect structure 110. The interconnection with any two of the signal processing chip 200 and the pixel circuit substrate 100 optimizes the packaging structure. Through the design of the transmission signal, when the CMOS image sensor package module is used for image shooting, for example, it is convenient to buffer the digital image signal output by the readout circuit in the DRAM chip 30, and then transmit it from the DRAM chip 30 to the signal processing chip 20. Processing is beneficial to increase the processing speed of the transmitted data and digital image signals, thereby improving image quality.

The ends (or electrical contacts) of the interconnect structure 110 may extend to the second surface 100b of the pixel circuit substrate 100 to rewire the connected signal ends. 6, the CMOS image sensor package module of this embodiment may further include a rewiring layer 400 (or rewiring layer, RDL), which is laid on the second surface 100b, and the rewiring layer 400 and the interconnect structure 110 Electric connection. The rewiring layer 400 may include rewiring and a bonding pad (I/O pad) electrically connected to the rewiring. In order to avoid the influence of incident light on the photosensitive region I, the rewiring layer 500 is preferably laid on the second surface 100b corresponding to the peripheral area of the pixel circuit substrate 100.

The above-mentioned interconnect structure 110 may include one or more electrical contacts, electrical connections, and electrical connection lines formed between the pixel circuit substrate 100 and the bonding layer 300. Specifically, in an embodiment of the present invention, the interconnection structure 110 may include a first conductive plug 111 disposed in the pixel circuit substrate 100, and one end of the first conductive plug 111 is in contact with and electrically connected to the readout circuit. The circuit interconnection end (such as connecting the first circuit interconnection end 101 or the second circuit interconnection end 102 in this embodiment), the other end faces the second surface 100 b and is electrically connected to the rewiring layer 400. In an embodiment of the present invention, the interconnect structure 110 includes a second conductive plug 112, one end of the second conductive plug 112 is in contact with the second connection end 22 of the electrical connection signal processing chip 20, and the other end faces the second surface 100b is also electrically connected to the rewiring layer 400. In an embodiment of the present invention, the interconnect structure 110 further includes a third conductive plug 113, one end of the third conductive plug 113 is in contact with the fourth connection end 32 electrically connected to the DRAM chip 30, and the other end faces the second surface 100b And it is electrically connected to the rewiring layer 400. 6, in this embodiment, the interconnection structure 110 includes the first conductive plug 111, the second conductive plug 112, and the third conductive plug 113 described above. In addition, in order to correspond to different circuit interconnection terminals of the readout circuit, there may be more than one first conductive plug 111. In this embodiment, the interconnection structure 110 includes two first conductive plugs 111 to electrically connect the first circuit interconnection terminal 101 and the second circuit interconnection terminal 102 to the rewiring layer. 400.

It should be noted that the interconnection structure 110 and the rewiring layer 400 in the drawings are only examples. For example, in some embodiments, the rewiring layer 400 may also be connected to the conductive plugs (or electrical connections) of the interconnection structure 110. Connect separately. Each of the interconnection structure 110 and the rewiring layer 400 and the electrical connection between the two can be designed according to specific circuits to achieve preset functions, and are not limited as shown in the figure.

Generally, in the first surface 100a of the pixel circuit substrate 100, the area corresponding to the photosensitive area I is relatively large, and the area corresponding to the peripheral circuit is relatively small. Therefore, in order to optimize the packaging effect, the CMOS image sensor package module may include a dummy chip (dummy chip) 10, to control the warpage of the packaged module. The dummy chip 10 is, for example, a silicon chip. According to the specific conditions of the pixel circuit substrate 100 and the size of the dummy chip, for example, one or more dummy chips can be bonded to the pixel array. In area I (the side opposite to the light incident surface), the dummy chip 10 may be embedded in the chip combination structure 200 and bonded to the pixel circuit substrate 100, or may be bonded to the pixel circuit substrate 100 separately.

The CMOS image sensor package module of this embodiment includes a pixel circuit substrate 100, a chip joint structure 200 bonded on a first surface 100a of the pixel circuit substrate 100, and a chip assembly structure 200 disposed in the pixel circuit substrate 100 and the bonding layer 300 The interconnect structure 110 and the rewiring layer 400 laid on the second surface 100b of the pixel circuit substrate 100. In the chip joint structure 200, the signal processing chip 20 and the DRAM chip 30 are interconnected through the chip interconnect layer 230. In addition, The signal processing chip 20, the DRAM chip 30, and the readout circuit of the pixel circuit substrate 100 are all electrically connected to the interconnect structure 110, and the interconnect structure 110 is also electrically connected to the rewiring layer 400, thereby realizing the pixel circuit substrate 100 and the signal processing The electrical interconnection between the chip 20 and the DRAM chip 30 optimizes the structure of the package module, and facilitates the buffering of the digital image signal output by the readout circuit in the DRAM chip 30, and then transmits the DRAM chip 30 to the signal processing chip 20 for processing. When the CMOS image sensor package module is used for image shooting, it is beneficial to increase the processing speed of the transmitted data and digital image signals, thereby improving image quality.

This embodiment also includes a method for forming a CMOS image sensor package module, which is used to manufacture the above-mentioned CMOS image sensor package module.

The method for forming the CMOS image sensor package module of this embodiment first includes the step of forming a chip joint structure. A fan-out process can be used to form the chip joint structure. The following first introduces the method of forming the chip joint structure.

FIG. 1 is a schematic cross-sectional view of a signal processing chip and a DRAM chip after bonding a signal processing chip and a DRAM chip on a temporary carrier in a method for forming a CMOS image sensor package module according to an embodiment of the present invention. 1, the method for forming the chip joint structure of this embodiment includes: providing a temporary carrier board 40, and joining the signal processing chip 20 and the DRAM chip 30 on the temporary carrier board 40 in parallel, wherein the signal processing chip 20 has a first A connecting terminal 21 and a second connecting terminal 22. The DRAM chip 30 has a third connecting terminal 31 and a fourth connecting terminal 32.

The temporary carrier 40 can be a silicon wafer or a substrate made of glass, ceramic, or polymer materials. The signal processing chip 20 and the DRAM chip 30 can be temporarily fixed on the surface of the temporary carrier 40 (ie, the bonding surface) by means such as bonding or adhesion. For example, a dry film or tape can be provided on the surface of the temporary carrier 40 for fixation. The function of the chip. In another embodiment, the signal processing chip 20 and the DRAM chip 30 can be adhered to the surface of the temporary carrier 40 with hot melt adhesive to facilitate the removal of the temporary carrier 40 by heating. For the respective characteristics of the signal processing chip 20 and the DRAM chip 30, reference may be made to the description in the above-mentioned CMOS image sensor package module.

In order to facilitate the interconnection of the first connection terminal 21 of the signal processing chip 20 and the third connection terminal 31 of the DRAM chip 30, as an example, when bonding to the temporary carrier 40, the first connection terminal 21 and the second connection terminal 21 of the signal processing chip 20 The two connecting ends 22 and the third connecting end 31 and the fourth connecting end 32 of the DRAM chip 30 may all face or face away from the bonding surface of the temporary carrier board 40. The distance between the signal processing chip 20 and the DRAM chip 30 can be set according to the subsequent distance in the package module.

Next, a chip molding layer 210 is formed on the temporary carrier board 40. The chip molding layer 210 includes the signal processing chip 20, the DRAM chip 30, and covers the signal processing chip 20, the DRAM chip 30, and The encapsulation material of the joint surface of the temporary carrier 40. The packaging material may include one or more of thermosetting resins such as phenolic resin, urea-formaldehyde resin, formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, polyimide, etc., which may also include various additives.

In this embodiment, the first connection terminal 21 and the third connection terminal 31 are both facing away from the bonding surface of the temporary carrier board 40 as an example. Therefore, after the chip molding layer 210 is formed, the first connection terminal 21 and An interconnection process is performed above the third connection terminal 31 (part of the chip molding layer 210 material can be removed), as shown in FIG. 1. It can be understood that the temporary carrier 40 may be removed before the interconnection process or after the interconnection process. In another embodiment, both the first connection end 21 and the third connection end 31 face the joint surface of the temporary carrier board 40, so as to expose the first connection end 21 and the third connection end 21 to be electrically connected for interconnection. After the chip molding layer 210 is formed, the temporary carrier 40 needs to be removed (the bonding material remaining on the surface of the first connection terminal 21 and the third connection terminal 21 can be removed as needed) before the interconnection process is performed.

2 is a schematic cross-sectional view after forming a dielectric layer, a first electrical connection member and a second electrical connection member in a method for forming a CMOS image sensor package module according to an embodiment of the present invention. 2, the method for forming the chip joint structure of this embodiment may further include: forming a dielectric layer 220 on the chip molding layer 210, the dielectric layer 220 covering the first connection terminal 21 and the third connection End 31; and a first electrical connection piece 201 and a second electrical connection piece 202 are formed in the dielectric layer 220, the first electrical connection piece 201 is in contact and electrically connected with the first connection end 21, the first The second electrical connector 202 is in contact and electrical connection with the third connecting end 31.

The above-mentioned dielectric layer 220 is, for example, an insulating material such as oxide, and other insulating materials used in interconnection processes in this field may also be used. In this embodiment, the first electrical connector 201 and the second electrical connector 202 are, for example, conductive plugs formed in the dielectric layer 220, one end of which is electrically connected to the corresponding connection terminal on the chip, and the other end is exposed from the dielectric layer. 220 surface for interconnection on the dielectric layer 220.

Fig. 3 is a schematic cross-sectional view after forming a chip interconnection layer in the method for forming a CMOS image sensor package module according to an embodiment of the present invention. 3, the method for forming the chip joint structure of this embodiment may further include: forming a chip interconnection layer 230 on the dielectric layer 220, and the chip interconnection layer 230 is connected to the first electrical connector 201 and the The second electrical connectors 202 are electrically connected to obtain the chip joint structure 200 of this embodiment. The chip joint structure 200 includes a chip molding layer 210 (in which the signal processing chip 20 and the DRAM chip 30 are embedded) that are sequentially stacked. , The dielectric layer (wherein the first electrical connection member 201 and the second electrical connection member 202 are embedded) and the chip interconnection layer 230, wherein the chip interconnection layer 230 is disposed on the first electrical connection member 201 and the second The electrical connector 202 is electrically connected to the first connection terminal 21 of the signal processing chip 20 and the third connection terminal 31 of the DRAM chip 30 respectively.

In order to bond with the pixel circuit substrate, the above-mentioned chip joint structure 200 may be formed as a chip-level bonding unit. For example, after the chip interconnection layer 230 is formed, the structure is cut by a chip cutting process disclosed in the art to form a chip. Grade size joint unit. But not limited to this, the above-mentioned chip joint structure 200 may be formed in a wafer-level size, that is, a wafer-level structure, so that when the chip joint structure 200 and the pixel circuit substrate are joined, the chip joint structure 200 can be combined with the pixel circuit substrate. The pixel circuit substrates are opposed and bonded according to the wafer-level size. In addition, a dummy chip may be embedded in the chip joint structure 200. When the chip joint structure 200 and the pixel circuit substrate 100 are subsequently joined, the signal processing chip 20 and the DRAM chip 30 And the dummy chips respectively correspond to suitable positions on the pixel circuit substrate 100, which can control the warpage of the formed package module. It can be understood that, when the chip-level size bonding is performed, the dummy chip may also be bonded to the pixel circuit substrate 100 separately.

The method for forming the CMOS image sensor package module of this embodiment then includes the step of joining the above-mentioned chip combination structure 200 and the pixel circuit substrate 100.

4 is a schematic cross-sectional view of a pixel circuit substrate after bonding a chip assembly structure in a method for forming a CMOS image sensor package module according to an embodiment of the present invention. 4, the method of forming the CMOS image sensor package module of this embodiment includes: bonding the chip joint structure 200 and the pixel circuit substrate 100. The pixel circuit substrate 100 includes a photosensitive area I and a readout circuit area II. The CMOS image The pixel array of the sensor is arranged in the photosensitive area I, the readout circuit is arranged in the readout circuit area II, and the readout circuit has a circuit interconnection terminal (this embodiment includes a first circuit interconnection terminal 101 and a second circuit interconnection terminal 101). The second circuit interconnection terminal 102), the pixel circuit substrate 100 includes a first surface 100a and a second surface 100b opposite to each other, and the chip joint structure 200 is located on the first surface 100a with a bonding layer 300 spaced apart.

For the pixel circuit substrate 100, refer to the description in the aforementioned CMOS image sensor package module. In this embodiment, the incident light is set to enter the pixel unit from the side of the second surface 100b. The chip joint structure 200 is bonded to the first surface 100a through the bonding layer 300. The dummy chip 10 may also be bonded on the first surface 100a. As described above, the chip joint structure 200 may be a die of a chip level, or a structure of a wafer level, so that different bonding methods can be used. Specifically, the chip assembly structure 200 and the pixel circuit substrate 100 can be joined by bonding or bonding. A bonding layer 300 is formed between the chip assembly structure 200 and the pixel circuit substrate 100.

Since the signal processing chip 20 and the DRAM chip 30 in the chip united structure 200 have been interconnected, they are more flexible during bonding. After bonding, the chip interconnection layer 230 of the chip united structure 200 can be interposed between the bonding layer 300 and the dielectric layer 220 In between, it can also be located on the side of the chip joint structure 200 away from the bonding layer 300. In a preferred solution, the second interconnection terminal 22 of the signal processing chip 20 and the fourth interconnection terminal 32 of the DRAM chip 30 are joined in a direction toward the first surface 100a, so as to connect them with the readout circuit in the pixel circuit substrate 100. Electric connection.

After bonding the chip joint structure 200 and the pixel circuit substrate 100, in order to prevent the package module from being affected by external factors (such as water vapor, oxygen, vibration, impact, etching, etc.), the above chip joint structure 200 and the dummy chip 10 are combined with After the pixel circuit substrate 100 is joined, an encapsulation layer 500 can be further formed to cover the above-mentioned chip joint structure 200 (the chip-level size joining unit in FIG. 4) and the dummy chip 10. According to needs, the encapsulation layer 500 may also cover other areas of the pixel circuit substrate 100. The encapsulation layer 500 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc., and may also include such as polycarbonate, polyethylene terephthalate, polyethersulfone, polyphenylene oxide, Thermoplastic resins such as polyamides, polyetherimides, methacrylic resins or cyclic polyolefin resins can also include epoxy resins, phenolic resins, urea-formaldehyde resins, formaldehyde resins, polyurethanes, acrylic resins, vinyl ester resins, and acrylic resins. Thermosetting resins such as imine resins, urea resins or melamine resins may also include organic insulating materials such as polystyrene and polyacrylonitrile. The encapsulation layer 500 may be formed by, for example, a chemical vapor deposition process or an injection molding process. In another embodiment, the chip joint structure 200 is a wafer-level structure, which is opposed to and bonded to the pixel circuit substrate 100 according to the wafer-level size, and the packaging material may not be additionally covered.

The method for forming the CMOS image sensor package module of this embodiment then includes the step of forming an interconnect structure.

5 is a schematic cross-sectional view after forming an interconnection structure in the method for forming a CMOS image sensor package module according to an embodiment of the present invention. 5, the method of forming a CMOS image sensor package module of this embodiment includes: forming an interconnection structure 110 disposed in the pixel circuit substrate 100 and the bonding layer 300, and the interconnection The structure 110 is electrically connected to the circuit interconnection end of the readout single channel, the second connection end 22 of the signal processing chip 20 and the fourth connection end 32 of the DRAM chip 30.

The interconnect structure 110 may include one or more electrical contacts, electrical connections, and electrical connection lines formed between the pixel circuit substrate 100 and the bonding layer 300. In this embodiment, the method of forming the interconnect structure 110 may include performing a hole etching process and a hole filling process from the side of the second surface 100b to form a plurality of conductive plugs (filling holes with conductive materials such as metal) ). Optionally, the plurality of conductive plugs include a first conductive plug 111 electrically connected to a circuit interconnection end of the readout circuit, and the first conductive plug 111 is disposed in the pixel circuit substrate 100. Optionally, the plurality of conductive plugs may include a second conductive plug 112 for electrically connecting to the second connecting end 22 of the signal processing chip 20, and/or a fourth connecting end for electrically connecting to the DRAM chip 30 32 of the third conductive plug 113, the second conductive plug 112 and the third conductive plug 113 both pass through the pixel circuit substrate 100 and the bonding layer 300. In addition, the plurality of conductive plugs may include ends exposed on the second surface 100b to be electrically connected to the rewiring layer formed later. The plurality of conductive plugs may also be formed using methods disclosed in the art.

5, in this embodiment, the plurality of conductive plugs include a first conductive plug 111, a second conductive plug 112, and a third conductive plug 113, and the first conductive plug 111 is in contact and electrically connected to read The circuit interconnection end of the output circuit (the first circuit interconnection end 101 and the second circuit interconnection end 102 in FIG. 4), the second conductive plug 112 contacts the second connection end of the signal processing chip 20 electrically connected 22. The third conductive plug 113 contacts and electrically connects to the fourth connection terminal 32 of the DRAM chip 30.

The method for forming the CMOS image sensor package module of this embodiment further includes a step of forming a rewiring layer.

6 is a schematic cross-sectional view after forming a rewiring layer in the method for forming a CMOS image sensor package module according to an embodiment of the present invention. 6, the method for forming a CMOS image sensor package module of this embodiment includes: forming a rewiring layer 400 on the second surface 100 b of the pixel circuit substrate 100, and the rewiring layer 400 is electrically connected to the interconnect structure 110.

Specifically, the rewiring layer 400 may be formed on the planarization layer on the side of the second surface 100a of the pixel circuit substrate 100, and is in contact with the above-mentioned plurality of conductive plugs of the interconnect structure 110, thereby being electrically connected to the interconnect structure 110. connection. The formation process of the rewiring layer 400 is, for example, first depositing a metal layer on the second surface 100b of the pixel circuit substrate 100 by physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD), and then patterning Chemical treatment to form the rewiring layer 400. The rewiring layer 400 can also be manufactured by a public method.

The above-mentioned rewiring layer 400 may further include rewiring and a bonding pad (I/O pad) electrically connected to the rewiring. The rewiring layer 400 may be configured to connect the interconnect structure 110 (and further to the signal processing chip 20, DRAM) according to design requirements. The electrical connections between the chip 30 and the pixel circuit substrate 100) are re-layed out. The solder pads that are electrically connected to the rewiring can be used to connect the rewiring layer to external signals or devices of the packaged module to process or control the electrical signals transmitted by the rewiring.

After the above steps, the method for forming a CMOS image sensor package module of this embodiment first uses a fan-out process such as the above to form a chip joint structure 200, which includes a chip molding layer 210 embedded with a signal processing chip 20 and a DRAM chip 30, and The chip interconnection layer 230 interconnects the first connection terminal 21 of the signal processing chip 20 and the third connection terminal 31 of the DRAM chip 30, and then the chip joint structure 200 is bonded to the pixel circuit substrate 100, and then the pixel circuit substrate 100 is bonded to the pixel circuit substrate 100. The layer 300 forms an interconnection structure 110 electrically connected to the circuit interconnection end of the readout circuit, the second connection end 22 of the signal processing chip, and the fourth connection end 32 of the DRAM chip 30, and is formed on the second connection end of the pixel circuit substrate 100. On the two surfaces 100b (the side opposite to the chip joint structure 200), the rewiring layer 400 is electrically connected to the interconnect structure 110, which realizes the integration between the chips and the integration between the chip joint structure 200 and the pixel circuit substrate 100. Simple and low cost. The DRAM chip can be used as a buffer element in the CMOS image sensor package module. When used for image capture, it is beneficial to increase the processing speed of the transmitted data and digital image signals, thereby improving the image quality. In addition, the signal processing chip 20 and the DRAM chip 30 are vertically bonded on the pixel circuit substrate 100, the design margin of the pixel array substrate 100 is large, and the overall size of the module is small.

An embodiment of the present invention also provides an imaging device, which is provided with the CMOS image sensor packaging module described in the embodiment of the present invention. The imaging device in the embodiment of the present invention may be a miniature camera, a digital camera, or various electronic devices such as a mobile phone, a tablet, a notebook computer, smart glasses, a digital helmet, a monitor, and the like with a miniature camera function. The imaging device of the embodiment of the present invention adopts the CMOS image sensor package module of the embodiment of the present invention, which helps to achieve a smaller size and better image quality.

The method and structure in this embodiment are described in a progressive manner. The following method and structure mainly describe the differences from the previous method and structure, and the relevant points can be understood by reference.

The foregoing description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any person skilled in the art can use the methods and technical content disclosed above to improve the present invention without departing from the spirit and scope of the present invention. The technical solution makes possible changes and modifications. Therefore, all simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention belong to the technical solution of the present invention. protected range.

Claims

A CMOS image sensor packaging module, characterized in that it comprises:

The pixel circuit substrate includes a photosensitive area and a readout circuit area, the pixel array of the CMOS image sensor is arranged in the photosensitive area, the readout circuit is arranged in the readout circuit area, and the readout circuit has a circuit interconnection terminal, The pixel circuit substrate includes a first surface and a second surface opposite to each other;

A bonding layer, laid on the first surface;

A chip joint structure is arranged on the first surface with an interval between the bonding layer, and the chip joint structure includes a chip molding layer, a dielectric layer, and a chip interconnection layer stacked in sequence, wherein the chip molding layer is embedded with a signal A processing chip and a DRAM chip, the signal processing chip has a first connection end and a second connection end, the DRAM chip has a third connection end and a fourth connection end, and the chip interconnection layer is disposed on the medium layer The first electrical connection piece and the second electrical connection piece are respectively electrically connected to the first connection end and the third connection end;

An interconnection structure, which is provided in the pixel circuit substrate and the bonding layer, the interconnection structure is electrically connected to the circuit interconnection terminal, the second connection terminal, and the fourth connection terminal; and

The rewiring layer is laid on the second surface, and the rewiring layer is electrically connected to the interconnection structure.
The CMOS image sensor package module according to claim 1, wherein the chip interconnection layer is between the bonding layer and the chip molding layer, or the chip molding layer is between the bonding layer. Between the layer and the chip interconnection layer.
The CMOS image sensor package module of claim 1, wherein the interconnection structure comprises a first conductive plug disposed in the pixel circuit substrate, and the first conductive plug is electrically connected to the circuit Interconnection terminals and the rewiring layer.
The CMOS image sensor package module according to claim 3, wherein the circuit interconnection terminal includes a first circuit interconnection terminal and a second circuit interconnection terminal, and the second interconnection structure includes two First conductive plugs to electrically connect the first circuit interconnection end and the rewiring layer, and the second circuit interconnection end and the rewiring layer respectively.
The CMOS image sensor package module of claim 1, wherein the interconnect structure comprises a second conductive plug passing through the pixel circuit substrate and the bonding layer, and the second conductive plug is electrically Connecting the signal processing chip and the rewiring layer.
The CMOS image sensor package module of claim 1, wherein the interconnection structure comprises a third conductive plug passing through the pixel circuit substrate and the bonding layer, and the third conductive plug is electrically Connecting the DRAM chip and the rewiring layer.
The CMOS image sensor package module according to claim 1, wherein the rewiring layer includes a rewiring and a bonding pad electrically connected to the rewiring.
3. The CMOS image sensor package module of claim 1, further comprising: a dummy chip, which is provided on the first surface with the bonding layer interposed therebetween.
The CMOS image sensor package module according to claim 8, wherein the chip joint structure is provided on the first surface corresponding to the readout circuit area, and incident light is set to be from the second One side of the surface enters the pixel array, and the dummy chip is disposed on the first surface corresponding to the photosensitive area.
3. The CMOS image sensor package module according to claim 1, wherein the CMOS image sensor is a back-illuminated CMOS image sensor.
3. The CMOS image sensor package module of claim 1, wherein the bonding layer comprises an adhesive material.
3. The CMOS image sensor package module of claim 1, wherein the first electrical connection member and the second electrical connection member are conductive plugs.
An imaging device, characterized by comprising the CMOS image sensor package module according to any one of claims 1 to 12.
A method for forming a CMOS image sensor package module is characterized in that it comprises:

A chip joint structure is formed, and the chip joint structure includes a chip molding layer, a dielectric layer, and a chip interconnection layer that are sequentially stacked, wherein the chip molding layer is embedded with a signal processing chip and a DRAM chip, and the signal processing chip has a first A connection end and a second connection end, the DRAM chip has a third connection end and a fourth connection end, the chip interconnection layer passes through a first electrical connection piece and a second electrical connection piece arranged in the dielectric layer Are respectively electrically connected to the first connection end and the third connection end;

Joining the chip joint structure and the pixel circuit substrate, the pixel circuit substrate includes a photosensitive area and a readout circuit area, the pixel array of the CMOS image sensor is arranged in the photosensitive area, and the readout circuit is arranged in the readout circuit area, The readout circuit has a circuit interconnection terminal, the pixel circuit substrate includes a first surface and a second surface opposite to each other, and the chip joint structure spacer bonding layer is located on the first surface;

An interconnection structure is formed, the interconnection structure is disposed in the pixel circuit substrate and the bonding layer, the interconnection structure is connected to the circuit interconnection terminal, the second connection terminal, and the fourth connection terminal Are electrically connected; and

A rewiring layer is formed on the second surface, and the rewiring layer is electrically connected to the interconnect structure.
14. The method of forming a CMOS image sensor package module according to claim 14, wherein the method of forming the chip joint structure comprises:

Provide a temporary carrier board, join the signal processing chip and the DRAM chip on the temporary carrier board in parallel, and both the first connection end and the third connection end face the bonding surface of the temporary carrier board;

Forming a chip molding layer, the chip molding layer including the signal processing chip, the DRAM chip, and packaging material covering the signal processing chip, the DRAM chip, and the temporary carrier;

Removing the temporary carrier board to expose the first connection end and the third connection end;

Forming a dielectric layer on the chip molding layer, the dielectric layer covering the first connection end and the third connection end;

A first electrical connection piece and a second electrical connection piece are formed in the dielectric layer, the first electrical connection piece is electrically connected to the first connection end, and the second electrical connection piece is electrically connected to the third connection end Electrical connection; and

A chip interconnection layer is formed on the dielectric layer, and the chip interconnection layer is electrically connected to both the first electrical connection member and the second electrical connection member, thereby obtaining the chip joint structure.
14. The method of forming a CMOS image sensor package module according to claim 14, wherein the method of forming the chip joint structure comprises:

A temporary carrier board is provided, and the signal processing chip and the DRAM chip are joined in parallel on the temporary carrier board, and the first connection end and the third connection end are both facing away from the joint surface of the temporary carrier board One side

Forming a chip molding layer, the chip molding layer including the signal processing chip, the DRAM chip, and packaging material covering the signal processing chip, the DRAM chip, and the temporary carrier;

Forming a dielectric layer on the chip molding layer, the dielectric layer covering the first connection end and the third connection end;

A first electrical connection piece and a second electrical connection piece are formed in the dielectric layer, the first electrical connection piece is electrically connected to the first connection end, and the second electrical connection piece is electrically connected to the third connection end Electrical connection; and

A chip interconnection layer is formed on the dielectric layer, and the chip interconnection layer is electrically connected to both the first electrical connection member and the second electrical connection member, thereby obtaining the chip joint structure.
16. The method for forming a CMOS image sensor package module according to claim 16, wherein the temporary carrier is removed before or after the step of joining the chip joint structure and the pixel circuit substrate.
14. The method for forming a CMOS image sensor package module according to claim 14, wherein the chip joint structure is a bonding unit with a chip level size.
18. The method for forming a CMOS image sensor package module according to claim 18, wherein in the step of joining the chip joint structure and the pixel circuit substrate, a dummy chip is further joined on the first surface.
The method for forming a CMOS image sensor package module according to claim 14, wherein the chip joint structure and the pixel circuit substrate are both wafer-level structures, and when the chip joint structure and the pixel circuit substrate are joined , The chip joint structure and the pixel circuit substrate are opposed and joined according to the wafer-level size.
22. The method for forming a CMOS image sensor package module according to claim 20, wherein the chip joint structure further comprises a dummy chip, and the dummy chip is embedded in the chip molding layer.
The method for forming a CMOS image sensor package module according to claim 14, wherein the method of forming the interconnect structure comprises performing a hole etching process and a hole filling process from one side of the second surface to form a multi A conductive plug.
22. The method for forming a CMOS image sensor package module according to claim 22, wherein the plurality of conductive plugs comprise first conductive plugs, and the first conductive plugs are formed in the pixel circuit substrate, And electrically connect the circuit interconnection terminal and the rewiring layer.
The method for forming a CMOS image sensor package module according to claim 22, wherein the plurality of conductive plugs comprise second conductive plugs, and the second conductive plugs pass through the pixel circuit substrate and the The bonding layer is electrically connected to the second connection terminal and the rewiring layer.
The method for forming a CMOS image sensor package module according to claim 22, wherein the plurality of conductive plugs comprise a third conductive plug, and the third conductive plug passes through the pixel circuit substrate and the The bonding layer is electrically connected to the fourth connection terminal and the rewiring layer.