KR101571353B1 - Image sensor and method of fabricating the same - Google Patents

Abstract

An image sensor and a method of manufacturing the same are provided. The image sensor includes a substrate, an insulating structure including a first metal interconnection formed on a front side of the substrate, a contact hole penetrating the substrate to expose the first metal interconnection, And a pad formed on a backside of the substrate and electrically connected to the first metal interconnection.

Semiconductor device, image sensor

Description

[0001] Image sensor and method for fabricating the same [0002]

The present invention relates to an image sensor and a method of manufacturing the same, and more particularly, to an image sensor having improved productivity and a method of manufacturing the same.

An image sensor is an element that converts an optical image into an electrical signal. Recently, with the development of the computer industry and the communication industry, there has been an increase in demand for image sensors with improved performance in various fields such as digital cameras, camcorders, personal communication systems (PCS), game devices, light cameras, medical micro cameras and robots have.

In the image sensor, light enters from the lens formed on the multilayer wiring layer to the photoelectric conversion portion through the interconnection layers. In this structure, the amount of light actually reaching the photoelectric conversion portion due to a failure due to the layout of the multilayer wiring layer is not sufficient. That is, the aperture ratio to the photoelectric conversion portion is reduced by the multilayer wiring layer, so that the amount of light incident on the photoelectric conversion portion is remarkably reduced, and the sensitivity may be lowered.

In order to solve this problem, the image sensor of the opposite type is implemented. An image sensor of the other irradiation type is a structure for receiving light from the other side (opposite to the wiring portion) of the semiconductor substrate and receiving light by the photoelectric conversion portion. The layout of the multilayer wiring layer enhances the effective aperture ratio and sensitivity .

An object of the present invention is to provide an image sensor with improved productivity.

Another object of the present invention is to provide a method of manufacturing an image sensor with improved productivity.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an image sensor including a substrate, an insulating structure including a first metal interconnection formed on a front side of the substrate, a contact hole exposing the first metal interconnection through the substrate, A conductive spacer formed on a sidewall of the contact hole and connected to the first metal interconnection, and a pad formed on a backside of the substrate and electrically connected to the first metal interconnection.

According to another aspect of the present invention, there is provided a method of manufacturing an image sensor, including forming a plurality of photoelectric conversion units in a substrate by a plurality of device isolation regions, sequentially stacking metal wirings on the substrate A support substrate is bonded to a front side of the substrate, a backside of the substrate is etched, a contact hole is formed through the substrate to expose a part of the metal wiring, Forming a conductive spacer on a sidewall of the contact hole, the conductive spacer being connected to one of the metal wirings; and forming a pad electrically connected to the metal wiring on a rear surface of the substrate.

Other specific details of the invention are included in the detailed description and drawings.

According to an image sensor according to an embodiment of the present invention, a conductive spacer is formed in a contact hole through which a pad is electrically connected. At this time, the conductive spacers are formed so as to be conformal in the contact holes, or to have a smaller width toward the top. Thus, by forming a conductive spacer conformally in a narrow contact hole, the electrical connection between the internal metal wiring and the pad to be formed on the top can be more stable.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Thus, in some embodiments, well known process steps, well-known structures, and well-known techniques are not specifically described to avoid an undue interpretation of the present invention.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions. And "and / or" include each and any combination of one or more of the mentioned items. Like reference numerals refer to like elements throughout the following description.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, an image sensor according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The image sensor according to embodiments of the present invention includes a CCD (Charge Coupled Device) and a CMOS image sensor. Here, the CCD has less noise and image quality than a CMOS image sensor, but requires a high voltage and is expensive. The CMOS image sensor is easy to operate and can be implemented by various scanning methods. In addition, since the signal processing circuit can be integrated on a single chip, the product can be miniaturized and the CMOS process technology can be used in a compatible manner, which can reduce the manufacturing cost. Power consumption is also very low, making it easy to apply to products with limited battery capacity. Therefore, a CMOS image sensor will be described below as an image sensor of the present invention. However, it goes without saying that the technical idea of the present invention can be applied to a CCD as it is.

1 is a cross-sectional view of an image sensor according to an embodiment of the present invention. Fig. 1 shows a sensing region I in which an APS array is formed, an OB region II in an optical black region, and a pad region III in which pads are formed.

1, an image sensor according to an exemplary embodiment of the present invention includes a sensing region I in which an APS array is formed, an OB region II in an optical black region, and a pad 100 The optical black region is a region which blocks the inflow of light and provides a reference of a black signal to the active pixel region. Therefore, the optical black region is formed in the same structure as the sensing region I, As shown in FIG.

A photoelectric conversion element such as a photodiode PD is formed in the substrate 110 of the sensing region I and the OB region II and a plurality of gates 123 may be disposed on the substrate 110 have. This gate 123 may be, for example, a gate of a charge transfer element, a gate of a reset element, a gate of a drive element, or the like. For example, a P-type or N-type bulk substrate may be used, or a P-type or N-type epitaxial layer may be grown on the P-type bulk substrate, or an N-type bulk substrate may be used. A P-type or N-type epitaxial layer may be grown on the substrate. In addition to the semiconductor substrate, a substrate such as an organic plastic substrate may be used. The substrate 110 shown in FIG. 1 shows a case where the bulk substrate is completely removed through the polishing process (described later with reference to FIG. 5) and only the epi layer is left, but the present invention is not limited thereto. That is, if necessary, a part of the bulk substrate may be left.

Insulating structures 122, 124a to 124c, and 126 are disposed on the front surface of the substrate 110. [ The insulating structures 122, 124a to 124c and 126 are formed of an interlayer insulating film 122, a plurality of wirings 124a to 124c sequentially formed on the sensing region I and the OB region II, And a first metal interconnection 126 formed on the third metal interconnection layer III. Here, the first metal interconnection 126 may be at the same level as the lowest level interconnection 124a among the plurality of interconnection 124a to 124c. The first metal interconnection 126 may be at the same level as the second or third highest level interconnection 124b or 124c of the plurality of interconnection 124a to 124c. The first metal interconnection 126 may be made of the same material as the interconnection having the same level (corresponding to 124a in Fig. 4C). Here, the levels of the plurality of wirings 124a to 124c are measured based on the substrate 110. [

On the insulating structures 122, 124a to 124c, and 126, a supporting substrate 132 is adhered and fixed. The support substrate 132 is for securing the strength of the substrate 110 thinned through the polishing process. The supporting substrate 132 may be not only a semiconductor substrate but also any substrate made of a material capable of maintaining mechanical strength. For example, a glass substrate can be used.

Adhesive films 134a and 134b are interposed between the supporting substrate 132 and the insulating structures 122, 124a to 124c and 126 to adhere the supporting substrate 132 and the insulating structures 122, 124a to 124c, . When the support substrate 132 is a silicon substrate, the adhesion films 134a and 134b may be, for example, a silicon oxide film.

On the other hand, an anti-reflection film 142 may be disposed on the backside of the substrate 110. The material / thickness of the antireflection film 142 may vary depending on the wavelength of light used in the photolithography process. For example, a silicon oxide film having a thickness of about 50-200 A and a silicon nitride film having a thickness of about 300-500 A may be stacked as the antireflection film 142.

A buffer film 144 is disposed on the antireflection film 142. The buffer film 144 is intended to prevent the substrate 110 from being damaged in the patterning process for forming the pad 100. As the buffer film 144, for example, a silicon oxide film having a thickness of about 3000-8000 Å may be used.

The pad region III of the image sensor according to an exemplary embodiment of the present invention includes a buffer film 144, an anti-reflection film 142, a contact hole 142 that exposes the first metal interconnection 126 through the substrate 110, (160).

Insulating spacers 170 and conductive spacers 180 may be formed on the sidewalls of the contact holes 160. The insulating spacer 170 may be formed on the sidewall of the contact hole 160 and may have a width narrower toward the upper portion of the contact hole 160. The insulating spacer 170 may be formed of, for example, an oxide film such as a silicon oxide film.

The conductive spacers 180 are formed on the insulating spacers 170 and are electrically connected to the first metal wire 126. The conductive spacer 180 may be formed to have a smaller width toward the upper portion of the contact hole 160, but may have the same width as the upper portion of the contact hole 160. That is, the conductive spacers 180 may be conformally formed in the contact holes 160. The conductive spacers 180 may be formed of a conductive material, for example, W. It may also include a barrier film formed of Ti / TiN. The conductive spacer 180 may be a CVD film, but is not limited thereto.

1, the conductive spacer 180 is formed on the insulating spacer 170 to expose the lower surface of the contact hole 160. However, the conductive spacer 180 is not limited to the contact hole 160, As shown in FIG. That is, the conductive spacers 180 formed on both side walls of the contact holes 160 may be connected to the lower surface of the contact holes 160.

According to the image sensor according to the embodiment of the present invention, the conductive spacer 180 is formed to be conformal in the contact hole 160 or to have a smaller width as it goes to the upper part. Thus, by forming the conductive spacer 180 more congruently within the narrow contact hole 160, the electrical connection between the first metal interconnection 126 and the contact 192 to be formed on the top may be more stable.

A pad 100 electrically connected to the conductive spacer 180 in the contact hole 160 is formed in the pad region III. The pad 100 may be electrically connected to the first metal interconnection 126 by being electrically connected to the conductive spacer 180 through the contact 192. [ Alternatively, the first metal wirings 126 and the contacts 192 may be directly in contact with the lower surface of the contact hole 160, as shown in FIG. That is, according to the image sensor according to the embodiment of the present invention, even if the pad 100 is in contact with the conductive spacer 180 as well as the first metal interconnection 126, Can be connected. Therefore, the first metal interconnection 126 and the pad 100 can be electrically connected more stably.

On the other hand, a blocking film 194 may be formed in the OB region II. The blocking film 194 can block the light flowing into the OB region II by blocking the entire upper surface of the OB region II. At this time, the blocking film 194 may be formed of the same process and / or material as the conductive film forming the pad 100, but is not limited thereto.

Pad 100 and blocking film 194 may be a conductive material and may include, for example, Al. Further, the pad 100 and the blocking film 194 may include a barrier film such as Ti / TiN and / or a capping film such as Ti / TiN. Specifically, for example, Ti / TiN, Al, and Ti / TiN may be sequentially stacked.

Hereinafter, a method of manufacturing an image sensor according to an embodiment of the present invention will be described with reference to FIGS. 1 to 10. FIG. 2 to 10 are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention.

2, device isolation regions (not shown) such as STI (Shallow Trench Isolation) and DTI (Deep Trench Isolation) are formed on a substrate 110 to form sensing regions I, The OB region II and the pad region III are defined.

Then, a plurality of pixels are formed in the sensing region I and the OB region II. Specifically, a photoelectric conversion element, for example, a photodiode PD is formed in the sensing region I and the OB region II, and a plurality of gates 123 are formed. This gate 123 may be, for example, a gate of a charge transfer element, a gate of a reset element, a gate of a drive element, or the like.

Next, the insulating structures 122, 124a to 124c, and 126 are formed on the front surface of the substrate 110. Then, More specifically, the insulating structures 122, 124a to 124c, and 126 are formed of an interlayer insulating film 122, a plurality of wirings 124a to 124c formed sequentially on the sensing region I and the OB region II, And a first metal interconnection 126 formed on the pad region I. Here, the first metal interconnection 126 may be at the same level as the lowest level interconnection 124a among the plurality of interconnection 124a to 124c.

Referring to Fig. 3, the supporting substrate 132 is bonded onto the insulating structures 122, 124a to 124c, and 126. As shown in Fig.

Specifically, an adhesive film 134a is formed on the insulating structures 122, 124a to 124c, and 126 to planarize the surface. An adhesion film 134b is formed on the support substrate 132. [ Thereafter, the adhesive films 134a and 134b are opposed to each other to bond the substrate 110 and the supporting substrate 132 together.

Referring to FIG. 4, the upper and lower sides of the substrate 110 are inverted.

Referring to FIG. 5, the back surface of the substrate 110 is polished. Specifically, the back surface of the substrate 110 is polished by using CMP (Chemical Mechanical Polishing), BGR (Back Grinding), reactive ion etching, or a combination thereof. The thickness of the polished and remained substrate 110 is, for example, about 3-5 占 퐉, but is not limited thereto.

Referring to FIG. 6, an anti-reflection film 142 is formed on the rear surface of the substrate 110. For example, a silicon oxide film having a thickness of about 50-200 Å and a silicon nitride film having a thickness of about 300-500 Å can be formed by using a CVD (Chemical Vapor Deposition) method.

Subsequently, a buffer film 144 is formed on the antireflection film 142. For example, a silicon oxide film having a thickness of about 3000-8000A can be formed by stacking using a CVD method.

Then, a hard mask film 150 is formed on the buffer film 144. Then, The hard mask film 150 may be, for example, a silicon nitride film or a silicon oxide film, or a combination thereof.

Referring to FIG. 7, a contact hole 160 is formed in the pad region III. Specifically, a photoresist pattern (not shown) is formed on the hard mask film 150, and the hard mask film 150 is patterned using a photoresist pattern. Subsequently, after the photoresist pattern is removed, a patterned hard mask film 150 is used to expose the first metal interconnection 126 through the buffer film 144, the antireflection film 142, and the substrate 110, Holes 160 are formed. When forming the contact hole 160, for example, anisotropic etching may be used.

Referring to FIG. 8, after the hard mask layer 150 is removed, an insulating material is deposited in the contact hole 160 and partially etched to form an insulating spacer 170.

For example, an insulating material is deposited in the contact hole 160 by CVD or the like, and the insulating material is etched back to expose the first metal wiring 120, thereby forming the insulating spacer 170.

Referring to FIG. 9, a conductive layer 180a is formed on a substrate 110 on which an insulating spacer 170 is formed. The conductive layer 180a may be formed so that the conductive layer is conformally formed in the contact hole 160. [ The conductive layer 180a can be formed by, for example, a CVD method, but is not limited thereto. However, forming the conductive layer 180a may be performed by a method in which the material to be deposited is more conformally formed. The CVD deposition method is one of the deposition methods in which the material to be deposited is more conformally formed.

The conductive layer 180a may include W and may include a barrier film formed of Ti / TiN. That is, for example, the conductive layer 180a can be formed by sequentially depositing Ti / TiN and W.

Referring to FIG. 10, the conductive spacer (180a in FIG. 9) is partly etched to form the conductive spacer 180 on the sidewall of the contact hole 160.

At this time, partial etching of the conductive layer 180a can proceed to an etch-back process. That is, the entire surface of the substrate may be etched back to leave a part of the conductive layer 180a only on the sidewall of the contact hole 160, thereby forming the conductive spacer 180.

Alternatively, etching the conductive layer 180a partially can be performed by a CMP process. That is, the entire surface of the substrate is subjected to CMP to etch the entire conductive layer 180a on the buffer film 144 and to leave only the conductive layer 180a in the contact hole 160 to form the conductive spacer 180 have.

Alternatively, both the etch-back process and the CMP process may be performed to partially etch the conductive layer 180a. Here, after the etch-back process, the CMP process may be performed, or the etch-back process may be performed after the CMP process.

However, it is to be understood that the present invention is not limited to the above description, and may include all processes that will be apparent to those skilled in the art, which can partially etch the conductive layer 180a and form the conductive spacers 180 only in the contact holes 160 to be.

The conductive spacers 180 are formed on the insulating spacers 170 and are electrically connected to the first metal wires 126. The conductive spacer 180 may be formed to have a smaller width toward the upper portion of the contact hole 160, but may have the same width as the upper portion of the contact hole 160. That is, the conductive spacers 180 may be conformally formed in the contact holes 160. The conductive spacer 180 may be formed on the insulating spacer 170 to expose the lower surface of the contact hole 160. The conductive spacer 180 may be formed on the lower surface of the contact hole 160 As shown in Fig. That is, the conductive spacers 180 formed on both side walls of the contact holes 160 may be connected to the lower surface of the contact holes 160.

1, a contact 192 and a pad 100 which are electrically connected to the conductive spacer 180 in the contact hole 160 are formed in the pad region III and a pad 100 is formed in the OB region II. A blocking film 194 is formed.

Concretely, a conductive material (not shown) is formed conformally along the buffer film 144 and the conductive spacer 180, and the conductive material is patterned. By doing so, the contact 192, the pad 100, and the blocking film 194 are simultaneously formed. Meanwhile, the contact 192 and the pad 100 are formed at the same time, but the present invention is not limited thereto. If necessary, a separate process may be used to first form a contact electrically connected to the first metal interconnection 126 or the conductive spacer 180, and then to form the pad 100 electrically connected to the contact.

Hereinafter, an apparatus using an image sensor according to embodiments of the present invention will be described with reference to FIGS. 11 to 14. FIG. FIG. 11 is a view for explaining a chip implementing an image sensor according to embodiments of the present invention, and FIGS. 12 to 14 are views for explaining a processor-based apparatus including an image sensor according to embodiments of the present invention These are the drawings. Fig. 12 shows a computer device, Figs. 13A and 13B show a camera device, and Fig. 14 shows a mobile phone device. The image sensor according to embodiments of the present invention may be applied to other devices (e.g., a scanner, a mechanized timepiece, a navigation device, a video phone, a supervisory device, an autofocus device, a tracking device, Stabilizers, etc.).

Referring to FIG. 11, a chip 200 implementing an image sensor according to embodiments of the present invention includes a sensor array 210 in which pixels including an optical sensing element are arranged in a two-dimensional array, a timing generator, A column decoder 220, a row decoder 230, a row driver 240, a correlated double sampler (CDS) 250, an analog to digital converter (ADC) 260, a latch 270, a column decoder 280, and the like.

The sensor array 210 includes a plurality of unit pixels arranged two-dimensionally. The plurality of unit pixels serve to convert the optical image into an electrical output signal. The sensor array 210 is driven by receiving a plurality of driving signals such as a row selection signal, a reset signal, and a charge transfer signal from the row driver 240. In addition, the converted electrical output signal is provided to the correlated double sampler 250 through a vertical signal line.

The timing generator 220 provides a timing signal and a control signal to the row decoder 230 and the column decoder 280.

The row driver 240 provides a plurality of driving signals to the active pixel sensor array 210 for driving a plurality of unit pixels according to the decoded result in the row decoder 230. [ Generally, when unit pixels are arranged in a matrix form, a driving signal is provided for each row.

The correlated dual sampler 250 receives and holds and samples the output signal formed on the active pixel sensor array 210 via the vertical signal line. That is, a specific noise level and a signal level by the output signal are sampled double, and a difference level corresponding to the difference between the noise level and the signal level is output.

The analog-to-digital converter 260 converts the analog signal corresponding to the difference level into a digital signal and outputs the digital signal.

The latch unit 270 latches the digital signal and the latched signal is sequentially output to the image signal processing unit (not shown) according to the decoding result in the column decoder 280.

All of the functional blocks shown in FIG. 11 may be composed of one chip or a plurality of chips. For example, the timing generator 220 may be formed of a single chip, and the remaining chips may be formed of a single chip. For example, the described chips may be implemented in a package.

12, the computing device 300 includes a central processing unit (CPU) 320 such as a microprocessor or the like capable of communicating with an input / output (I / O) . Image sensor 310 may communicate with the device via bus 305 or other communication link. The processor-based device 300 may further include a RAM 340 and / or a port 360 that can communicate with the CPU 320 via the bus 305. [ The port 360 may be a port capable of coupling a video card, a sound card, a memory card, a USB device, or the like, or communicating data with another device. The image sensor 310 may be integrated with a CPU, a digital signal processing device (DSP), a microprocessor, or the like. Also, the memories may be integrated together. Of course, in some cases, it may be integrated on a separate chip from the processor.

13A, a camera device 400 includes an image sensor package 410 in which an image sensor 413 is mounted on a circuit board 411 through a bonding wire. A housing 420 is attached on the circuit board 411 and the housing 420 protects the circuit board 411 and the image sensor 413 from the external environment.

A barrel portion 421 through which an image to be imaged passes is formed in the housing 420. A protective cover 422 is provided at an outer end portion facing the outside of the barrel portion 421 and an infrared ray Blocking and anti-reflection filter 423 can be mounted. A lens 424 is mounted in the inside of the barrel section 421 and the lens 424 can be moved along the thread of the barrel section 421.

Referring to FIG. 13B, the camera device 500 uses an image sensor package 501 using a through via 572. With the through vias 572, the image sensor 570 and the circuit board 560 can be electrically connected without using wire bonding. Reference numeral 520, which is not described here, is a first lens, 540 is a second lens, and 526 and 527 are lens components. Reference numeral 505 is a support member, 545 is an aperture, 510 and 530 are transparent substrates, and 550 is glass.

Referring to FIG. 14, an image sensor 452 is attached to a predetermined position of the cellular phone system 450. It is apparent to those skilled in the art that the image sensor 452 may be attached to a portion different from the position shown in Fig.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention.

2 to 10 are views for explaining a method of manufacturing an image sensor according to an embodiment of the present invention.

11 is a view for explaining a chip implementing an image sensor according to embodiments of the present invention.

12 to 14 are diagrams for explaining a processor-based apparatus including an image sensor according to embodiments of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS (S)

1: image sensor 100: pad

126: first metal wiring 132: supporting substrate

142: antireflection film 144: buffer film

160: contact hole 170: insulating spacer

180: conductive spacer

Claims (10)

Board; An insulating structure including a first metal interconnection formed on a front side of the substrate; A contact hole penetrating the substrate to expose the first metal interconnection; A conductive spacer formed on a sidewall of the contact hole and connected to the first metal interconnection; And And a pad formed on a backside of the substrate and electrically connected to the first metal wiring, Wherein the pad comprises a contact directly in contact with the first metal interconnection at a lower surface of the contact hole. The method according to claim 1, And an insulating spacer formed between the contact hole and the conductive spacer. The method according to claim 1, Wherein the conductive spacer comprises W. The method according to claim 1, Wherein the conductive spacer is a CVD film. The method according to claim 1, Wherein the pad comprises Al. A plurality of photoelectric conversion portions are formed in the substrate by a plurality of device isolation regions, Forming an insulating structure including metal wirings sequentially stacked on the substrate, Bonding a support substrate to a front side of the substrate, Etching the backside of the substrate, Forming a contact hole through the substrate to expose a part of the metal wiring, Forming a conductive spacer on a side wall of the contact hole, the conductive spacer being connected to one of the metal wirings; And forming a pad electrically connected to the metal wiring on a rear surface of the substrate, Wherein the pad includes a contact directly in contact with the metal wiring on the lower surface of the contact hole. The method according to claim 6, The formation of the conductive spacer may be performed, Forming a conductive layer on the substrate, And partially etching the conductive layer to form the conductive spacer. 8. The method of claim 7, The formation of the conductive layer may be performed, To the CVD process. 8. The method of claim 7, Wherein the etching of the conductive layer proceeds in an etch-back process or a CMP process. The method according to claim 6, Further comprising forming an insulating spacer on a sidewall of the contact hole before forming the conductive spacer, Wherein the conductive spacers are formed on the insulating spacers.

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