KR101555179B1 - Fabficating method of image sensor and image sensor fabricated by the same - Google Patents

Abstract

A manufacturing method of an image sensor and an image sensor manufactured thereby are provided. A method of manufacturing an image sensor includes providing a substrate defined by a pad region, an OB region, and a cell region, forming an insulating structure including a metal wiring on one surface of the substrate, forming a first passivation film on the other surface of the substrate, A first passivation film and a contact hole exposing a part of the metal wiring through the substrate and formed in a pad and an OB region electrically connected to the metal wiring through the contact hole and blocking the OB region at the same height as the pad And forming a conductive pattern including a blocking film on the first passivation film.

Semiconductor device, image sensor

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing an image sensor,

The present invention relates to a method of manufacturing an image sensor and an image sensor manufactured thereby, and more particularly, to a method of manufacturing an image sensor and an image sensor manufactured by the method.

An image sensor is an element that converts an optical image into an electrical signal. Recently, with the development of the computer industry and the communication industry, there has been an increase in demand for image sensors with improved performance in various fields such as digital cameras, camcorders, personal communication systems (PCS), game devices, light cameras, medical micro cameras and robots have.

In the image sensor, light enters from the lens formed on the multilayer wiring layer to the photoelectric conversion portion through the interconnection layers. In this structure, the amount of light actually reaching the photoelectric conversion portion due to a failure due to the layout of the multilayer wiring layer is not sufficient. That is, the aperture ratio to the photoelectric conversion portion is reduced by the multilayer wiring layer, so that the amount of light incident on the photoelectric conversion portion is remarkably reduced, and the sensitivity may be lowered.

In order to solve this problem, the image sensor of the opposite type is implemented. An image sensor of the other irradiation type is a structure for receiving light from the other side (opposite to the wiring portion) of the semiconductor substrate and receiving light by the photoelectric conversion portion. The layout of the multilayer wiring layer enhances the effective aperture ratio and sensitivity .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing an image sensor with improved reliability.

Another object of the present invention is to provide an image sensor with improved reliability.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing an image sensor, including: providing a substrate defined by a pad region, an OB region, and a cell region; forming an insulating structure including a metal wiring on one surface of the substrate; Forming a first passivation film on the other surface of the substrate, forming a contact hole in the pad region through the first passivation film and the substrate to expose a part of the metal wiring, Forming a conductive pattern on the first passivation film, the conductive pattern including an electrically connected pad and a blocking film formed on the OB region and blocking the OB region at the same height as the pad.

According to another aspect of the present invention, there is provided a method of manufacturing an image sensor, comprising: providing a semiconductor substrate; bonding a support substrate to a front surface of the substrate; etching the other surface of the substrate; Forming a first passivation film on the other surface, forming a conductive pattern including a pad for inputting and outputting an external signal on the first passivation film, and performing a first annealing process to remove dangling bonds of the substrate .

According to another aspect of the present invention, there is provided an image sensor including a semiconductor substrate having a pad region, an OB region, and a sensing region defined therein, an insulating structure including a first metal wiring formed on one surface of the substrate, A pad formed on the other surface of the substrate in the pad region and electrically connected to the first metal interconnection, and a pad formed in the OB region at the same height as the pad And a blocking film formed on the insulating structure to block the OB region, and a first passivation film formed between the conductive pattern and the other surface of the substrate.

Other specific details of the invention are included in the detailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Thus, in some embodiments, well known process steps, well-known structures, and well-known techniques are not specifically described to avoid an undesirable interpretation of the present invention.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive of reference to one or more other elements, steps, operations and / And does not exclude the presence or addition thereof. And "and / or" include each and any combination of one or more of the mentioned items. Like reference numerals refer to like elements throughout the following description.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, an image sensor according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The image sensor according to embodiments of the present invention includes a CCD (Charge Coupled Device) and a CMOS image sensor. Here, the CCD has less noise and image quality than a CMOS image sensor, but requires a high voltage and is expensive. The CMOS image sensor is easy to operate and can be implemented by various scanning methods. In addition, since the signal processing circuit can be integrated on a single chip, the product can be miniaturized and the CMOS process technology can be used in a compatible manner, which can reduce the manufacturing cost. Power consumption is also very low, making it easy to apply to products with limited battery capacity. Therefore, a CMOS image sensor will be described below as an image sensor of the present invention. However, it goes without saying that the technical idea of the present invention can be applied to a CCD as it is.

1 is a cross-sectional view of an image sensor according to an embodiment of the present invention. Fig. 1 shows a sensing region I in which an APS array is formed, an OB region II in an optical black region, a logic region III in which peripheral circuits are formed, and a pad region IV in which pads are formed.

1, an image sensor according to an exemplary embodiment of the present invention includes a sensing area I in which an APS array is formed, an OB area II in an optical black area, a logic area in which a peripheral circuit is formed, (III) and a pad 194. The OB region II is a region for blocking the inflow of light and providing a reference of a black signal to the active pixel region, The dark current of the active pixel of the sensing region I is corrected on the basis of the dark current of the OB region II so that the dark current of the sensing region I is corrected. The logic region III includes a core region and a peri region where peripheral circuits are formed, and is formed so as to block the inflow of light.

A photoelectric conversion element such as a photodiode PD is formed in the substrate 110 of the sensing region I and the OB region II and a plurality of gates 123 may be disposed on the substrate 110 have. This gate 123 may be, for example, a gate of a charge transfer element, a gate of a reset element, a gate of a drive element, or the like. For example, a P-type or N-type bulk substrate may be used, or a P-type or N-type epitaxial layer may be grown on the P-type bulk substrate, or an N-type bulk substrate may be used. A P-type or N-type epitaxial layer may be grown on the substrate. In addition to the semiconductor substrate, a substrate such as an organic plastic substrate may be used. The substrate 110 shown in FIG. 1 shows a case where the bulk substrate is completely removed through the polishing process (described later with reference to FIG. 5) and only the epi layer is left, but the present invention is not limited thereto. That is, if necessary, a part of the bulk substrate may be left.

On the other hand, in the logic region III, an integrated circuit including at least one gate 127 for operation of the device and transmission / reception of signals can be formed.

Insulating structures 122, 124a to 124c, 125, and 126 are disposed on the front surface of the substrate 110. [ The insulating structures 122, 124a to 124c, 125 and 126 include an interlayer insulating film 122, a plurality of wirings 124a to 124c sequentially formed on the sensing region I and the OB region II, A wiring 125 formed on the logic region III and a first metal interconnection 126 formed on the pad region IV. Here, the first metal interconnection 126 may be at the same level as the lowest level interconnection 124a among the plurality of interconnection 124a to 124c. The first metal interconnection 126 may be at the same level as the second or third highest level interconnection 124b or 124c of the plurality of interconnection 124a to 124c. The first metal interconnection 126 may be made of the same material as the interconnection having the same level (corresponding to 124a in FIG. 1). Here, the levels of the plurality of wirings 124a to 124c are measured based on the substrate 110. [

On the insulating structures 122, 124a to 124c, 125 and 126, a supporting substrate 132 is adhered and fixed. The support substrate 132 is for securing the strength of the substrate 110 thinned through the polishing process. The supporting substrate 132 may be not only a semiconductor substrate but also any substrate made of a material capable of maintaining mechanical strength. For example, a glass substrate can be used.

124a to 124c, 125, and 126 are formed between the supporting substrate 132 and the insulating structures 122, 124a to 124c, 125, and 126 in order to adhere the supporting substrate 132 and the insulating structures 122, 124a to 124c, , 134b may be interposed. When the support substrate 132 is a silicon substrate, the adhesion films 134a and 134b may be, for example, a silicon oxide film.

On the other hand, an anti-reflection film 142 may be disposed on the backside of the substrate 110. The material / thickness of the antireflection film 142 may vary depending on the wavelength of light used in the photolithography process. For example, a silicon oxide film having a thickness of about 50-200 A and a silicon nitride film having a thickness of about 300-500 A may be stacked as the antireflection film 142.

A buffer film 144 is disposed on the antireflection film 142. As the buffer film 144, for example, a silicon oxide film having a thickness of about 100 to 5000 Å may be used. The buffer film 144 may also be used to protect the substrate 110 from damage during the patterning process to form the conductive patterns 192, 194, and 196 including the contact 192, the pad 194, and the blocking film 196 . Therefore, it is generally formed to have a sufficient thickness to prevent damage to the substrate 110, for example, a thickness of about 3000-8000 ANGSTROM. However, according to the image sensor according to an embodiment of the present invention, since the first passivation film 152 formed of SiN or the like is formed on the buffer film 144, the buffer film 144 may not be formed excessively thick. Therefore, as the thickness of the buffer layer 144 is reduced, the sensing area I and the buffer layer 144, in which the buffer layer 144 and the like are not formed, The step difference between the other regions formed can be reduced. Accordingly, the unioformitivity of the entire surface of the substrate 110 can be improved, and a more stable image device can be manufactured.

A first passivation film 152 is disposed on the buffer film 144. The first passivation film 152 may be formed of, for example, a nitride film, that is, SiN, and may be formed to a thickness of, for example, about 1000 to 5000 ANGSTROM. The first passivation film 152 protects the substrate 110 in the patterning process to form the conductive patterns 192, 194 and 196 including the contact 192, the pad 194 and the blocking film 196. Also, the first passivation film 152 may function as a passivation film in an annealing process that proceeds to remove the dangling bonds after forming the conductive patterns 192, 194, and 196. At this time, since the first passivation film 152 is formed adjacent to the substrate 110, the dangling bonds can be removed more efficiently.

In general, a passivation film is formed on the conductive patterns 192, 194, and 196. Therefore, the distance between the passivation film and the substrate 110 is considerable, and the conductive patterns 192, 194, and 196 block the gap between the passivation film and the substrate 110. Therefore, when the annealing process for removing the dangling bonds of the substrate 110 is performed, it is difficult for the passivation process to proceed effectively. However, since the first passivation film 152 is formed under the pad 194 and the blocking film 196 in the image sensor according to the embodiment of the present invention, the substrate 110 and the first passivation film 152 Are formed in close proximity. Thus, the dangling bonds can be removed more efficiently during the annealing process. In the image sensor, the dark current of the active pixel of the sensing region I formed on the same line is corrected based on the dark current of the OB region IV. At this time, if the dark current is large in the OB region (IV) and the difference between the lines is large, a characteristic difference occurs between the active pixel lines of the sensing region (I), which causes a signal failure and an increase in noise. In the image sensor according to the embodiment of the present invention, the dangling bonds are effectively removed, and the dark current in the OB region (IV) is significantly reduced, so that an image sensor with improved reliability can be provided.

The pad region IV includes a first passivation film 152, a buffer film 144, an antireflection film 142, a contact hole 160 which penetrates the substrate 110 and exposes the first metal interconnection 126, .

Insulation spacers 170 are formed on the sidewalls of the contact holes 160. The insulating spacer 170 may be formed on the sidewall of the contact hole 160 and may have a width narrower toward the upper portion of the contact hole 160. The insulating spacer 170 may be formed of, for example, an oxide film such as a silicon oxide film.

On the first passivation film 152, conductive patterns 192 and 194 including a pad 194 and a blocking film 196 are formed. The pad 194 is formed in the pad region IV and is connected to the contact 192 filling the contact hole 160 at the backside of the substrate 110 and electrically connected to the first metal interconnection 126 do. At this time, the insulating spacer 170 insulates the contact 192 from the substrate 110. The blocking film 196 is formed to block the logic region III and the OB region II at the same height as the pad 194 in the logic region III and the OB region II so that the insulating structures 122, , 125, 126).

The conductive patterns 192, 194 and 196 including the contact 192, the pad 194 and the blocking film 196 may comprise, for example, Al. Further, the pad 194 and the blocking film 196 may include a barrier film such as Ti / TiN and / or a capping film such as Ti / TiN. Specifically, for example, Ti / TiN, Al, and Ti / TiN may be sequentially stacked.

Hereinafter, a method of manufacturing an image sensor according to an embodiment of the present invention will be described with reference to FIGS. 1 to 10. FIG. 2 to 10 are cross-sectional views illustrating a method of manufacturing an image sensor according to an embodiment of the present invention.

2, device isolation regions (not shown) such as STI (Shallow Trench Isolation) and DTI (Deep Trench Isolation) are formed on a substrate 110 to form sensing regions I, An OB region II, a logic region III, and a pad region IV.

Then, a plurality of pixels are formed in the sensing region I and the OB region II. Specifically, a photoelectric conversion element, for example, a photodiode PD is formed in the sensing region I and the OB region II, and a plurality of gates 123 are formed. This gate 123 may be, for example, a gate of a charge transfer element, a gate of a reset element, a gate of a drive element, or the like. On the other hand, in the logic region III, an integrated circuit including one or more gates 127 for operation of devices and transmission / reception of signals can be formed.

Next, the insulating structures 122, 124a to 124c, 125 and 126 are formed on the front surface of the substrate 110. Next, Specifically, the insulating structures 122, 124a to 124c, 125 and 126 are formed on the interlayer insulating film 122 and a plurality of wirings 124a to 124c (not shown) formed sequentially on the sensing region I and the OB region II And a first metal wiring 126 formed on the pad region I and a wiring 125 formed on the logic region III. Here, the first metal interconnection 126 may be at the same level as the lowest level interconnection 124a among the plurality of interconnection 124a to 124c.

Referring to FIG. 3, the supporting substrate 132 is bonded onto the insulating structures 122, 124a to 124c, 125, and 126.

Specifically, an adhesive film 134a is formed on the insulating structures 122, 124a to 124c, 125, and 126 to planarize the surface. An adhesion film 134b is formed on the support substrate 132. [ Thereafter, the adhesive films 134a and 134b are opposed to each other to bond the substrate 110 and the supporting substrate 132 together.

Referring to FIG. 4, the upper and lower sides of the substrate 110 are inverted.

Referring to FIG. 5, the back surface of the substrate 110 is polished. Specifically, the back surface of the substrate 110 is polished by using CMP (Chemical Mechanical Polishing), BGR (Back Grinding), reactive ion etching, or a combination thereof. The thickness of the polished and remained substrate 110 is, for example, about 3-5 占 퐉, but is not limited thereto.

Referring to FIG. 6, an anti-reflection film 142 is formed on the rear surface of the substrate 110. For example, a silicon oxide film having a thickness of about 50-200 Å and a silicon nitride film having a thickness of about 300-500 Å can be formed by using a CVD (Chemical Vapor Deposition) method.

Then, a rear interlayer insulating film, which is a buffer film 144, is formed on the antireflection film 142. For example, a silicon oxide film having a thickness of about 100 to 5000 Å can be formed by stacking using a CVD method.

Subsequently, a first passivation film 152 is formed on the buffer film 144. For example, a silicon nitride film having a thickness of about 1000 to 5000 Å, that is, SiN, may be deposited by using a PE-CVD method.

Referring to FIG. 7, a contact hole 160 is formed in the pad region IV. Specifically, a photolithography process is performed to form a photoresist pattern (not shown) on the first passivation film 152. Then, the first passivation film 152, the buffer film 144, the antireflection film 142, and the contact hole for penetrating the substrate 110 and exposing the first metal interconnection 126 are formed using the photoresist pattern as an etching mask, (160). When forming the contact hole 160, for example, anisotropic etching may be used.

Referring to FIG. 8, an insulating material is deposited in the contact hole 160 and partially etched to form an insulating spacer 170.

For example, an insulating material is deposited in the contact hole 160 by CVD or the like, and the insulating material is etched back to expose the first metal wiring 126, thereby forming the insulating spacer 170.

Referring to FIG. 9, conductive patterns 192, 194, and 196 are formed that include a contact 192, a pad 194, and a blocking film 196.

Specifically, a contact 192 and a pad 194 electrically connected to the conductive spacer 180? In the contact hole 160 are formed in the pad region IV, and the contact 192 and the contact 192, A blocking film 196 blocking light is formed in the pads 194 extending from the first passivation film 192 to the first passivation film 152 and the OB region II and the logic region III.

More specifically, a conductive material (not shown) is conformally formed along the first passivation film 152 and the insulating spacer 170, and the conductive material is patterned. By doing so, the contact 192, the pad 194, and the blocking film 196 are simultaneously formed. On the other hand, here, the contact 192 and the pad 194 are simultaneously However, the present invention is not limited thereto. If desired, a separate process may be used to first form a contact electrically connected to the first metal interconnection 126, followed by forming a pad 194 electrically connected to the contact.

Next, referring to FIG. 10, a first annealing process is performed.

The first annealing process may be an annealing process for passivation. When the first annealing process is performed, the dangling bonds in the substrate 110 are removed through the first passivation film 152 adjacent to the substrate 110. Specifically, the hydrogen supplied to the substrate 110 through the first passivation film 152 may be Si-H bonded to remove the dangling bonds.

According to the method of manufacturing an image sensor according to an embodiment of the present invention, the first passivation film 152 is formed closer to the substrate 110. That is, a first passivation film 152 is formed under the pad 194 and the blocking film 196. Since the first passivation film 152 is formed adjacent to the substrate 110, the dangling bonds can be more effectively removed during the first annealing process for removing the dangling bonds using the first passivation film 152.

Referring again to FIG. 11, the first passivation film 152, which is exposed to the conductive patterns 192, 194, and 196 by an etching mask, is removed.

At this time, the removal of the first passivation film 152 can be performed, for example, by an etch bach process. That is, the exposed first passivation film 152 may be removed without additional photoprocessing. When the exposed first passivation film 152 is removed, the buffer film 144 is partially exposed. 10, since a part of the pad region IV and the first passivation film 152 of the sensing region I are exposed, a portion of the pad region IV and a portion of the sensing region I The first passivation film 152 is removed and the buffer film 144 is exposed. Since the first passivation film 152 is formed of SiN or the like, the light transmittance is poor. Therefore, by removing the first passivation film 152 in the sensing region I, the light receiving efficiency is not lowered.

Next, referring to FIG. 12, a second annealing process is performed.

The second annealing process may be a UV annealing process. The second annealing process heals the damage of the substrate 110 at the time of etching the first passivation film 152.

According to the method of manufacturing an image sensor according to an embodiment of the present invention, the first passivation film 152 is formed closer to the substrate 110. That is, a first passivation film 152 is formed under the pad 194 and the blocking film 196. Since the first passivation film 152 is formed adjacent to the substrate 110, the dangling bonds can be more effectively removed during the first annealing process for removing the dangling bonds using the first passivation film 152. After the first passivation film 152 is formed, a first annealing process is performed to form a pad 194 and a blocking film 196 on the first passivation film 152, After the first passivation film 152 is exposed, a second annealing process is performed. That is, by carrying out the annealing process in a divided manner, the damage of the substrate 110 in the manufacturing process can be more effectively healed.

According to the method of manufacturing an image sensor according to an embodiment of the present invention, a photolithography process for forming the conductive patterns 192, 194, and 196 is only required once. In patterning the first passivation film 152, , No photo process is required. This is because a part of the first passivation film 152 can be removed by the etch-back process using the conductive patterns 192, 194, and 196 as an etching mask. Therefore, in forming the rear surface of the image sensor, an image sensor can be manufactured by a small photolithography process. That is, since the photolithography process, which is an expensive process, can be reduced, the cost can be reduced and the productivity can be improved.

Hereinafter, an image sensor according to another embodiment of the present invention will be described with reference to FIG. 13 is a cross-sectional view of an image sensor according to another embodiment of the present invention.

Referring to FIG. 13, the image sensor according to another embodiment of the present invention further includes a second passivation film 154 formed on the conductive patterns 192, 194, and 196.

The second passivation film 154 is not formed on the sensing region I and is formed on the blocking film 196 on the OB region II and the logic region III. Is formed on the pad region (IV) above the pad (194), and is formed to partially open the upper region of the pad (194).

Hereinafter, a method of manufacturing an image sensor according to another embodiment of the present invention will be described with reference to FIGS. 2 to 8 and FIGS. 13 to 18. FIG. 14 to 18 are views for explaining a method of manufacturing an image sensor according to another embodiment of the present invention.

2 to 8, an antireflection film 142, a buffer film 144, and a first passivation film 152 are formed on a substrate 110, and a contact hole 160 is formed in the pad region IV The description thereof is omitted because it is the same as that of the method of manufacturing an image sensor according to an embodiment of the present invention.

14, conductive patterns 192, 194, and 196 are formed that include a contact 192, a pad 194, and a blocking film 196. As shown in FIG.

That is, a contact 192 and a pad 194, which are electrically connected to the first metal interconnection 126 by embedding the contact hole 160 in the pad region IV, are formed, and the OB region II and the logic region (III), a blocking film 196 blocking light is formed.

Concretely, a conductive material (not shown) and an oxidized material (not shown) are conformally formed and patterned along the first passivation film 152 and the insulating spacer 170 to form conductive patterns 192, 194, An oxide film pattern 180 formed on the conductive patterns 192, 194, and 196 is formed.

On the other hand, here, the contact 192 and the pad 194 are simultaneously However, the present invention is not limited thereto. If desired, a separate process may be used to first form a contact electrically connected to the first metal interconnection 126, followed by forming a pad 194 electrically connected to the contact.

15, a second passivation film 154 is formed on the substrate 110 on which the conductive patterns 192, 194, and 196 are formed.

The second passivation film 154 may be formed to cover the entire substrate 110, for example, by depositing a silicon nitride film, that is, SiN, using a PE-CVD method.

Next, referring to FIG. 16, a first annealing process is performed.

As the first annealing process proceeds, the dangling bonds in the substrate 110 are removed through the first passivation film 152 and the second passivation film 154. Specifically, the hydrogen supplied to the substrate 110 through the first passivation film 152 and the second passivation film 154 may be Si-H bonded to remove dangling bonds.

According to the method of manufacturing an image sensor according to another embodiment of the present invention, the first passivation film 152 is formed closer to the substrate 110. That is, a first passivation film 152 is formed under the pad 194 and the blocking film 196. Since the first passivation film 152 is formed adjacent to the substrate 110, the dangling bonds can be more effectively removed during the first annealing process for removing the dangling bonds using the first passivation film 152.

A first passivation film 152 is formed under the pad 194 and the blocking film 196 and a second passivation film 154 is formed over the conductive patterns 192, Some damage in the patterning process of the patterns 192, 194, and 196 can be more effectively healed.

Next, referring to FIG. 17, the first and second passivation films 154 are patterned.

Specifically, the first and second passivation films 154 are partially removed by performing a photolithography process. At this time, the first and second passivation films 154 on the sensing region I are all removed, and the second passivation film 154 is removed so that a part of the pad region IV is opened.

That is, by the patterning process, the first and second passivation films 154 are all removed in the sensing region I, and the light transmittance can be improved. On the other hand, the first passivation film 152, the blocking film 196, and the second passivation film 154 are sequentially stacked on the OB region II and the logic region III to completely block the transmission of light. A pad 194 is formed on the first passivation film 152 and a second passivation film 154 is formed on the pad 194. The second passivation film 154 is formed on the pad region IV, A part of which is removed so that the pad 194 can be connected to the external terminal.

Next, referring to FIG. 18, a second annealing process is performed.

The second annealing process may be, for example, a UV annealing process, and the annealing process may heal the substrate 110 damage in the fabrication process, particularly damage to the patterning process of the first and second passivation films 154 .

Hereinafter, an apparatus using an image sensor according to embodiments of the present invention will be described with reference to FIGS. 19 to 22. FIG. FIG. 19 is a view for explaining a chip implementing an image sensor according to an embodiment of the present invention, and FIGS. 20 to 22 are views for explaining a processor-based apparatus including an image sensor according to embodiments of the present invention These are the drawings. Fig. 20 shows a computer device, Figs. 21A and 21B show a camera device, and Fig. 22 shows a mobile phone device. The image sensor according to embodiments of the present invention may be applied to other devices (e.g., a scanner, a mechanized timepiece, a navigation device, a video phone, a supervisory device, an autofocus device, a tracking device, Stabilizers, etc.).

Referring to FIG. 19, a chip 200 implementing an image sensor according to embodiments of the present invention includes a sensor array 210 in which pixels including an optical sensing element are arranged in two dimensions, a timing generator, A column decoder 220, a row decoder 230, a row driver 240, a correlated double sampler (CDS) 250, an analog to digital converter (ADC) 260, a latch 270, a column decoder 280, and the like.

The sensor array 210 includes a plurality of unit pixels arranged two-dimensionally. The plurality of unit pixels serve to convert the optical image into an electrical output signal. The sensor array 210 is driven by receiving a plurality of driving signals such as a row selection signal, a reset signal, and a charge transfer signal from the row driver 240. In addition, the converted electrical output signal is provided to the correlated double sampler 250 through a vertical signal line.

The timing generator 220 provides a timing signal and a control signal to the row decoder 230 and the column decoder 280.

The row driver 240 provides a plurality of driving signals to the active pixel sensor array 210 for driving a plurality of unit pixels according to the decoded result in the row decoder 230. [ Generally, when unit pixels are arranged in a matrix form, a driving signal is provided for each row.

The correlated dual sampler 250 receives and holds and samples the output signal formed on the active pixel sensor array 210 via the vertical signal line. That is, a specific noise level and a signal level by the output signal are sampled double, and a difference level corresponding to the difference between the noise level and the signal level is output.

The analog-to-digital converter 260 converts the analog signal corresponding to the difference level into a digital signal and outputs the digital signal.

The latch unit 270 latches the digital signal and the latched signal is sequentially output to the image signal processing unit (not shown) according to the decoding result in the column decoder 280.

All the functional blocks shown in FIG. 19 may be composed of one chip or a plurality of chips. For example, the timing generator 220 may be formed of a single chip, and the remaining chips may be formed of a single chip. For example, the described chips may be implemented in a package.

20, a computing device 300 includes a central processing unit (CPU) 320 such as a microprocessor or the like capable of communicating with an input / output (I / O) . Image sensor 310 may communicate with the device via bus 305 or other communication link. The processor-based device 300 may further include a RAM 340 and / or a port 360 that can communicate with the CPU 320 via the bus 305. [ The port 360 may be a port capable of coupling a video card, a sound card, a memory card, a USB device, or the like, or communicating data with another device. The image sensor 310 may be integrated with a CPU, a digital signal processing device (DSP), a microprocessor, or the like. Also, the memories may be integrated together. Of course, in some cases, it may be integrated on a separate chip from the processor.

21A, the camera device 400 includes an image sensor package 410 in which an image sensor 413 is mounted on a circuit board 411 through a bonding wire. A housing 420 is attached on the circuit board 411 and the housing 420 protects the circuit board 411 and the image sensor 413 from the external environment.

A barrel portion 421 through which an image to be imaged passes is formed in the housing 420. A protective cover 422 is provided at an outer end portion facing the outside of the barrel portion 421 and an infrared ray blocking portion 422 is provided at an inner end portion of the barrel portion 421. [ And an anti-reflection filter 423 may be mounted. A lens 424 is mounted in the inside of the barrel section 421 and the lens 424 can be moved along the thread of the barrel section 421.

Referring to FIG. 21B, the camera device 500 uses an image sensor package 501 using a through via 572. With the through vias 572, the image sensor 570 and the circuit board 560 can be electrically connected without using wire bonding. Reference numeral 520, which is not described here, is a first lens, 540 is a second lens, and 526 and 527 are lens components. Reference numeral 505 is a support member, 545 is an aperture, 510 and 530 are transparent substrates, and 550 is glass.

Referring to FIG. 22, an image sensor 452 is attached to a predetermined position of the cellular phone system 450. It is apparent to those skilled in the art that the image sensor 452 may be attached to a portion different from the position shown in Fig.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention.

2 to 12 are views for explaining a method of manufacturing an image sensor according to an embodiment of the present invention.

13 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention.

14 to 18 are views for explaining a method of manufacturing an image sensor according to another embodiment of the present invention.

19 is a diagram for explaining a chip implementing an image sensor according to embodiments of the present invention.

20 to 22 are views for explaining a processor-based apparatus including an image sensor according to embodiments of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS (S)

1: image sensor 110: substrate

126: first metal wiring 132: supporting substrate

142: antireflection film 144: buffer film

152: first passivation film 154: second passivation film

160: contact hole 170: insulating spacer

192: contact 194: pad

196: blocking film 192, 194, 196: conductive film

Claims (26)

Providing a substrate defined by a pad region, an OB region, and a cell region, Forming an insulating structure including a metal wiring on one surface of the substrate, Forming a first passivation film on the other surface of the substrate, Forming a contact hole in the pad region through the first passivation film and the substrate to expose a part of the metal wiring, A contact formed integrally with the pad; and a blocking film formed on the OB region and blocking the OB region at the same height as the pad, And forming the second passivation film on the first passivation film. A semiconductor substrate is provided, Forming an insulating structure including a metal wiring on one surface of the semiconductor substrate, Bonding a supporting substrate to one surface of the substrate, Etching the other surface of the substrate, Forming a first passivation film on the etched second surface of the substrate, Forming a contact hole through the first passivation film and the semiconductor substrate to expose a part of the metal wiring, Forming a conductive pattern including a pad for inputting and outputting an external signal on the first passivation film, Wherein the contact hole and the pad are simultaneously formed in the contact hole, the contact being electrically connected to the conductive pattern and the metal wiring, And performing a first annealing process to remove dangling bonds of the substrate. A semiconductor substrate on which a pad region, an OB region, and a sensing region are defined; An insulating structure including a first metal wiring formed on one surface of the substrate; A contact hole formed in the pad region and penetrating the substrate to expose the first metal interconnection; A pad formed on the other surface of the substrate in the pad region and electrically connected to the first metal interconnection; a contact formed integrally with the pad; and an insulating layer formed on the OB region and the OB region so as to block the OB region at the same height as the pad. A conductive pattern comprising a blocking film formed on the structure; And And a first passivation film formed between the other surface of the substrate and the conductive pattern. The method of claim 3, And a buffer oxide film formed between the other surface of the substrate and the first passivation film so as to cover the whole of the substrate. 5. The method of claim 4, Wherein the first passivation film is formed in the same pattern as the conductive pattern on the buffer oxide film. The method of claim 3, And a second passivation film formed on the conductive pattern. The method according to claim 6, Wherein the second passivation film includes a contact hole that opens at least a portion of the pad. The method according to claim 6, And a buffer oxide film formed between the other surface of the substrate and the first passivation film so as to cover the whole of the substrate. The method according to claim 6, Wherein the first passivation film and the second passivation film are patterned to expose the buffer oxide film of the sensing region. The method of claim 3, Wherein a logic region is further defined in the semiconductor substrate and the blocking film is also formed on the insulating structure of the logic region to block light from entering the logic region. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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