CN111614240A

CN111614240A - Full-bridge IGBT drive circuit and implementation method thereof

Info

Publication number: CN111614240A
Application number: CN202010500180.5A
Authority: CN
Inventors: 崔士军; 张立伟; 徐凯; 刘兰兵
Original assignee: Integrated Electronic Systems Lab Co Ltd
Current assignee: Integrated Electronic Systems Lab Co Ltd
Priority date: 2020-06-04
Filing date: 2020-06-04
Publication date: 2020-09-01
Anticipated expiration: 2040-06-04
Also published as: CN111614240B

Abstract

The invention provides a full-bridge IGBT drive circuit and a realization method thereof, the invention uses two IO interfaces of a CPU as control signals, when the levels of the two control signals are the same, the IGBT drive signal is not output, the full-bridge circuit does not act, when one of the two control signals is lower and the other control signal is higher, the drive signal is output, the full-bridge circuit acts, when the levels of the two control signals are different and are simultaneously turned over, the drive signal is switched, the output voltage of the full-bridge circuit is turned over, and the mutual exclusion problem is solved; the driving ends of driving chips for controlling the two groups of IGBTs for opening and closing are connected in series, and a current limiting resistor is connected in series in a loop, so that the two groups of IGBTs for opening and closing operation are ensured to be simultaneously switched on and off, and the problem of synchronism is solved; the input ends of the two driving chips connected in series are connected with a small-capacity capacitor in parallel, the capacitor and the current-limiting resistor form an RC delay circuit, the delay of a dead zone of opening and closing operation is increased, the immediate opening after closing or the immediate closing after opening is prevented, and the problem of intermittence is solved.

Description

Full-bridge IGBT drive circuit and implementation method thereof

Technical Field

The invention relates to the technical field of full-bridge IGBT driving, in particular to a full-bridge IGBT driving circuit and an implementation method thereof.

Background

In a power distribution network power supply system, the permanent magnet operating mechanism has the advantages of simple structure, high reliability, high action speed and the like, and is applied to more distribution lines. The switching-on and switching-off operations of the monostable permanent magnet operating mechanism share one electromagnetic coil, forward applied direct current voltage is switching-on, reverse applied direct current voltage is switching-off, the power output stage of the conventional driving circuit is a full-bridge circuit consisting of 4 IGBTs, the bus voltage is DC220V or DC380V, as shown in FIG. 1, Q801 and Q804 are simultaneously conducted to be switching-on, and Q803 and Q802 are simultaneously conducted to be switching-off.

The 4 IGBTs in the full-bridge circuit also need a driving circuit, and the driving circuit needs to have three characteristics, wherein the first characteristic is mutual exclusivity, namely opening and closing operations can not be carried out simultaneously, otherwise, the short circuit of bus voltage can be caused, and devices can be burnt out; secondly, synchronism, that is, the on-off of the upper bridge arm IGBT on one side and the lower bridge arm IGBT on the other side are synchronized, as shown in Q801, Q804, Q803 and Q802 in fig. 1, if the on-off is asynchronous, the first conducting tube is CE zero-voltage conducting, and the second conducting tube is CE full-voltage conducting, which increases the on-off loss of the latter, and in the same way, the off-off loss of the last conducting tube is also increased, which is not beneficial to long-term operation; the third is intermittent, after the closing operation is finished, the opening operation can not be immediately carried out within a very short time, because the time is needed for the IGBT device to be in a state from a complete conduction state to a complete disconnection state, if the upper bridge arm is not completely disconnected, the lower bridge arm starts to be conducted, the loss of a tube can be increased, and if the upper bridge arm is not completely disconnected, the lower bridge arm generates heat seriously, and if the upper bridge arm is heavy, the lower bridge arm is damaged. Therefore, the opening and closing operation requires a dead zone interval.

Disclosure of Invention

The invention aims to provide a full-bridge IGBT driving circuit and an implementation method thereof, aims to solve the problem that the IGBT driving circuit in the prior art cannot simultaneously meet mutual exclusion, synchronism and intermittence, and realizes the driving of an IGBT by a low-cost and low-complexity circuit.

In order to achieve the technical purpose, the invention provides a full-bridge IGBT driving circuit, which comprises:

a switching-on drive circuit and a switching-off drive circuit;

the switching-on drive circuit and the switching-off drive circuit are respectively connected with the input end of the driving isolation chip by control signals CPU _ LTRP _ HCLS _ CTR and CPU _ HTRP _ LCLS _ CTR of two different IO interfaces of the singlechip through a current-limiting resistor, when one of the two control signals is low level and the other is high level, the driving signals are output, the full-bridge circuit acts, when the two control signals are different in level and are turned over simultaneously, the driving signals are switched, and the output voltage of the full-bridge circuit is turned over;

the output end of the drive isolation chip is connected with an IGBT control pin;

the two driving isolation chips of the closing driving circuit and the opening driving circuit are connected in series;

the input ends of the two driving isolation chips of the closing driving circuit and the opening driving circuit are connected in parallel with a capacitor, and the capacitor and the current-limiting resistor form a delay circuit.

Preferably, the circuit structure of the closing drive circuit is as follows:

the single-chip IO interface 1 is connected with a resistor R809 through a CPU _ LTRP _ HCLS _ CTR signal line, the other end of the R809 is connected with a 1 st pin of a driving isolation chip U801,

pins

3, 4 and 5 of the U801 are respectively connected with a CLS _ HV-signal end, a CLS _ HO signal end and a CLS _ HV + signal end, capacitors C801 and C802 are connected between the CLS _ HV-signal end and the CLS _ HV + signal end in parallel, and the CLS _ HO signal end is a driving signal output end;

the single-chip IO interface 2 is connected with a resistor R810 through a CPU _ HTRP _ LCLS _ CTR signal line, the other end of the R810 is connected with a No. 2 pin of a driving isolation chip U804,

pins

3, 4 and 5 of the U804 are respectively connected with a DC380V _ C-signal end, a CLS _ LO signal end and a DBR _ LV + signal end, capacitors C804 and C805 are connected between the DC380V _ C-signal end and the DBR _ LV + signal end in parallel, and the CLS _ LO signal end is a driving signal output end;

a capacitor C803 is connected in parallel between the resistor R809 and the resistor R810, and the 2 nd pin of the U801 is connected with the 1 st pin of the U804.

Preferably, the circuit structure of the opening drive circuit is as follows:

the single-chip microcomputer IO interface 1 is further connected with a resistor R812 through a CPU _ LTRP _ HCLS _ CTR signal line, the other end of the R812 is connected with a No. 2 pin of a driving isolation chip U802,

pins

3, 4 and 5 of the U802 are respectively connected with a DC380V _ C-signal end, a TRP _ LO signal end and a DBR _ LV + signal end, capacitors C809 and C810 are connected between the DC380V _ C-signal end and the DBR _ LV + signal end in parallel, and the TRP _ LO signal end is a driving signal output end;

the single-chip IO interface 2 is also connected with a resistor R811 through a CPU _ HTRP _ LCLS _ CTR signal line, the other end of the resistor R811 is connected with a pin 1 of the drive isolation chip U803,

pins

3, 4 and 5 of the U803 are respectively connected with a TRP _ HV-signal end, a TRP _ HO signal end and a TRP _ HV + signal end, capacitors C806 and C807 are connected between the TRP _ HV-signal end and the TRP _ HV + signal end in parallel, and the TRP _ HO signal end is a drive signal output end;

a capacitor C808 is connected in parallel between the resistor R812 and the resistor R811, and the 1 st pin of the U802 is connected with the 2 nd pin of the U803.

Preferably, the selection of the resistance value of the current limiting resistor is related to the amplitude of the CPU driving signal.

Preferably, the capacitance value of the capacitor connected in parallel with the input ends of the two driving isolation chips and the resistance value of the current limiting resistor connected in series jointly determine the opening and closing dead time.

Preferably, the type of the drive isolation chip is PS 9031.

The invention also provides a realization method of the full-bridge IGBT drive circuit, which is characterized by comprising the following operations:

control signals of two different IO interfaces of the single chip microcomputer are respectively connected with a driving isolation chip through a current-limiting resistor, an IGBT control pin is controlled through the output of the driving isolation chip, and when the levels of the two control signals are different, switching-off or switching-on operation is carried out;

connecting two driving isolation chips which need to act simultaneously in series, and synchronizing driving signals output by the two driving isolation chips;

and a capacitor is connected in parallel between the two driving isolation chips, and the opening and closing dead time is controlled through the capacitor and the current-limiting resistor.

The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:

compared with the prior art, the invention uses two IO interfaces of the CPU as control signals at the same time, the IO interfaces have the push-pull output capacity of 20mA current, when the levels of the two control signals are the same, the IGBT drive signal is not output, the full-bridge circuit does not act, when one of the two control signals is lower and the other control signal is higher, the drive signal is output, the full-bridge circuit acts, when the levels of the two control signals are different and are simultaneously turned over, the drive signal is switched, the output voltage of the full-bridge circuit is turned over, and the problem of mutual exclusivity is solved; the driving ends of driving chips for controlling the two groups of IGBTs for opening and closing are connected in series, and a current limiting resistor is connected in series in a loop, so that the two groups of IGBTs for opening and closing operation are ensured to be simultaneously switched on and off, and the problem of synchronism is solved; the input ends of two driving chips connected in series are connected with a small-capacity capacitor in parallel, the capacitor and a current-limiting resistor form an RC delay circuit, the delay of a dead zone of opening and closing operation is increased, the immediate opening after closing is prevented, or the immediate closing after opening is prevented, and the problem of intermittence is solved; the circuit has low cost, simple principle and easy realization, and can be used for full-bridge driving formed by switching devices such as MOSFET or IGBT.

Drawings

Fig. 1 is a structural diagram of a full bridge circuit composed of IGBTs according to an embodiment of the present invention;

fig. 2 is a structural diagram of an IGBT driving circuit provided in an embodiment of the present invention;

fig. 3 is a flowchart of an implementation method of a full-bridge IGBT driving circuit provided in an embodiment of the present invention.

Detailed Description

In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.

The full-bridge IGBT driving circuit and the implementation method thereof according to the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

As shown in fig. 1 and 2, an embodiment of the present invention discloses a full-bridge IGBT driving circuit, including:

a switching-on drive circuit and a switching-off drive circuit;

the input ends of two driving isolation chips of the closing driving circuit and the opening driving circuit are connected in series;

the input ends of the two driving isolation chips of the closing driving circuit and the opening driving circuit are connected in parallel with a capacitor, and the capacitor and the current-limiting resistor form an RC time-delay circuit.

The circuit structure of the switching-on drive circuit is as follows:

pins

The circuit structure of the opening drive circuit is as follows:

pins

The type of the drive isolation chip is PS 9031.

The CPU _ LTRP _ HCLS _ CTR signal line and the CPU _ HTRP _ LCLS _ CTR signal line are connected to two different IO interfaces of the CPU, and the two interfaces have the driving capability of 20mA source current and sink current. When the signal end of the CPU _ LTRP _ HCLS _ CTR is at a high level and the signal end of the CPU _ HTRP _ LCLS _ CTR is at a low level, switching-on operation is carried out; on the contrary, when the signal end of the CPU _ LTRP _ HCLS _ CTR is at a low level and the signal end of the CPU _ HTRP _ LCLS _ CTR is at a high level, the opening operation is carried out; when both are at the high level or at the low level, no operation is performed. Through the design, the opening and closing operations can not be carried out simultaneously, mutual exclusion is realized, and the problem of short circuit caused by simultaneous actions of opening and closing operations is fundamentally solved.

The driving isolation chips U801-U804 respectively control four IGBTs Q801-Q804, and the 4 th pin of the driving isolation chip is a driving signal output end and is respectively connected to the grid driving ends of the corresponding IGBTs through current limiting resistors. Because the driving signals of the two groups of driving isolation chips for respectively controlling the opening and closing are in series connection, the driving currents flowing through the two driving isolation chips are always consistent, have the same magnitude and have the same existence, thereby ensuring the synchronism of the output driving signals and further ensuring the switching synchronism of the two groups of IGBTs for controlling the opening and closing. The resistance value of the current-limiting resistor is related to the amplitude of the CPU driving signal, and if the amplitude of the driving signal is adjusted, the resistance value of the current-limiting resistor can be changed.

The resistors R809, R810, R811 and R812 are current-limiting resistors, the capacitors C803 and C808 are delay capacitors, and the dead zone interval of the opening and closing operation can be adjusted by adjusting the capacitance values of the two capacitors. For example, after completing one closing operation, although the opening circuit does not operate, the capacitor C808 on the opening driving side is reversely charged to a level with an amplitude equal to that of the driving signal, at this time, if the opening operation is immediately performed, the voltage of the capacitor C808 is firstly released, then the capacitor C808 is reversely charged to an operation threshold value on the input side of two driving isolation chips, the IGBT will operate, the opening operation can be executed, the time consumed in the process is the opening and closing dead time, and the intermittent problem is solved through the time interval. The opening and closing dead time can be adjusted according to the actual application requirement, and the RC time constant is calculated according to a formula t (RC), wherein R is the equivalent resistance of the whole loop, and generally about 10uS is taken.

According to the invention, two IO interfaces of a CPU are used as control signals at the same time, the IO interfaces have the push-pull output capacity of 20mA current, when the levels of the two control signals are the same, an IGBT drive signal is not output, a full-bridge circuit does not act, when one of the two control signals is low and the other control signal is high, the drive signal is output, the full-bridge circuit acts, when the two different control signals are both overturned, the drive signal is switched, and the output voltage of the full-bridge circuit is overturned, so that the mutual exclusion problem is solved; the driving ends of driving chips for controlling the two groups of IGBTs for opening and closing are connected in series, and current limiting resistors are connected in series in a loop, so that the two groups of IGBTs for opening and closing operation are ensured to be simultaneously switched on and off, and the problem of synchronism is solved; the input ends of two driving chips connected in series are connected with a small-capacity capacitor in parallel, the capacitor and a current-limiting resistor form an RC delay circuit, the delay of a dead zone of opening and closing operation is increased, and the phenomenon that the brake is opened immediately after closing or closed immediately after opening is avoided, so that the problem of intermittence is solved.

The circuit of the invention has low cost, simple principle and easy realization, and can be used for full-bridge driving formed by switching devices such as MOSFET or IGBT.

As shown in fig. 3, an embodiment of the present invention further discloses a method for implementing the full-bridge IGBT driving circuit, where the method includes the following operations:

The driving isolation chips U801-U804 respectively control four IGBTs Q801-Q804, and the 4 th pin of the driving isolation chip is a driving signal output end and is respectively connected to the grid driving ends of the corresponding IGBTs through current limiting resistors. Because the driving signals of the two groups of driving isolation chips for respectively controlling the opening and closing are in series connection, the driving currents flowing through the two driving isolation chips are always consistent, have the same magnitude and have the same existence, thereby ensuring the synchronism of the output driving signals and further ensuring the switching synchronism of the two groups of IGBTs for controlling the opening and closing.

The resistors R809, R810, R811 and R812 are current-limiting resistors, the capacitors C803 and C808 are delay capacitors, and the dead zone interval of the opening and closing operation can be adjusted by adjusting the capacitance values of the two capacitors. For example, after completing one closing operation, although the opening circuit does not operate, the capacitor C808 on the opening driving side is reversely charged to a level with an amplitude equal to that of the driving signal, at this time, if the opening operation is immediately performed, the voltage of the capacitor C808 is firstly released, then the capacitor C808 is reversely charged to an operation threshold value on the input side of two driving isolation chips, the IGBT will operate, the opening operation can be executed, the time consumed in the process is the opening and closing dead time, and the intermittent problem is solved through the time interval.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A full-bridge IGBT drive circuit, characterized in that the drive circuit comprises:

a switching-on drive circuit and a switching-off drive circuit;

2. The full-bridge IGBT drive circuit according to claim 1, wherein the circuit structure of the switching-on drive circuit is as follows:

the single-chip IO interface 1 is connected with a resistor R809 through a CPU _ LTRP _ HCLS _ CTR signal line, the other end of the R809 is connected with a 1 st pin of a driving isolation chip U801, pins 3, 4 and 5 of the U801 are respectively connected with a CLS _ HV-signal end, a CLS _ HO signal end and a CLS _ HV + signal end, capacitors C801 and C802 are connected between the CLS _ HV-signal end and the CLS _ HV + signal end in parallel, and the CLS _ HO signal end is a driving signal output end;

the single-chip IO interface 2 is connected with a resistor R810 through a CPU _ HTRP _ LCLS _ CTR signal line, the other end of the R810 is connected with a No. 2 pin of a driving isolation chip U804, pins 3, 4 and 5 of the U804 are respectively connected with a DC380V _ C-signal end, a CLS _ LO signal end and a DBR _ LV + signal end, capacitors C804 and C805 are connected between the DC380V _ C-signal end and the DBR _ LV + signal end in parallel, and the CLS _ LO signal end is a driving signal output end;

3. The full-bridge IGBT drive circuit according to claim 1, wherein the circuit structure of the opening drive circuit is as follows:

the single-chip microcomputer IO interface 1 is further connected with a resistor R812 through a CPU _ LTRP _ HCLS _ CTR signal line, the other end of the R812 is connected with a No. 2 pin of a driving isolation chip U802, pins 3, 4 and 5 of the U802 are respectively connected with a DC380V _ C-signal end, a TRP _ LO signal end and a DBR _ LV + signal end, capacitors C809 and C810 are connected between the DC380V _ C-signal end and the DBR _ LV + signal end in parallel, and the TRP _ LO signal end is a driving signal output end;

the single-chip IO interface 2 is also connected with a resistor R811 through a CPU _ HTRP _ LCLS _ CTR signal line, the other end of the resistor R811 is connected with a pin 1 of the drive isolation chip U803, pins 3, 4 and 5 of the U803 are respectively connected with a TRP _ HV-signal end, a TRP _ HO signal end and a TRP _ HV + signal end, capacitors C806 and C807 are connected between the TRP _ HV-signal end and the TRP _ HV + signal end in parallel, and the TRP _ HO signal end is a drive signal output end;

4. The full-bridge IGBT drive circuit according to claim 1, wherein the selection of the resistance value of the current limiting resistor is related to the amplitude of the CPU drive signal.

5. The full-bridge IGBT drive circuit according to claim 1, wherein the capacitance value of the capacitor connected in parallel with the input ends of the two drive isolation chips and the resistance value of the current limiting resistor connected in series determine the switching-on and switching-off dead time.

6. The full-bridge IGBT drive circuit according to claim 1, wherein the drive isolation chip is PS 9031.

7. A method for implementing a full-bridge IGBT driving circuit according to any one of claims 1-6, characterized in that the method comprises the following operations: