CN111613534B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN111613534B
CN111613534B CN201910142892.1A CN201910142892A CN111613534B CN 111613534 B CN111613534 B CN 111613534B CN 201910142892 A CN201910142892 A CN 201910142892A CN 111613534 B CN111613534 B CN 111613534B
Authority
CN
China
Prior art keywords
region
gate structure
gate
layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910142892.1A
Other languages
Chinese (zh)
Other versions
CN111613534A (en
Inventor
王潇
田志娟
孔云龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201910142892.1A priority Critical patent/CN111613534B/en
Publication of CN111613534A publication Critical patent/CN111613534A/en
Application granted granted Critical
Publication of CN111613534B publication Critical patent/CN111613534B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method of forming the same, the method of forming includes providing a semiconductor substrate having a first region, a second region, and an isolation region, the second region being separated from the isolation region by the first region; a gate structure is formed on the semiconductor substrate, the gate structure spans the first region and the second region, and a width of the gate structure at a portion of the first region is greater than a width at a portion of the second region. The junction of the active region and the isolation structure of the semiconductor device often generates larger stress, so that a channel effect occurs; the first region is a region on the active region, the channel effect is easy to occur, the width of the gate structure at the position is changed, the channel length of the first region is longer, and the longer channel length prevents the source electrode from being communicated with the drain electrode, so that the device failure caused by electric leakage cannot occur.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are currently widely used as the most basic semiconductor devices, but during the testing of the transistors, channel effects (pipeline defects) occur in the transistors, which cause leakage between the source and drain on the devices, and thus cause transistor failure, particularly on NMOS structures where electrostatic discharge (ESD) is repeated over a large area, which frequently occurs.
In the prior art, when manufacturing a semiconductor device, the stress is reduced by adjusting the thickness of a mask layer during ion implantation and tempering process or Shallow Trench Isolation (STI) etching, so as to eliminate the channel effect.
However, the atomic number of the element doped into the NMOS is larger, the ion implantation energy is higher, the damage to the Active Area (AA) is larger, and sometimes the damage can not be completely eliminated even though tempering is carried out; in addition, the whole structure area is large, and a large-area mask layer is deposited when shallow trench isolation etching is performed on the active region, so that even if the thickness of the mask layer is adjusted, large stress exists at two ends of the active region; these factors add up and, due to the damage of the active region and the presence of stress, the two ends of the semiconductor device still generate a channel effect (pipeline defect), causing the semiconductor device to fail.
Disclosure of Invention
The invention solves the problem of providing a method for forming a semiconductor structure, which improves the performance of the formed semiconductor structure and reduces the occurrence of failure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising a semiconductor substrate, wherein the semiconductor substrate has a first region, a second region and an isolation region, and the second region is separated from the isolation region by the first region; a gate structure is formed on the semiconductor substrate, the gate structure spans the first region and the second region, and a width of the gate structure at a portion of the first region is greater than a width at a portion of the second region.
Optionally, the ratio of the width of the gate structure at the first region to the width of the gate structure at the second region is 1.5-3.
Optionally, in a direction parallel to the extension direction of the gate structure, a length value of the gate structure at the first region portion is 1 to 2 times a width value at the second region portion.
Optionally, forming the gate structure includes: forming a gate dielectric layer on the surface of the semiconductor substrate; forming a gate electrode layer on the surface of the gate dielectric layer; forming a patterned photoresist layer on the gate electrode layer; and etching the gate electrode layer and the gate dielectric layer by taking the patterned photoresist layer as a mask until the semiconductor substrate layer is exposed, so as to form the gate electrode structure.
Optionally, forming the patterned photoresist layer includes: a first patterned photoresist layer and a second patterned photoresist layer are formed.
Optionally, etching the gate layer and the gate dielectric layer with the first patterned photoresist layer as a mask until the semiconductor substrate layer is exposed, so as to form a gate structure located at the second region; and etching the gate electrode layer and the gate dielectric layer by taking the second graphical photoresist layer as a mask until the semiconductor substrate layer is exposed, so as to form a gate electrode structure positioned at the first region part.
Optionally, the first patterned photoresist layer and the second patterned photoresist layer are formed simultaneously.
Optionally, the first patterned photoresist layer and the second patterned photoresist layer are formed step by step.
Optionally, the gate structures adjacent to the first region are connected or disconnected in the width direction.
Optionally, after forming the gate structure on the semiconductor substrate, forming source-drain doped regions in the semiconductor substrate at two sides of the gate structure.
The invention also provides a semiconductor structure, comprising: a semiconductor substrate having a first region, a second region, and an isolation region, the second region being separated from the isolation region by the first region; and a gate structure spanning the first region and the second region, and having a greater width in the first region than in the second region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
a gate structure is formed on the semiconductor substrate, the gate structure spans the first region and the second region, and a width of the gate structure at a portion of the first region is greater than a width at a portion of the second region. The junction of the active region and the isolation structure of the semiconductor device often generates larger stress, so that a channel effect occurs; the first region is a region on the active region, the channel effect is easy to occur, the width of the gate structure at the position is made to be long, the channel length of the first region is enabled to be longer, the longer channel length is used for avoiding the situation that the source electrode and the drain electrode are communicated together, and therefore the device failure caused by electric leakage cannot occur.
Drawings
Fig. 1 to 5 are schematic views illustrating a gate structure forming process according to an embodiment of the invention;
FIG. 6 is a schematic top view of a gate structure (forming multiple gates) according to an embodiment of the present invention;
fig. 7 is a schematic top view of a gate structure (forming a plurality of gates) according to another embodiment of the present invention.
Detailed Description
As described in the background art, during testing of semiconductor devices, a channel effect (tunnel defect) is often generated, and this channel effect may cause leakage between the source and the drain on the device, thereby causing the transistor to fail.
Through researches, the metal oxide semiconductor device, particularly an NMOS device, has larger atomic number of elements doped into the NMOS, higher ion implantation energy and larger damage to an Active Area (AA), and sometimes the damage cannot be completely eliminated even though the damage is tempered; in addition, when the active region is subjected to various processes, a large-area mask layer deposited on the surface of the active region is covered on the active region, the mask layer can cause interfacial tension, and the surface of the active region is pulled, in particular, larger stress can be generated at two ends of the active region; particularly when the material of the mask layer is silicon nitride (SiN), the compactness of the silicon nitride is high, which leads to a large interfacial tension. At present, when a semiconductor device is manufactured, the ion implantation energy is adjusted, and after tempering technology and Shallow Trench Isolation (STI) etching, the thickness of a mask layer is adjusted to reduce stress, but the channel effect is not eliminated fundamentally, the probability of occurrence of the channel effect is only reduced, or the penetration degree of a channel is reduced to some extent, and the same type of failure still occurs when a CP test is performed.
Through researches, the stress at two ends of the semiconductor device is too large, and the channel length (channel length) of the semiconductor device is short, so that the source electrode and the drain electrode are easily communicated, a channel is formed, and electric leakage is formed. In order to solve the technical problem, the channel lengths at two ends of the semiconductor device are long, so that even if the channel effect occurs here, the source and the drain cannot be communicated together due to the long channel. Thus, failure of the device due to leakage cannot occur.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 5 are schematic diagrams illustrating a gate structure forming process according to an embodiment of the invention.
Referring to fig. 1 and 2, fig. 2 is a cross-sectional view along AA1 in fig. 1, providing a semiconductor substrate 100, the semiconductor substrate 100 having a first region 101, a second region 102, and an isolation region 103, the second region 102 being separated from the isolation region 103 by the first region 101.
In this embodiment, the semiconductor substrate 100 is a silicon substrate. In other embodiments, the material of the semiconductor substrate 100 may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the first region 101 and the second region 102 are active regions, and semiconductor device structures are formed on the active regions, the first region 101 is located at two ends of the second region 102, and two ends of the first region 101 are respectively the second region 102 and the isolation region 103.
Fig. 3 is a schematic structural view of forming a gate structure on the semiconductor substrate 100, fig. 4 is a cross-sectional view along the direction BB1 in fig. 3, and fig. 5 is a cross-sectional view along the direction CC1 in fig. 3.
Referring to fig. 3 and 4, a gate structure is formed on the semiconductor substrate 100, and the forming process of the gate structure is as follows:
firstly forming the gate dielectric layer 11 on the surface of the semiconductor substrate 100, and then forming the gate layer 12 on the surface of the gate dielectric layer 11; forming a patterned photoresist layer 13 on the gate electrode layer 12; the gate electrode layer 12 and the gate dielectric layer 11 are etched using the patterned photoresist layer 13 as a mask until the surface of the semiconductor substrate 100 is exposed, thereby forming the gate structure 10 (refer to fig. 4 and 5).
The gate structure 10 spans the first region 101 and the second region 102, and a portion of the gate structure 10 located in the first region 101 has a greater width than a portion located in the second region 102.
In this embodiment, the gate structure 10 includes a gate dielectric layer 11 and a gate layer 12, and the gate structure 10 is used to control the on/off of a channel of the formed semiconductor device.
The gate dielectric layer 11 may be made of silicon oxide or silicon oxynitride. In this embodiment, the gate dielectric layer 11 is made of silicon oxide.
The material of the gate layer 12 may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon, and in this embodiment, the material of the gate layer 12 is polysilicon.
A photoresist layer is formed on the surface of the gate electrode layer 12, and a dynamic spraying mode is adopted to form the photoresist layer, so that a more uniform photoresist film is obtained. In other embodiments, static glue application may be used.
Exposing and developing the photoresist layer; the patterned photoresist layer 13 is formed. And etching by taking the patterned photoresist layer 13 as a mask layer to form the gate structure 10, wherein the gate structure 10 is formed by overlapping the etched gate dielectric layer 11 and the gate layer 12.
In this embodiment, etchingThe process may be a dry etching process. The gas includes an etching gas and a carrier gas, the etching gas including CF 4 、CHF 3 、CH 2 F 2 、CH 3 F, wherein the carrier gas is hydrogen, nitrogen or inert gas.
In other embodiments, the gate structure 10 may also be a single layer structure, i.e., the gate structure includes only the gate layer 12. The gate structure 10 is formed by: forming the gate layer 12 on the surface of the semiconductor substrate 100; forming a patterned photoresist layer 13 on the gate electrode layer 12; and etching the gate layer 12 by using the patterned photoresist layer 13 as a mask until the surface of the semiconductor substrate layer 100 is exposed, thereby forming a plurality of gate structures 10.
In this embodiment, forming the patterned photoresist layer 13 includes: a first patterned photoresist layer and a second patterned photoresist layer are formed. The first patterned photoresist layer is located in the second region 102; the second patterned photoresist layer is located in the first region.
Etching the gate layer 12 and the gate dielectric layer 11 with the first patterned photoresist layer as a mask until the surface of the semiconductor substrate layer 100 is exposed, so as to form a gate structure located in the second region; etching the gate layer 12 and the gate dielectric layer 11 with the second patterned photoresist layer as a mask until the semiconductor substrate layer 100 is exposed, so as to form a gate structure located in the first region; and etching the gate structure positioned in the second area part to have a narrower width than that of the gate structure positioned in the first area part.
In this embodiment, the ratio of the width of the gate structure located in the first region 101 to the width of the gate structure located in the second region 102 is 1.5-3. When the ratio is in the range, the problem of source-drain power-on short circuit caused by channel effect at two ends of the semiconductor device can be solved, and the characteristics of the large-area device can not be influenced. When the ratio exceeds 3, the width of the gate structure at the first region 101 is too large, resulting in reduced control capability of the gate structure, which affects the basic performance of a large-area device; when the ratio is lower than 1.5, the function of preventing the source drain from penetrating and avoiding the failure of the device caused by the channel effect is weakened. In this embodiment, the first patterned photoresist layer and the second patterned photoresist layer are formed simultaneously. When the first patterned photoresist layer and the second patterned photoresist layer are formed simultaneously, the gate dielectric layer 11 and the gate electrode layer 12 are etched to form the gate structure 10 by using the first patterned photoresist layer and the second patterned photoresist layer as masks.
In other embodiments, the first patterned photoresist layer and the second patterned photoresist layer are formed in steps. Specifically, the first patterned photoresist layer may be formed first, and then the second patterned photoresist layer may be formed; alternatively, the second patterned photoresist layer may be formed first, and then the first patterned photoresist layer may be formed.
The etching steps when the first patterned photoresist layer is formed first and then the second patterned photoresist layer is formed are as follows: forming the first patterned photoresist layer, and etching the gate dielectric layer and the gate layer which are positioned in the second region 102 by taking the first patterned photoresist layer as a mask until the surface of the semiconductor substrate 100 positioned in the second region 102 is exposed, so as to form a gate structure positioned in the second region 102; and forming the second patterned photoresist layer, and etching the gate dielectric layer and the gate electrode layer which are positioned in the first region 101 by taking the second patterned photoresist layer as a mask until the surface of the semiconductor substrate 100 positioned in the second region 101 is exposed, so as to form a gate electrode structure positioned in the first region 101.
When the second patterned photoresist layer is formed first, the etching step when the first patterned photoresist layer is formed is as follows: forming a second patterned photoresist layer, and etching the gate dielectric layer and the gate electrode layer which are positioned in the first region 101 by taking the second patterned photoresist layer as a mask until the surface of the semiconductor substrate 100 positioned in the second region 101 is exposed, so as to form a gate electrode structure positioned in the first region 101; and forming the first patterned photoresist layer, and etching the gate dielectric layer and the gate layer which are positioned in the second region 102 by taking the first patterned photoresist layer as a mask until the surface of the semiconductor substrate 100 positioned in the second region 102 is exposed, so as to form a gate structure positioned in the second region 102.
Fig. 6 is a schematic top view of a gate structure (forming a plurality of gates) according to an embodiment of the invention.
Referring to fig. 6, adjacent gate structures located at the first region 101 are connected in the width direction. As can be seen from the above, the width of the gate structure at the portion of the first region 101 is wider than the width of the gate structure at the portion of the second region 102; when the distance between two adjacent gate structures 10 is within a certain range, the gate structures located in the first region 101 are connected.
Fig. 7 is a schematic top view of a gate structure (forming a plurality of gates) according to another embodiment of the present invention.
Referring to fig. 7, adjacent gate structures located at the first region 101 are not connected in the width direction.
In this embodiment, in the extending direction parallel to the gate structure 10, the length of the portion of the gate structure 10 located in the first region 101 is 1 to 2 times the width of the portion located in the second region 102. The gate structure 10 spans the first region 101 and the second region 102 to be an extending direction of the gate structure, and a width direction of the gate structure 10 is perpendicular to the extending direction of the gate structure 10.
In the prior art, in order to ensure the control force of a grid structure on a channel in a semiconductor device, the length of the channel is designed to be short, and the design is a main reason that when the channel effect occurs, the source electrode and the drain electrode can be communicated; on the semiconductor device, the gate structure 10 is located at two ends, that is, at a portion of the gate structure in the first region 101, where the channel effect is likely to occur. It is desirable to avoid the source-drain penetration when the channel effect occurs, that is, to avoid the source-drain penetration at the position where the channel effect is likely to occur.
In the embodiment of the present invention, the gate structure 10 is designed to be widened only in the first region 101, so that even if the channel effect occurs due to the longer channel length, the source and the drain cannot be penetrated together, thereby avoiding the short circuit and failure. When the length value of the gate structure located in the first region 101 exceeds 2 times the width value of the gate structure located in the second region 102 in the extending direction of the gate structure 10, the widened region of the gate structure 10 is too large, and the control capability of the gate structure 10 to the channel is weakened, which affects the performance of the whole semiconductor device; when the length of the gate structure in the portion of the first region 101 is shorter than the width of the gate structure in the portion of the second region 102, the region where the channel effect is likely to occur cannot be effectively covered, and when the channel effect occurs, the width of the gate structure in the region is not widened, so that the source drain penetration caused by the channel effect cannot be effectively avoided.
In this embodiment, a mask layer is formed on the semiconductor substrate before the gate structure is formed, so as to form the isolation region 103.
The mask layer is made of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or the like, and in this embodiment, the mask layer is made of silicon nitride. The mask layer has larger stress and high compactness, and the semiconductor substrate is covered with the mask layer, so that interfacial tension exists, and the interface is pulled to generate stress. Particularly after the silicon nitride cap, a significant stress is created at the interface of the active region and the isolation region. In this case, the thickness of the mask layer is adjusted to reduce the stress on the interface of the active region and improve the performance of the semiconductor device.
The isolation region 103 is used as an isolation structure of a semiconductor device and is used for isolating adjacent devices, and the material of the isolation region 103 is silicon oxide. In other embodiments, the material of the isolation region 103 may also be silicon nitride or silicon oxynitride.
In this embodiment, the gate structure 10 passes through the junction between the active region and the isolation region 103, and the gate structure width at the junction and extending to the isolation region 103 is widened, i.e. the gate structure width at the junction and extending to the isolation region 103 is greater than the gate structure width at the second region. In other embodiments, the gate structure extending to the portion of the isolation region 103 has a width equal to the width of the gate structure in the second region.
In this embodiment, a sidewall is formed on the side of the gate structure 10. The side wall material is composed of a nitride layer material. After the side walls are formed, source-drain doped regions 20 are formed in the semiconductor substrate at two sides of the gate structure 10.
With continued reference to fig. 6 and 7, the present invention provides a semiconductor structure, including a semiconductor substrate, the semiconductor substrate having a first region 101, a second region 102 and an isolation region 103, wherein the first region 101 and the second region 102 are active regions of a device, and the second region 102 is separated from the isolation region 103 by the first region 101; also included is a gate structure 10, the gate structure 10 spanning the first region 101 and the second region 102, and the gate structure 10 having a greater width in the portion of the first region 101 than in the portion of the second region 102.
The semiconductor structure further includes source and drain doped regions 20 located in the substrate on either side of the gate structure 10.
In the invention, the width of the portion of the gate structure 10 located in the first region 101 is larger than the width of the portion of the gate structure located in the second region 102, so that the situation that the source electrode and the drain electrode of the portion of the first region 101 are communicated and short-circuited when channel effect occurs is avoided on the premise that the control capability of the gate structure 10 on the device is not affected, the probability of failure of the device is reduced, and the electrical performance of the semiconductor device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (9)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first region, a second region and an isolation region, and the second region is separated from the isolation region through the first region;
forming a gate structure on the semiconductor substrate, wherein the gate structure spans the first area and the second area, and the width of the gate structure at the first area is larger than that of the gate structure at the second area so as to solve the problem of source-drain power-on short circuit caused by channel effect at two ends of the semiconductor structure;
the ratio of the width of the gate structure at the first area part to the width of the gate structure at the second area part is 1.5-3;
the length of the gate structure at the first region portion is 1 to 2 times the width of the gate structure at the second region portion in a direction parallel to the extending direction of the gate structure.
2. The method of forming a semiconductor structure of claim 1, wherein forming the gate structure comprises:
forming a gate dielectric layer on the surface of the semiconductor substrate;
forming a gate electrode layer on the surface of the gate dielectric layer;
forming a patterned photoresist layer on the gate electrode layer;
and etching the gate electrode layer and the gate dielectric layer by taking the patterned photoresist layer as a mask until the semiconductor substrate layer is exposed, so as to form the gate electrode structure.
3. The method of forming a semiconductor structure of claim 2, wherein forming the patterned photoresist layer comprises: a first patterned photoresist layer and a second patterned photoresist layer are formed.
4. The method of claim 3, wherein etching the gate layer and the gate dielectric layer using the first patterned photoresist layer as a mask until the semiconductor substrate layer is exposed forms a gate structure in the second region portion;
and etching the gate electrode layer and the gate dielectric layer by taking the second graphical photoresist layer as a mask until the semiconductor substrate layer is exposed, so as to form a gate electrode structure positioned at the first region part.
5. The method of claim 3, wherein the first patterned photoresist layer and the second patterned photoresist layer are formed simultaneously.
6. The method of claim 3, wherein the first patterned photoresist layer and the second patterned photoresist layer are formed in steps.
7. The method of forming a semiconductor structure of claim 1, wherein gate structures adjacent to the first region are connected or disconnected in a width direction.
8. The method of forming a semiconductor structure of claim 1, further comprising, after forming a gate structure on the semiconductor substrate, forming source-drain doped regions in the semiconductor substrate on both sides of the gate structure.
9. A structure of a semiconductor, comprising:
a semiconductor substrate having a first region, a second region, and an isolation region, the second region being separated from the isolation region by the first region;
the gate structure spans the first area and the second area, and the width of the gate structure at the first area is larger than that of the gate structure at the second area so as to solve the problem of source-drain electrifying short circuit caused by channel effect at two ends of the semiconductor structure;
the ratio of the width of the gate structure at the first area part to the width of the gate structure at the second area part is 1.5-3;
the length of the gate structure at the first region portion is 1 to 2 times the width of the gate structure at the second region portion in a direction parallel to the extending direction of the gate structure.
CN201910142892.1A 2019-02-26 2019-02-26 Semiconductor structure and forming method thereof Active CN111613534B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910142892.1A CN111613534B (en) 2019-02-26 2019-02-26 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910142892.1A CN111613534B (en) 2019-02-26 2019-02-26 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN111613534A CN111613534A (en) 2020-09-01
CN111613534B true CN111613534B (en) 2024-03-22

Family

ID=72201387

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910142892.1A Active CN111613534B (en) 2019-02-26 2019-02-26 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN111613534B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1316781A (en) * 2000-04-04 2001-10-10 夏普公司 Silicon insulator structure semiconductor device
CN1855542A (en) * 2005-03-30 2006-11-01 台湾积体电路制造股份有限公司 Quasi-plannar and finfet-like transistors on bulk silicon and manufacturing method thereof
CN1983631A (en) * 2005-12-13 2007-06-20 上海华虹Nec电子有限公司 MOS field effective pipe and its production
CN102034831A (en) * 2009-09-28 2011-04-27 中芯国际集成电路制造(上海)有限公司 Circle stacking grid fin type field-effect transistor memory device and forming method thereof
CN104240762A (en) * 2013-06-09 2014-12-24 中芯国际集成电路制造(上海)有限公司 Antifuse structure and programming method
CN104465760A (en) * 2013-09-13 2015-03-25 株式会社东芝 Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4044276B2 (en) * 2000-09-28 2008-02-06 株式会社東芝 Semiconductor device and manufacturing method thereof
US7323389B2 (en) * 2005-07-27 2008-01-29 Freescale Semiconductor, Inc. Method of forming a FINFET structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1316781A (en) * 2000-04-04 2001-10-10 夏普公司 Silicon insulator structure semiconductor device
CN1855542A (en) * 2005-03-30 2006-11-01 台湾积体电路制造股份有限公司 Quasi-plannar and finfet-like transistors on bulk silicon and manufacturing method thereof
CN1983631A (en) * 2005-12-13 2007-06-20 上海华虹Nec电子有限公司 MOS field effective pipe and its production
CN102034831A (en) * 2009-09-28 2011-04-27 中芯国际集成电路制造(上海)有限公司 Circle stacking grid fin type field-effect transistor memory device and forming method thereof
CN104240762A (en) * 2013-06-09 2014-12-24 中芯国际集成电路制造(上海)有限公司 Antifuse structure and programming method
CN104465760A (en) * 2013-09-13 2015-03-25 株式会社东芝 Semiconductor device

Also Published As

Publication number Publication date
CN111613534A (en) 2020-09-01

Similar Documents

Publication Publication Date Title
US7476941B2 (en) Semiconductor integrated circuit device and fabrication process thereof
US7244643B2 (en) Semiconductor device and manufacturing method thereof
US20200203479A1 (en) Semiconductor apparatus and manufacturing method for same
JPH1167927A (en) Semiconductor device and its manufacture
KR970004484B1 (en) Fabrication method of ldd mosfet
US6136657A (en) Method for fabricating a semiconductor device having different gate oxide layers
US20070290208A1 (en) Semiconductor device and manufacturing method thereof
US8021956B2 (en) Ultrathin SOI CMOS devices employing differential STI liners
US20110284935A1 (en) Semiconductor device and method for manufacturing the same
KR20050071156A (en) Method for fabricating gate spacer of semiconductor device
CN111613534B (en) Semiconductor structure and forming method thereof
CN110660808B (en) Memory structure and manufacturing method thereof
US20200127013A1 (en) Dummy gate isolation and method of production thereof
US8232152B2 (en) Removing method of a hard mask
CN118315344B (en) Method for forming semiconductor device
KR100772272B1 (en) Method for manufacturing mosfet on semiconductor device
CN109841527B (en) Semiconductor structure and forming method thereof
KR100685541B1 (en) Method for forming semiconductor device
KR20070002661A (en) Method for forming transistor of semiconductor device
US20110309424A1 (en) Structure of memory device and process for fabricting the same
CN112652531A (en) Method for forming semiconductor device
KR100873018B1 (en) Method for fabricating semiconductor device with recess gate
KR101012438B1 (en) Method of manufacturing semiconductor device
KR20050093160A (en) Method for manufacturing merged semiconductor device
KR20050010239A (en) Method for forming a silicide layer in semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant