CN110660808B - Memory structure and manufacturing method thereof - Google Patents
Memory structure and manufacturing method thereof Download PDFInfo
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- CN110660808B CN110660808B CN201810688042.7A CN201810688042A CN110660808B CN 110660808 B CN110660808 B CN 110660808B CN 201810688042 A CN201810688042 A CN 201810688042A CN 110660808 B CN110660808 B CN 110660808B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 96
- 229920005591 polysilicon Polymers 0.000 claims abstract description 83
- 238000007667 floating Methods 0.000 claims abstract description 74
- 230000000903 blocking effect Effects 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000002347 injection Methods 0.000 claims abstract description 13
- 239000007924 injection Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- Engineering & Computer Science (AREA)
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- Non-Volatile Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
The invention relates to a memory structure and a manufacturing method thereof, wherein a high-voltage device area of the memory structure comprises a substrate and a grid structure on the substrate, the grid structure comprises a high-voltage area floating gate, a high-voltage area polysilicon gate covering the high-voltage area floating gate and an insulating layer arranged between the high-voltage area floating gate and the high-voltage area polysilicon gate, at least part of the top of the high-voltage area floating gate is not provided with the insulating layer, so that the high-voltage area floating gate is communicated with the high-voltage area polysilicon gate at the position without the insulating layer, and the high-voltage device area also comprises lightly doped drain electrodes positioned in the substrate and at two sides below the high-voltage area floating gate. The invention reserves the floating gate structure of the high-voltage region in the high-voltage device region, and increases the thickness of the polysilicon for blocking LDD injection by overlapping the high-voltage region floating gate on the high-voltage region floating gate, thereby preventing the LDD injection from penetrating the polysilicon to be driven into a conductive channel.
Description
Technical Field
The present invention relates to the fabrication of semiconductor devices, and more particularly, to a memory structure and a method of fabricating a memory structure.
Background
In an Embedded FLASH (SST) of an SST (Silicon Storage Technology), as the line width of a Logic core device (Logic core device) is continuously reduced, the space (space) between polysilicon gates is also continuously reduced. In order to meet the subsequent filling requirement, the thickness of the polysilicon needs to be continuously reduced to avoid the deterioration of the filling effect caused by the increase of the aspect ratio.
However, in this way, a problem is encountered with the devices in the High Voltage (HV) region of the memory: in order to meet the requirement of high breakdown voltage of a high-voltage device, high implantation energy is needed during lightly doped drain implantation (HV LDD) of a high-voltage device region, but the high implantation energy HV LDD can break down a thinned polysilicon gate of a high-voltage region, so that punch-through leakage between a source and a drain is caused.
Therefore, for the situation that the polysilicon gate is thinned to the thickness that causes punch-through leakage by HV LDD implantation, a machine with better filling capability is generally required to be equipped, but this will lead to cost increase.
Disclosure of Invention
In view of the above, there is a need for a method of fabricating a memory structure that can meet the fill requirement without the polysilicon gate being broken down by HV LDD implantation.
A method of fabricating a memory structure, the memory structure comprising a logic region and a high voltage device region, the method comprising: step A, obtaining a wafer with a first polycrystalline silicon layer formed on a substrate; step B, forming a first etching barrier structure positioned on the first polycrystalline silicon layer in the high-voltage device area; step C, etching the first polysilicon layer to form a high-voltage region floating gate under the protection of the first etching barrier structure; step D, photoetching and etching the first etching blocking structure to expose at least part of the top of the floating gate of the high-voltage area; step E, forming a second polycrystalline silicon layer on the substrate, the high-voltage area floating gate and the first etching blocking structure; step F, photoetching and etching the second polysilicon layer to form a high-voltage area polysilicon gate and a logic area polysilicon gate, wherein the high-voltage area polysilicon gate covers two sides and the top surface of the high-voltage area floating gate, and the high-voltage area polysilicon gate is communicated with the high-voltage area floating gate to obtain the same potential as the high-voltage area floating gate; and carrying out lightly doped drain injection on the high-voltage device area.
In one embodiment, a step of forming an insulating layer on the substrate, the high-voltage area floating gate and the first etching barrier structure is further included between the step C and the step D, and the insulating layer at the corresponding position is etched and removed when the step D etches the first etching barrier structure.
In one embodiment, the method further includes, between the step a and the step B, the steps of: forming a hard mask on the first polysilicon layer; and photoetching and etching the hard mask, and removing the hard mask at the position where the first etching blocking structure is required to be formed.
In one embodiment, in the step B, silicon oxide is formed at the position where the hard mask is removed to serve as the first etching stop structure, and then the remaining hard mask is removed.
In one embodiment, the hard mask is made of silicon nitride.
In one embodiment, the wafer obtained in step a further has a gate oxide layer formed between the substrate and the first polysilicon layer.
In one embodiment, the memory structure further includes a cell region, the step B further includes forming a second etching blocking structure located on the first polysilicon layer in the cell region, the step C forms a cell region floating gate under the protection of the second etching blocking structure after etching, the step F forms a cell region polysilicon gate after etching, and one end of the cell region polysilicon gate is lapped on the second etching blocking structure.
The manufacturing method of the memory structure forms the high-voltage region floating gate structure of the high-voltage device region in the manufacturing process on the basis of the prior manufacturing process, and increases the thickness of the polycrystalline silicon for blocking LDD injection by overlapping the high-voltage region polycrystalline silicon gate on the high-voltage region floating gate, thereby preventing the LDD injection from penetrating the polycrystalline silicon to be driven into a conductive channel. And the high-voltage region polysilicon gate and the logic region polysilicon gate are formed in the same step, the thickness of the logic region polysilicon gate can be kept unchanged, and the filling requirement can be met on the premise of not upgrading a filling machine.
It is also desirable to provide a memory structure.
A memory structure comprises a high-voltage device area, wherein the high-voltage device area comprises a substrate and a grid structure on the substrate, the grid structure comprises a high-voltage area floating gate, a high-voltage area polysilicon gate covering the high-voltage area floating gate and an insulating layer arranged between the high-voltage area floating gate and the high-voltage area polysilicon gate, the insulating layer is not arranged in at least partial area of the top of the high-voltage area floating gate, so that the high-voltage area floating gate is communicated with the high-voltage area polysilicon gate at the position where the insulating layer is not arranged, and the high-voltage device area further comprises lightly doped drain electrodes which are positioned in the substrate and on two sides below the high-voltage area floating gate.
In one embodiment, the high voltage device region further includes a first etching blocking structure, the first etching blocking structure is arranged between the high voltage region floating gate and the insulating layer on the top of the high voltage region floating gate, and the high voltage region polysilicon gate is communicated with the high voltage region floating gate at a position where the first etching blocking structure is not arranged.
In one embodiment, the cell etching device further comprises a logic area and a cell area, wherein the logic area comprises a logic area polysilicon gate, the cell area comprises a cell area floating gate, a cell area polysilicon gate and a second etching blocking structure on the cell area floating gate, and one end of the cell area polysilicon gate is lapped on the second etching blocking structure.
According to the memory structure, the high-voltage region floating gate structure is reserved in the high-voltage device region, and the high-voltage region polycrystalline silicon gate is overlapped on the high-voltage region floating gate, so that the thickness of polycrystalline silicon for blocking LDD injection is increased, and the LDD injection is prevented from penetrating the polycrystalline silicon and being driven into a conducting channel.
Drawings
FIG. 1 is a flow chart of a method of fabricating a memory structure according to one embodiment;
fig. 2 a-2 i are schematic cross-sectional views of a device in the process of manufacturing a memory using the method of manufacturing a memory structure in one embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1 is a flow chart of a method for manufacturing a memory structure in an embodiment, where the memory structure is a SST architecture flash memory in the present embodiment. The manufacturing method of the memory structure comprises the following steps:
s110, a wafer with a first polycrystalline silicon layer formed on the substrate is obtained.
In this embodiment, a gate oxide layer is further formed between the first polysilicon layer and the substrate. In one embodiment, the substrate may be a silicon substrate, and the gate oxide layer is made of silicon oxide, such as silicon dioxide.
And S120, forming a first etching blocking structure on the first polycrystalline silicon layer in the high-voltage device (HV) area.
Referring to fig. 2c, in this embodiment, a gate oxide layer 20 is formed on a substrate 10, a first polysilicon layer 30 is formed on the gate oxide layer 20, and a first etch stop structure 52 is formed on the first polysilicon layer.
S130, etching the first polysilicon layer so as to form a high-voltage region floating gate under the protection of the first etching blocking structure.
Referring to fig. 2d, the first polysilicon layer 30 without the protection of the etch stop structure is etched away, and the polysilicon remaining under the first etch stop structure 52 serves as the high-voltage region floating gate 32.
S140, photoetching and etching the first etching blocking structure to expose at least part of the top of the floating gate in the high-voltage area.
In the present embodiment, since the gate oxide layer 20 is thin, it is removed together in the etching of step S130 (except for the gate oxide layer under the etching stop structure, such as the high voltage gate oxide 22, see fig. 2 d), so an insulating layer (in the present embodiment, an insulating oxide layer) is formed again after step S130, see fig. 2e. The insulating layer also covers the first etching stop structure 52, so that when the first etching stop structure 52 is etched, the insulating layer at the corresponding position (i.e. the position where the photoresist is opened) is etched and removed together, as shown in fig. 2f. In one embodiment, the insulating layer is made of silicon oxide, such as silicon dioxide.
S150, forming a second polysilicon layer on the substrate, the high-voltage region floating gate and the first etching blocking structure.
Referring to fig. 2g, in this embodiment, a second polysilicon layer 60 is deposited on the wafer surface.
And S160, photoetching and etching the second polysilicon layer to form a high-voltage area polysilicon gate and a logic area polysilicon gate.
Referring to fig. 2h, the remaining portion of the second polysilicon layer 60 after etching is referred to as a high-voltage polysilicon gate 62, and the remaining portion of the Logic (Logic) region is referred to as a Logic polysilicon gate 66. High-voltage region polysilicon gate 62 covers both sides and the top surface of high-voltage region floating gate 32. Since the floating gate is not required in the high voltage region in this embodiment, the high voltage region floating gate 32 and the high voltage region floating gate 62 are connected to obtain the same potential, and the high voltage region floating gate 32 and the high voltage region floating gate 62 are used together as a gate, so that the high voltage region floating gate 32 does not actually serve as a floating gate. Since the purpose of etching the first etching stopper 52 in step S140 is to enable the high-voltage region polysilicon gate 62 to communicate with the high-voltage region floating gate 32, in step S140, only one opening (as shown in fig. 2 f) may be opened on the first etching stopper 52, or the first etching stopper 52 may be completely removed.
And S170, carrying out lightly doped drain injection on the high-voltage device area.
Referring to fig. 2i, in the present embodiment, an implantation barrier layer is formed to limit the implanted region when performing the lightly doped drain implantation.
The manufacturing method of the memory structure forms a high-voltage region floating gate structure of a high-voltage device region in the manufacturing process on the basis of the prior manufacturing process, and increases the thickness of polysilicon for blocking LDD injection by overlapping the high-voltage region floating gate 62 on the high-voltage region floating gate 32, thereby preventing the LDD injection from penetrating the polysilicon to be driven into a conductive channel. And the high-voltage region polysilicon gate 62 and the logic region polysilicon gate 66 are formed in the same step, the thickness of the logic region polysilicon gate 66 can be kept unchanged, and the filling requirement of the space between the logic region polysilicon gates 66 can be met on the premise of not upgrading the filling machine.
In one embodiment, the first etch stop structure 52 is formed by:
referring to fig. 2a, a hard mask 40 is deposited on the first polysilicon layer 30, and then the hard mask 40 is etched by photolithography, and the hard mask is removed at the position where the first etching stop structure 52 is to be formed, thereby forming an opening 41. Silicon oxide is then formed at the removed openings 41 as first etch stop structures 52, see fig. 2b, after which the remaining hard mask 40 is removed again (first etch stop structures 52 remain). In one embodiment, the first etch stop structure 52 is a field oxide layer. In one embodiment, the hard mask is made of silicon nitride.
In one embodiment, the memory structure further includes a Cell (Cell) region. Step S120 further includes forming a second etch stop structure on the first polysilicon layer in the cell region. Referring specifically to fig. 2a, an opening 43 is also formed when etching the hard mask 40, so that a second etch stop structure 54 is also formed at the opening 43 when forming the first etch stop structure 52, see fig. 2b. Thus, the cell floating gates 34 (and the cell gate oxide 24) are formed under the protection of the second etch stop structure 54 during the etching in step S130. The cell region polysilicon gate 64 is also formed after the photolithography and etching of step S160. One end of the polysilicon gate 64 of the cell region is lapped over the second etch stop structure 54, and the other end extends to the insulating layer on the substrate 10.
The invention also provides a memory structure correspondingly. In one embodiment, the memory structure is a flash memory of SST architecture, divided into a high voltage device (HV) region, a Logic (Logic) region, and a Cell (Cell) region. Referring to fig. 2h, the memory structure includes a substrate 10 on which a gate structure is disposed, wherein the gate structure of the high voltage device region includes a high voltage region floating gate 32, a high voltage region polysilicon gate 62 covering the high voltage region floating gate 32, and an insulating layer 21 disposed between the high voltage region floating gate 32 and the high voltage region polysilicon gate 62. The insulating layer 21 is not provided on at least a part of the upper surface of the high-voltage floating gate 32, so that the high-voltage floating gate 32 and the high-voltage polysilicon gate 62 communicate with each other at a position where the insulating layer 21 is not provided. The high voltage device region also includes lightly doped drains (not shown in fig. 2 h) in the substrate 10 on both sides under the floating gate 32 of the high voltage region.
In the memory structure, a high-voltage region floating gate structure is reserved in a high-voltage device region, and the high-voltage region floating gate 62 is overlapped on the high-voltage region floating gate 32, so that the thickness of polysilicon for blocking LDD injection is increased, and the LDD injection is prevented from penetrating through the polysilicon and being driven into a conducting channel.
In the embodiment shown in fig. 2h, the high voltage device region further comprises a first etch stop structure 52. The first etch stop structure 52 is disposed between the high voltage region floating gate 32 and the insulating layer 21 on top of the high voltage region floating gate 32, and the high voltage region polysilicon gate 62 is in communication with the high voltage region floating gate 32 at a location where the first etch stop structure 52 is not disposed.
In the embodiment shown in fig. 2h, the logic region includes a logic region polysilicon gate 66, the cell region includes a cell region floating gate 34, a cell region polysilicon gate 64, and a second etching stop structure 54 on the cell region floating gate 34, one end of the cell region polysilicon gate 64 is lapped on the second etching stop structure 54, and the other end extends to the insulating layer on the substrate 10. In the embodiment shown in fig. 2h, a gate oxide layer is formed on the substrate 10, and the logic region polysilicon gate 66 and the cell region polysilicon gate 64 are disposed on the gate oxide layer. In one embodiment, the insulating layer 21, the gate oxide layer, the first etching stop structure 52 and the second etching stop structure 54 are all made of silicon oxide, such as silicon dioxide.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (4)
1. A method of fabricating a memory structure, the memory structure including a logic region and a high voltage device region, the method comprising:
step A, obtaining a wafer with a first polycrystalline silicon layer formed on a substrate;
step B, forming a first etching barrier structure positioned on the first polycrystalline silicon layer in the high-voltage device area;
step C, etching the first polysilicon layer to form a high-voltage region floating gate under the protection of the first etching barrier structure;
step D, photoetching and etching the first etching blocking structure to expose at least part of the top of the floating gate of the high-voltage area;
step E, forming a second polysilicon layer on the substrate, the high-voltage area floating gate and the first etching barrier structure;
step F, photoetching and etching the second polysilicon layer to form a high-voltage area polysilicon gate and a logic area polysilicon gate, wherein the high-voltage area polysilicon gate covers two sides and the top surface of the high-voltage area floating gate, the high-voltage area polysilicon gate is communicated with the high-voltage area floating gate to obtain the same potential as the high-voltage area floating gate, and the high-voltage area floating gate and the high-voltage area polysilicon gate are jointly used as a high-voltage area gate;
carrying out lightly doped drain injection on the high-voltage device region;
a step of forming an insulating layer on the substrate, the high-voltage region floating gate and the first etching blocking structure is further included between the step C and the step D, the insulating layer at the corresponding position is etched and removed when the first etching blocking structure is etched in the step D, the high-voltage region polysilicon gates at two sides of the high-voltage region floating gate are positioned on the insulating layer at two sides of the high-voltage region floating gate, and the insulating layer on the substrate of the logic region is used as a gate dielectric layer of the logic region polysilicon gate;
the method also comprises the following steps between the step A and the step B:
forming a hard mask on the first polysilicon layer;
photoetching and etching the hard mask, and removing the hard mask at the position where the first etching blocking structure is required to be formed;
and step B, forming silicon oxide at the position where the hard mask is removed to serve as the first etching blocking structure, and then removing the residual hard mask.
2. The method of claim 1, wherein the hard mask is made of silicon nitride.
3. The method for manufacturing the memory structure according to claim 1, wherein the wafer obtained in the step A is further formed with a gate oxide layer between the substrate and the first polysilicon layer.
4. The method of claim 1, wherein the memory structure further comprises a cell region, the step B further comprises forming a second etching blocking structure on the first polysilicon layer in the cell region, the step C forms a cell region floating gate under the protection of the second etching blocking structure after etching, the step F forms a cell region polysilicon gate after etching, and one end of the cell region polysilicon gate is lapped on the second etching blocking structure.
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| CN115241047B (en) * | 2021-04-23 | 2024-09-13 | 长鑫存储技术有限公司 | Method for preparing semiconductor structure |
| US12068158B2 (en) | 2021-04-23 | 2024-08-20 | Changxin Memory Technologies, Inc. | Method for fabricating semiconductor structure |
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|---|---|---|---|---|
| US4780431A (en) * | 1986-07-25 | 1988-10-25 | Sgs Microellettronica S.P.A. | Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors |
| CN1577869A (en) * | 2003-07-14 | 2005-02-09 | 三星电子株式会社 | Eeprom device having selecting transistors and method of fabricating the same |
| CN104752361A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN107316868A (en) * | 2016-04-22 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
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| CN105336695B (en) * | 2014-05-29 | 2018-06-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4780431A (en) * | 1986-07-25 | 1988-10-25 | Sgs Microellettronica S.P.A. | Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors |
| CN1577869A (en) * | 2003-07-14 | 2005-02-09 | 三星电子株式会社 | Eeprom device having selecting transistors and method of fabricating the same |
| CN104752361A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN107316868A (en) * | 2016-04-22 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
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