CN115274858A - LDMOS device, manufacturing method of LDMOS device and chip - Google Patents

LDMOS device, manufacturing method of LDMOS device and chip Download PDF

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Publication number
CN115274858A
CN115274858A CN202211205608.9A CN202211205608A CN115274858A CN 115274858 A CN115274858 A CN 115274858A CN 202211205608 A CN202211205608 A CN 202211205608A CN 115274858 A CN115274858 A CN 115274858A
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semiconductor substrate
drain electrode
metal
region
ldmos device
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CN202211205608.9A
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CN115274858B (en
Inventor
余山
赵东艳
陈燕宁
付振
刘芳
王帅鹏
王凯
吴波
邓永峰
刘倩倩
郁文
张同
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure

Abstract

The invention provides an LDMOS device, a manufacturing method of the LDMOS device and a chip, and belongs to the field of chips. The LDMOS device comprises: the semiconductor device comprises a semiconductor substrate, and a source electrode structure, a grid electrode structure and a drain electrode structure which are formed on the semiconductor substrate; a drift region and a body region are formed in the semiconductor substrate, and a gate structure is formed between the source structure and the drain structure; the source electrode structure comprises a source electrode doped region and source electrode metal, the source electrode doped region is formed in the body region and is away from the upper surface of the semiconductor substrate by a first preset distance, and the source electrode metal is connected with the source electrode doped region; the drain electrode structure comprises a drain electrode doped region and drain electrode metal, the drain electrode doped region is formed in the drift region and is away from the upper surface of the semiconductor substrate by a first preset distance, and the drain electrode metal is connected with the drain electrode doped region; and a low-K dielectric layer is also formed above the source electrode doped region and the drain electrode doped region and surrounds the source electrode metal and the drain electrode metal.

Description

LDMOS device, manufacturing method of LDMOS device and chip
Technical Field
The invention relates to the field of chips, belongs to the field of power semiconductor chips, and particularly relates to an LDMOS device, a manufacturing method of the LDMOS device and a chip.
Background
With the development of the times, the application fields of semiconductors have also been expanded from traditional industrial control, communication, computers, consumer electronics to new fields such as new energy, smart grid, rail transit, automotive electronics, and the like. The power semiconductor device pursues the handling of electric energy, and is required to have high withstand voltage and large current characteristics itself. As a Lateral power device, an LDMOS (Lateral Double-Diffused MOSFET) has the advantages of high withstand voltage, large gain, good linearity, high efficiency, good broadband matching performance, and the like, and is widely applied to power integrated circuits, especially low-power and high-frequency circuits.
Typically, the LDMOSFET has a large operating voltage and current. When the LDMOSFET is conducted, an electric field of a drain end in a channel direction is strong, so that the breakdown voltage BVon during conduction is influenced, and meanwhile, because a large amount of electrons flow through a high electric field area, a hot electron effect is easily caused, so that the reliability of the LDMOSFET is influenced.
Disclosure of Invention
The LDMOS device adopts low-K dielectric material to partially fill the upper part of a drain electrode doping region, and is equivalent to using drain electrode metal as a side field plate, so that the electric field of a drain end is reduced, and the breakdown voltage is improved.
In order to achieve the above object, a first aspect of the present invention provides an LDMOS device comprising: the semiconductor device comprises a semiconductor substrate, and a source electrode structure, a grid electrode structure and a drain electrode structure which are formed on the semiconductor substrate; a drift region and a body region are formed in the semiconductor substrate, the source electrode structure is connected with the body region, the drain electrode structure is connected with the drift region, and the gate electrode structure is formed between the source electrode structure and the drain electrode structure; the source electrode structure comprises a source electrode doped region and source electrode metal, the source electrode doped region is formed in the body region and is a first preset distance away from the upper surface of the semiconductor substrate, and the source electrode metal is connected with the source electrode doped region; the drain structure comprises a drain doped region and drain metal, the drain doped region is formed in the drift region and is away from the upper surface of the semiconductor substrate by a first preset distance, and the drain metal is connected with the drain doped region; and a low-K dielectric layer is also formed above the source electrode doped region and the drain electrode doped region and surrounds the source electrode metal and the drain electrode metal. The drain electrode doping region is implanted into the drift region for a first preset distance and is not positioned on the surface of the drift region, so that electrons on the surface are scattered when reaching the drain electrode doping region, and the phenomenon that the current is concentrated to cause impact ionization to generate a hot electron effect is reduced.
Optionally, the LDMOS device further includes a silicon dioxide layer formed on the semiconductor substrate to cover a region outside the source structure, the gate structure, and the drain structure.
Optionally, the LDMOS device further includes an interlayer dielectric layer formed above the silicon dioxide layer.
Optionally, the LDMOS device further includes a guard ring structure; the guard ring structure comprises a guard ring doping area and guard ring metal, the guard ring doping area is formed in the semiconductor substrate and is a first preset distance away from the upper surface of the semiconductor substrate, and the guard ring metal penetrates through the silicon dioxide layer and the interlayer dielectric layer to be connected with the guard ring doping area.
Optionally, the LDMOS device further includes a shallow trench isolation structure formed in the semiconductor substrate; the shallow trench isolation structure comprises a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure and the second shallow trench isolation structure are respectively arranged on two sides of the protection ring doping area, one end of the first shallow trench isolation structure is located in the drift area and adjacent to the drain electrode structure, and the other end of the first shallow trench isolation structure is located outside the drift area.
Optionally, the gate structure includes a gate oxide layer, a gate field plate and a polysilicon gate; the gate oxide layer is formed between the drain electrode structure and the source electrode structure, the second end of the gate oxide layer is positioned above the drift region, and the first end of the gate oxide layer is positioned above the body region; the polycrystalline silicon gate forms grid oxide top and first end with the first end of gate oxide flushes, the second end with the distance is predetermine at the second end interval of gate oxide, the gate field board forms the polycrystalline silicon gate with between the gate oxide, and one end is located drift region top, the other end with the second end of gate oxide flushes.
Optionally, the LDMOS device further includes a high voltage P-well and a high voltage N-well formed in the semiconductor substrate; the drift region and the body region are formed in the high-voltage N well; one end of the second shallow trench isolation structure is formed in the high-voltage N well, and the other end of the second shallow trench isolation structure is adjacent to the high-voltage P well; and a preset distance is arranged between the high-voltage P trap and the high-voltage N trap.
In a second aspect, the present invention provides a method for manufacturing an LDMOS device, the method comprising:
forming a drift region and a body region in the semiconductor substrate by adopting an ion implantation process;
depositing a silicon dioxide material on the surface of the semiconductor substrate, photoetching and etching the silicon dioxide material and the semiconductor substrate, and forming a pit at the corresponding position of the defined source electrode doped region and drain electrode doped region, wherein the bottom surface of the pit is away from the upper surface of the semiconductor substrate by a first preset distance;
forming a source electrode doped region and a drain electrode doped region in the semiconductor substrate at the corresponding positions of the pits by adopting an ion implantation process;
preparing a gate structure over a semiconductor substrate;
depositing a low-K dielectric material, etching the low-K dielectric material by a dry method, and reserving the low-K dielectric material filled in the filling pit;
depositing an interlayer dielectric material, photoetching and etching the interlayer dielectric material and the low-K dielectric material to form a contact hole;
and depositing a metal material, and photoetching and etching the metal material to form a source metal and a drain metal. The LDMOS device manufactured by the method is implanted into the drift region for a first preset distance and is not on the surface of the drift region, so that electrons on the surface are diffused when reaching the drain doped region, the phenomenon that the electrons collide and ionize due to current concentration to generate a thermionic effect is reduced, and low-K dielectric materials are partially filled above the drain doped region, which is equivalent to the phenomenon that drain metal is used as a side field plate, so that the electric field of a drain end is reduced, and the breakdown voltage is improved.
Optionally, before forming the drift region and the body region, the method further includes: and forming a high-voltage P well and a high-voltage N well in the semiconductor substrate by adopting an ion implantation process.
Optionally, the method further includes: and before depositing a silicon dioxide material on the surface of the semiconductor substrate, manufacturing a shallow trench isolation structure on the semiconductor substrate.
Optionally, the method includes: adopting the same manufacturing steps to form a protection ring doping area while forming a source doping area and a drain doping area;
and forming a guard ring metal while forming the source metal and the drain metal by using the same metal material and manufacturing steps.
The third aspect of the invention provides a chip, which is made by applying the LDMOS device.
According to the technical scheme, the LDMOS device, the manufacturing method and the chip are provided, the drain electrode doping region of the LDMOS device is implanted into the drift region for a first preset distance and is not arranged on the surface of the drift region, electrons on the surface are diffused when reaching the drain electrode doping region, the phenomenon that the electrons collide and ionize due to the concentration of current to generate a thermionic effect is reduced, and low-K dielectric materials are partially filled above the drain electrode doping region, so that the drain electrode metal is used as a side field plate, the electric field of a drain end is reduced, and the breakdown voltage is improved.
Additional features and advantages of embodiments of the present invention will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention and do not limit the embodiments. In the drawings:
fig. 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for manufacturing an LDMOS device according to an embodiment of the invention;
fig. 3A is a schematic structural diagram of an LDMOS device manufacturing method according to an embodiment of the invention after forming a high-voltage P-well, a high-voltage N-well, a drift region, and a body region;
fig. 3B is a schematic structural diagram of a method for manufacturing an LDMOS device according to an embodiment of the present invention after a shallow trench isolation structure is formed;
fig. 3C is a schematic structural diagram of an LDMOS device manufacturing method according to an embodiment of the invention after forming a source doped region and a drain doped region;
fig. 3D is a schematic structural diagram of an LDMOS device according to an embodiment of the invention after a gate structure is fabricated;
fig. 3E is a schematic structural diagram of an LDMOS device according to an embodiment of the invention after an interlayer dielectric material is deposited.
Description of the reference numerals
The field effect transistor comprises a semiconductor substrate 1, a high-voltage N well 2, a drift region 3, a body region 4, a source electrode doped region 5, a drain electrode doped region 6, a guard ring doped region 7, a low-K dielectric layer 8, a polysilicon gate 9, an interlayer dielectric layer 10, a silicon dioxide layer 11, source electrode metal 12, drain electrode metal 13, guard ring metal 14, a high-voltage P well 15, a shallow trench isolation structure 16, a gate oxide 17 and a gate field plate 18.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Example one
Fig. 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the invention. As shown in fig. 1, the LDMOS device includes: the semiconductor device comprises a semiconductor substrate 1, and a source electrode structure, a grid electrode structure and a drain electrode structure which are formed on the semiconductor substrate 1; a drift region 3 and a body region 4 are formed in the semiconductor substrate 1, the source structure is connected with the body region 4, the drain structure is connected with the drift region 3, and the gate structure is formed between the source structure and the drain structure; the source electrode structure comprises a source electrode doping region 5 and source electrode metal 12, wherein the source electrode doping region 5 is formed in the body region 4 and is away from the upper surface of the semiconductor substrate 1 by a first preset distance, and the source electrode metal 12 is connected with the source electrode doping region 5; the drain structure comprises a drain doped region 6 and drain metal 13, the drain doped region 6 is formed in the drift region 3 and is away from the upper surface of the semiconductor substrate 1 by a first preset distance, and the drain metal 13 is connected with the drain doped region 6; a low-K dielectric layer 8 is further formed above the source doped region 5 and the drain doped region 6, and the low-K dielectric layer 8 surrounds the source metal 12 and the drain metal 13. The drain electrode doping region is implanted into the drift region 3 for a first preset distance and is not positioned on the surface of the drift region 3, so that electrons on the surface are scattered when reaching the drain electrode doping region, and the phenomenon that the current is concentrated to cause collision ionization to generate a hot electron effect is reduced.
In the present embodiment, the LDMOS device further includes a silicon dioxide layer 11, and the silicon dioxide layer 11 is formed on the semiconductor substrate 1 to cover the region outside the source structure, the gate structure, and the drain structure.
In this embodiment, the LDMOS device further includes an interlayer dielectric layer 10, and the interlayer dielectric layer 10 is formed above the silicon dioxide layer.
In this embodiment, the LDMOS device further includes a guard ring structure; the guard ring structure comprises a guard ring doping area 7 and guard ring metal 14, wherein the guard ring doping area 7 is formed in the semiconductor substrate 1 and is away from the upper surface of the semiconductor substrate 1 by a first preset distance, and the guard ring metal 14 penetrates through the silicon dioxide layer 11 and the interlayer dielectric layer 10 to be connected with the guard ring doping area 7.
In the present embodiment, the LDMOS device further includes a shallow trench isolation structure 16, where the shallow trench isolation structure 16 is formed in the semiconductor substrate 1; the shallow trench isolation structure 16 includes a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure and the second shallow trench isolation structure are respectively disposed on two sides of the protection ring doping region 7, one end of the first shallow trench isolation structure is located in the drift region 3 and adjacent to the drain structure, and the other end of the first shallow trench isolation structure is located outside the drift region 3.
In the present embodiment, the gate structure includes a gate oxide layer 17, a gate field plate 18 and a polysilicon gate 9; the gate oxide layer 17 is formed between the drain structure and the source structure, the second end of the gate oxide layer 17 is positioned above the drift region 3, and the first end is positioned above the body region 4; polycrystalline silicon gate 9 forms gate oxide 17 top and first end with gate oxide 17's first end flushes, the second end with gate oxide 17's second end interval is predetermine the distance, gate field board 18 forms polycrystalline silicon gate 9 with between the gate oxide 17, and one end is located drift region 3 top, the other end with gate oxide 17's second end flushes.
In this embodiment, the LDMOS device further includes a high voltage P-well 15 and a high voltage N-well 2 formed in the semiconductor substrate 1, and the drift region 3 and the body region 4 are formed in the high voltage N-well 2; one end of the second shallow trench isolation structure is formed in the high-voltage N well 2, and the other end of the second shallow trench isolation structure is adjacent to the high-voltage P well 15; the high-voltage P trap 15 and the high-voltage N trap 2 are separated by a preset distance.
In another aspect, the present invention provides a method for manufacturing an LDMOS device, where the method is used to manufacture the LDMOS device, as shown in fig. 2, and the method includes:
s1: a high-voltage P well 15, a high-voltage N well 2, a drift region 3 and a body region 4 are formed in the semiconductor substrate 1 by adopting an ion implantation process.
In some embodiments, in order to form the high voltage P-well 15, the high voltage N-well 2, the drift region 3 and the body region 4, a thin silicon dioxide layer is first oxidized over the semiconductor substrate 1, then a photoresist is coated, developed by light, the photoresist in the corresponding regions of the high voltage P-well 15 and the high voltage N-well 2 is removed, the remaining photoresist is used as a mask in the ion implantation process, then P-type or N-type ion implantation is selected according to the type of the LDMOS device, the photoresist is removed, the drift region 3 and the body region 4 are manufactured by the same process, and the manufactured structure is as shown in fig. 3A. In one embodiment, P-type ions are implanted to form P-type body regions 4 and N-type ions are implanted to form N-type drift regions 3.
S2: and manufacturing a shallow trench isolation structure 16 on the semiconductor substrate 1.
In some embodiments, a thin layer of silicon dioxide SiO is first thermally oxidized 2 Then CVD SiN, photoetching to expose the region corresponding to STI, dry etching SiN, siO 2 And a semiconductor substrate 1, photoresist removed, thermally oxidized silicon-induced damage by a dry etch, HDP CVD SiO 2 Excess SiO on the CMP surface 2 Wet removal of SiN and its underlying thin SiO 2 And (5) annealing at high temperature to finish the manufacturing of the shallow trench isolation structure, wherein the manufactured structure is shown as figure 3B.
S3: depositing a silicon dioxide material on the surface of the semiconductor substrate 1, photoetching and etching the silicon dioxide material and the semiconductor substrate 1, and forming a pit at the corresponding position of the defined source electrode doped region 5 and drain electrode doped region 6, wherein the bottom surface of the pit is away from the upper surface of the semiconductor substrate 1 by a first preset distance.
In some embodiments, a layer of silicon dioxide is thermally oxidized on the surface of the semiconductor substrate 1, then a CVD silicon dioxide material is formed, then a photoresist is coated, a photo-etching process is performed, the photoresist in the region corresponding to the source doped region 5 and the drain doped region 6 is removed, the remaining photoresist is used as a mask in a subsequent etching process, then the silicon dioxide material and the semiconductor substrate 1 are dry-etched, that is, the silicon dioxide material is etched to penetrate through, and simultaneously a portion of the semiconductor substrate 1 is etched, and a pit is formed in the etched structure at the position corresponding to the source doped region 5 and the drain doped region 6, wherein the bottom surface of the pit is a first preset distance away from the surface of the semiconductor substrate 1. In the present application, the first predetermined distance is specifically designed according to parameters of the LDMOS device to be manufactured.
S4: and forming a source doped region 5 and a drain doped region 6 in the semiconductor substrate 1 at the corresponding positions of the pits by adopting an ion implantation process. The photoresist in step S3 also plays a role of a mask in the ion implantation process of S4, so that the material is saved, the photoresist is also removed and the high temperature is promoted after the ion implantation, and the drain doping region 6 and the source doping region 5 after the fabrication have the same structure as the drain doping region 6 and the source doping region 5 shown in fig. 3C. The fabrication of the guard ring is also included in fig. 3C.
S5: a gate structure is prepared over a semiconductor substrate 1.
In some embodiments, a photoresist is first coated on the structure in step S4, then photolithography is performed to expose a silicon dioxide material corresponding to the gate structure, then the silicon dioxide material is dry-etched, photoresist is removed, a gate oxide layer 17 is fabricated by gate oxidation, then LPCVD Polysilicon (Polysilicon) is subjected to ion implantation to heavily dope the Polysilicon, polysilicon is photo-etched, polysilicon is dry-etched, photoresist is removed, and a gate structure is fabricated, where the fabricated structure is as shown in fig. 3D.
S6: depositing a low-K dielectric material, and dry etching the low-K dielectric material to reserve the low-K dielectric material filled in the pit.
In some embodiments, PECVD is used to prepare a low-K dielectric material, which usually comprises SiO2 as a main component and has a dielectric constant of 1.5 to 2.5.
S7: depositing an interlayer dielectric material, photoetching and etching the interlayer dielectric material and the low-K dielectric material to form a contact hole, wherein the structure after the interlayer dielectric material is deposited is shown as a figure 3E;
s8: a metal material is deposited, and the metal material is etched by photolithography to form a source metal 12 and a drain metal 13.
In some embodiments, the metallic material is deposited using PVD techniques; and dry etching the metal material.
The LDMOS device manufactured by the method is implanted into the drift region 3 for a first preset distance and is not on the surface of the drift region 3, so that electrons on the surface are diffused when reaching the drain doped region, the phenomenon that the electrons on the surface are concentrated to cause impact ionization to generate a thermionic effect is reduced, and low-K dielectric materials are partially filled above the drain doped region 6, which is equivalent to the phenomenon that drain metal is used as a side field plate, so that the electric field of a drain end is reduced, and the breakdown voltage is improved.
Optionally, the method includes: adopting the same manufacturing steps, forming a guard ring doped region 7 while forming a source doped region 5 and a drain doped region 6;
the same metal material and manufacturing steps are used to form the guard ring metal 14 at the same time as the source metal 12 and the drain metal 13. The guard ring metal 14, the source electrode metal 12 and the drain electrode metal 13 are made of the same material on the same layer, so that the process is simplified, and the cost is saved.
The third aspect of the invention provides a chip, which is made by applying the LDMOS device.
On the other hand, the manufacturing method provided by the invention has the advantages of simple process, compatibility with the existing process and strong practicability.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should be noted that the various features described in the foregoing embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.

Claims (12)

1. An LDMOS device comprising: the semiconductor device comprises a semiconductor substrate, and a source electrode structure, a grid electrode structure and a drain electrode structure which are formed on the semiconductor substrate; a drift region and a body region are formed in the semiconductor substrate, the source electrode structure is connected with the body region, the drain electrode structure is connected with the drift region, and the gate electrode structure is formed between the source electrode structure and the drain electrode structure; the source structure is characterized by comprising a source doped region and source metal, wherein the source doped region is formed in the body region and is away from the upper surface of the semiconductor substrate by a first preset distance, and the source metal is connected with the source doped region; the drain electrode structure comprises a drain electrode doped region and drain electrode metal, the drain electrode doped region is formed in the drift region and is away from the upper surface of the semiconductor substrate by a first preset distance, and the drain electrode metal is connected with the drain electrode doped region;
and a low-K dielectric layer is also formed above the source electrode doped region and the drain electrode doped region and surrounds the source electrode metal and the drain electrode metal.
2. The LDMOS device set forth in claim 1 further including a silicon dioxide layer formed on said semiconductor substrate overlying a region other than said source, gate and drain structures.
3. The LDMOS device of claim 2, further comprising an interlevel dielectric layer formed over the silicon dioxide layer.
4. The LDMOS device of claim 3, further comprising a guard ring structure; the protection ring structure comprises a protection ring doping area and protection ring metal, the protection ring doping area is formed in the semiconductor substrate and is a first preset distance away from the upper surface of the semiconductor substrate, and the protection ring metal penetrates through the silicon dioxide layer and the interlayer dielectric layer to be connected with the protection ring doping area.
5. The LDMOS device of claim 4, further comprising a shallow trench isolation structure formed within the semiconductor substrate; the shallow trench isolation structure comprises a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure and the second shallow trench isolation structure are respectively arranged on two sides of the protection ring doping area, one end of the first shallow trench isolation structure is located in the drift area and adjacent to the drain electrode structure, and the other end of the first shallow trench isolation structure is located outside the drift area.
6. The LDMOS device of claim 1, wherein said gate structure includes a gate oxide layer, a gate field plate and a polysilicon gate; the gate oxide layer is formed between the drain electrode structure and the source electrode structure, the second end of the gate oxide layer is positioned above the drift region, and the first end of the gate oxide layer is positioned above the body region; the polycrystalline silicon gate forms grid oxide top and first end with the first end of gate oxide flushes, the second end with the distance is predetermine at the second end interval of gate oxide, the gate field board forms the polycrystalline silicon gate with between the gate oxide, and one end is located drift region top, the other end with the second end of gate oxide flushes.
7. The LDMOS device of claim 5, further comprising a high-voltage P-well and a high-voltage N-well formed within the semiconductor substrate, the drift region and the body region being formed within the high-voltage N-well; one end of the second shallow trench isolation structure is formed in the high-voltage N well, and the other end of the second shallow trench isolation structure is adjacent to the high-voltage P well; and a preset distance is arranged between the high-voltage P trap and the high-voltage N trap.
8. A method of fabricating an LDMOS device, the method being for fabricating the LDMOS device of any one of claims 3-7, the method comprising:
forming a drift region and a body region in the semiconductor substrate by adopting an ion implantation process;
depositing a silicon dioxide material on the surface of the semiconductor substrate, photoetching and etching the silicon dioxide material and the semiconductor substrate, and forming a pit at the corresponding position of the defined source electrode doping area and drain electrode doping area, wherein the bottom surface of the pit is away from the upper surface of the semiconductor substrate by a first preset distance;
forming a source electrode doped region and a drain electrode doped region in the semiconductor substrate at the corresponding positions of the pits by adopting an ion implantation process;
preparing a gate structure over a semiconductor substrate;
depositing a low-K dielectric material, etching the low-K dielectric material by a dry method, and reserving the low-K dielectric material filled in the pit;
depositing an interlayer dielectric material, photoetching and etching the interlayer dielectric material and the low-K dielectric material to form a contact hole;
and depositing a metal material, and photoetching and etching the metal material to form a source metal and a drain metal.
9. The method of fabricating an LDMOS device set forth in claim 8 wherein prior to forming the drift region and the body region, the method further comprises: and forming a high-voltage P well and a high-voltage N well in the semiconductor substrate by adopting an ion implantation process.
10. The method of fabricating an LDMOS device set forth in claim 8 further comprising: before depositing silicon dioxide material on the surface of the semiconductor substrate, a shallow trench isolation structure is manufactured on the semiconductor substrate.
11. The method of manufacturing the LDMOS device of claim 8, comprising: adopting the same manufacturing steps to form a source electrode doped region and a drain electrode doped region and simultaneously form a protection ring doped region;
and forming a guard ring metal while forming the source metal and the drain metal by using the same metal material and manufacturing steps.
12. A chip made using the LDMOS device of any one of claims 1 to 7.
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TW202017009A (en) * 2018-10-16 2020-05-01 立錡科技股份有限公司 High voltage device and manufacturing method thereof
CN112216738A (en) * 2019-07-09 2021-01-12 台湾积体电路制造股份有限公司 Integrated chip and forming method thereof
CN112216745A (en) * 2020-12-10 2021-01-12 北京芯可鉴科技有限公司 High-voltage asymmetric LDMOS device and preparation method thereof

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