CN111613533B - Method for manufacturing asymmetric low-medium voltage device and asymmetric low-medium voltage device - Google Patents
Method for manufacturing asymmetric low-medium voltage device and asymmetric low-medium voltage device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 150000002500 ions Chemical class 0.000 claims abstract description 23
- -1 boron ions Chemical class 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
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Abstract
Description
技术领域Technical Field
本发明属于半导体器件制造技术领域，尤其涉及一种制作非对称低中压器件的方法及非对称低中压器件。The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a method for manufacturing an asymmetric low-medium voltage device and the asymmetric low-medium voltage device.
背景技术Background technique
6V～8V Asym-DEMOS(非对称低中压器件)在SWITCH(转换器)以及LDO(低压差线性稳压器)领域有很大的应用需求。图1中示出的是一典型的Asym-DEMOS的剖面图，其沟道区域由5V NMOS(N型金属氧化物半导体)的P阱11构成，衬底区的上表面的闸极13与P阱11的重合的P阱区域为沟道，沟道的的长度为L，漂移区由5V PMOS(P型金属氧化物半导体)的N阱12构成。6V～8V Asym-DEMOS (asymmetric low and medium voltage devices) have great application demand in the fields of SWITCH (converter) and LDO (low dropout linear regulator). Figure 1 shows a cross-sectional view of a typical Asym-DEMOS, whose channel region is composed of a 5V NMOS (N-type metal oxide semiconductor) P well 11, the gate 13 on the upper surface of the substrate region and the P well region overlapping the P well 11 are the channel, the length of the channel is L, and the drift region is composed of a 5V PMOS (P-type metal oxide semiconductor) N well 12.
因为穿通电压与击穿电压都起着限制着晶体管最高工作电压的作用，P阱11与N阱12的击穿电压为16V(伏)左右，Asym-DEMOS的VDD(操作电压)在10V以内，低于16V的击穿电压，可保证Asym-DEMOS工作在正常电压范围内而不会击穿。Because both the punch-through voltage and the breakdown voltage play a role in limiting the maximum operating voltage of the transistor, the breakdown voltage of the P-well 11 and the N-well 12 is about 16V (volts), and the VDD (operating voltage) of Asym-DEMOS is within 10V, which is lower than the breakdown voltage of 16V, which can ensure that Asym-DEMOS operates within the normal voltage range without breakdown.
又因为受限于5V COMS穿通电压(punch-through)的要求，Asym-DEMOS器件的沟道长度L最低范围为0.5-0.6um(微米)，无法再根据器件做进一步缩小，这就限制了导通电阻的进一步改善，导致电阻较大，从而导致Asym-DEMOS的性能不高。Also, due to the limitation of 5V COMS punch-through voltage requirement, the minimum channel length L of Asym-DEMOS device is 0.5-0.6um (micrometer), which cannot be further reduced according to the device. This limits the further improvement of on-resistance, resulting in larger resistance and thus low performance of Asym-DEMOS.
发明内容Summary of the invention
本发明要解决的技术问题是为了克服现有技术中Asym-DEMOS的导通电阻较大，导致Asym-DEMOS的性能不高的缺陷，提供一种制作非对称低中压器件的方法及非对称低中压器件。The technical problem to be solved by the present invention is to overcome the defect of Asym-DEMOS in the prior art that the on-resistance is large, resulting in low performance of Asym-DEMOS, and to provide a method for manufacturing an asymmetric low and medium voltage device and an asymmetric low and medium voltage device.
本发明是通过下述技术方案来解决上述技术问题：The present invention solves the above technical problems through the following technical solutions:
提供一种制作非对称低中压器件的方法，所述方法包括：A method for manufacturing an asymmetric low-medium voltage device is provided, the method comprising:
在非对称低中压器件的衬底区形成N阱和P阱；forming an N-well and a P-well in a substrate region of an asymmetric low-medium voltage device;
在所述N阱上方的所述衬底区的上表面制作闸极，所述闸极与所述P阱无重合区域；Fabricate a gate on the upper surface of the substrate region above the N-well, wherein the gate has no overlapping area with the P-well;
从所述P阱上方的所述衬底区的上表面打开窗口，并大角度注入第一掺杂离子形成第一掺杂区；Open a window from the upper surface of the substrate region above the P well, and implant first doping ions at a large angle to form a first doping region;
从所述P阱上方的所述衬底区的上表面以小角度注入第二掺杂离子至所述第一掺杂区内形成第二掺杂区，所述第一掺杂区与所述第二掺杂区在横向上的间隔形成沟道。Second doping ions are implanted into the first doping region at a small angle from the upper surface of the substrate region above the P-well to form a second doping region, and a channel is formed between the first doping region and the second doping region in a lateral direction.
较佳地，所述从所述P阱上方的所述衬底区的上表面以小角度注入第二掺杂离子的步骤之后还包括：Preferably, after the step of implanting the second doping ions from the upper surface of the substrate region above the P-well at a small angle, the method further comprises:
在所述衬底区制作N型重掺杂区。An N-type heavily doped region is formed in the substrate region.
较佳地，在所述衬底区制作N型重掺杂区的步骤之后还包括：Preferably, after the step of forming the N-type heavily doped region in the substrate region, the method further comprises:
在所述闸极和所述N阱对应的所述衬底区的上表面之间形成合金阻挡区。An alloy barrier region is formed between the gate and an upper surface of the substrate region corresponding to the N well.
较佳地，在所述非对称低中压器件的衬底区形成N阱和P阱步骤之前还包括：Preferably, before the step of forming an N-well and a P-well in the substrate region of the asymmetric low and medium voltage device, the method further includes:
在所述非对称低中压器件的基片上形成衬底区以及在所述非对称低中压器件的基片上制作STI。A substrate region is formed on the substrate of the asymmetric low-medium voltage device, and an STI is manufactured on the substrate of the asymmetric low-medium voltage device.
较佳地，所述第一掺杂离子为硼离子，所述硼离子的掺杂浓度为1.8E12/立方厘米～2.2E12/立方厘米。Preferably, the first doping ions are boron ions, and the doping concentration of the boron ions is 1.8E12/cubic centimeter to 2.2E12/cubic centimeter.
较佳地，在所述大角度注入第一掺杂离子以形成沟道的步骤中，所述大角度注入的角度范围为27～33度。Preferably, in the step of implanting the first doping ions at a large angle to form a channel, the angle range of the large-angle implantation is 27 to 33 degrees.
较佳地，所述沟道的长度范围为0.05～0.3微米。Preferably, the length of the channel ranges from 0.05 to 0.3 microns.
较佳地，所述第二掺杂离子为砷离子，所述砷离子的掺杂浓度为5.5E14/立方厘米～6.1E14/立方厘米。Preferably, the second doping ions are arsenic ions, and the doping concentration of the arsenic ions is 5.5E14/cubic centimeter to 6.1E14/cubic centimeter.
较佳地，所述小角度注入的角度范围为0～10度。Preferably, the angle range of the small-angle injection is 0 to 10 degrees.
提供一种非对称低中压器件，所述非对称低中压器件包括：An asymmetric low-medium voltage device is provided, the asymmetric low-medium voltage device comprising:
衬底区；substrate area;
位于所述衬底区中的N阱和P阱；An N-well and a P-well located in the substrate region;
位于所述N阱上方的闸极，所述闸极与所述P阱无重合区域；A gate located above the N-well, wherein the gate has no overlapping area with the P-well;
位于所述P阱上方第一掺杂区；a first doped region located above the P-well;
位于所述第一掺杂区内的第二掺杂区，所述第一掺杂区与所述第二掺杂区在横向上的间隔形成沟道。The second doping region is located in the first doping region, and a channel is formed between the first doping region and the second doping region in a lateral direction.
本发明的积极进步效果在于：The positive and progressive effects of the present invention are:
本发明通过在第一掺杂区和第二掺杂区间形成的沟道，与传统的非对称低中压器件中的沟道相比，沟通长度变短，与传统的非对称低中压器件中的沟道相比，沟通长度变短，从而有效地降低导通电阻，进而进一步提高Asym-DEMOS的性能。The present invention forms a channel between the first doping region and the second doping region, and compared with the channel in the traditional asymmetric low and medium voltage devices, the communication length is shortened, thereby effectively reducing the on-resistance and further improving the performance of Asym-DEMOS.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为本发明的现有技术的非对称低中压器件的结构示意图。FIG. 1 is a schematic structural diagram of an asymmetric low-medium voltage device of the prior art of the present invention.
图2为本发明的实施例1的制作非对称低中压器件的方法的流程示意图。FIG. 2 is a schematic flow chart of a method for manufacturing an asymmetric low-medium voltage device according to Embodiment 1 of the present invention.
图3为本发明的实施例1的制作非对称低中压器件的方法中的步骤100的示意图。FIG. 3 is a schematic diagram of step 100 in the method for manufacturing an asymmetric low-medium voltage device according to Embodiment 1 of the present invention.
图4为本发明的实施例1的制作非对称低中压器件的方法中的步骤101的示意图。FIG. 4 is a schematic diagram of step 101 in the method for manufacturing an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
图5为本发明的实施例1的制作非对称低中压器件的方法中的步骤102的示意图。FIG. 5 is a schematic diagram of step 102 in the method for manufacturing an asymmetric low-medium voltage device according to Embodiment 1 of the present invention.
图6为本发明的实施例1的制作非对称低中压器件的方法中的步骤103的示意图。FIG. 6 is a schematic diagram of step 103 in the method for manufacturing an asymmetric low-medium voltage device according to Embodiment 1 of the present invention.
图7为本发明的实施例1的制作非对称低中压器件的方法中的步骤104的示意图。FIG. 7 is a schematic diagram of step 104 in the method for manufacturing an asymmetric low-medium voltage device according to Embodiment 1 of the present invention.
图8为本发明的实施例1的制作非对称低中压器件的方法中的步骤105的示意图。FIG. 8 is a schematic diagram of step 105 in the method for manufacturing an asymmetric low-medium voltage device according to Embodiment 1 of the present invention.
图9为本发明的实施例1的制作非对称低中压器件的方法中的步骤106的示意图。FIG. 9 is a schematic diagram of step 106 in the method for manufacturing an asymmetric low-medium voltage device according to Embodiment 1 of the present invention.
具体实施方式Detailed ways
下面通过实施例的方式进一步说明本发明，但并不因此将本发明限制在所述的实施例范围之中。The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.
实施例1Example 1
本实施例提供一种制作非对称低中压器件的方法，其方法流程示意图如图2所示，此方法包括：This embodiment provides a method for manufacturing an asymmetric low-medium voltage device, and a schematic flow chart of the method is shown in FIG2 . The method includes:
步骤100、如图3所示，在非对称低中压器件的基片上形成衬底区以及在非对称低中压器件的基片上制作STI21。Step 100, as shown in FIG. 3, a substrate region is formed on a substrate of an asymmetric low-medium voltage device and an STI 21 is fabricated on the substrate of the asymmetric low-medium voltage device.
步骤101、如图4所示，在非对称低中压器件的衬底区形成N阱22和P阱23。Step 101, as shown in FIG. 4, an N-well 22 and a P-well 23 are formed in a substrate region of an asymmetric low-medium voltage device.
步骤102、如图5所示，在N阱22上方的衬底区的上表面制作闸极24，闸极24与P阱23无重合区域。Step 102 , as shown in FIG. 5 , a gate 24 is formed on the upper surface of the substrate region above the N-well 22 , and the gate 24 has no overlapping area with the P-well 23 .
闸极24与衬底区通过氧化层隔离。The gate 24 is isolated from the substrate region by an oxide layer.
步骤103、如图6所示，从P阱23上方的衬底区的上表面打开窗口，并大角度注入第一掺杂离子以形成第一掺杂区25。Step 103 , as shown in FIG. 6 , a window is opened from the upper surface of the substrate region above the P-well 23 , and first doping ions are implanted at a large angle to form a first doping region 25 .
闸极24作为自阻挡层，在沿箭头所示方向大角度的向P阱区区域注入第一掺杂离子形成第一掺杂区，大角度注入是本领域技术术语，本领域技术人员清楚大角度注入所采用的角度的范围。在本实施例中，大角度注入第一掺杂离子为硼离子，硼离子的掺杂浓度为1.8E12/立方厘米～2.2E12/立方厘米，大角度注入的角度范围为27～33度。The gate 24 acts as a self-blocking layer, and the first doping ions are injected into the P-well region at a large angle along the direction indicated by the arrow to form a first doping region. Large-angle injection is a technical term in the art, and those skilled in the art are aware of the range of angles used for large-angle injection. In this embodiment, the first doping ions injected at a large angle are boron ions, and the doping concentration of the boron ions is 1.8E12/cubic centimeter to 2.2E12/cubic centimeter. The angle range of the large-angle injection is 27 to 33 degrees.
步骤104、如图7所示，从P阱上方的衬底区的上表面以小角度注入第二掺杂离子至第一掺杂区内形成第二掺杂区26，第一掺杂区25与第二掺杂区26在横向上的间隔形成沟道LL。Step 104, as shown in FIG. 7, second doping ions are implanted into the first doping region at a small angle from the upper surface of the substrate region above the P well to form a second doping region 26, and the first doping region 25 and the second doping region 26 are spaced apart in the lateral direction to form a channel LL.
第二掺杂离子为砷离子。砷离子的掺杂浓度为5.5E14/立方厘米～6.1E14/立方厘米；沿箭头所示方向注入的小角度注入的范围为0～10度，注入深度为0.025-0.03微米，第一掺杂区与第二掺杂区在横向上的间隔形成的沟道LL的长度范围为0.05～0.3微米。The second doping ion is arsenic ion. The doping concentration of arsenic ion is 5.5E14/cm3 to 6.1E14/cm3; the range of small angle injection along the direction indicated by the arrow is 0 to 10 degrees, the injection depth is 0.025-0.03 microns, and the length of the channel LL formed by the interval between the first doping region and the second doping region in the lateral direction is in the range of 0.05 to 0.3 microns.
本实施例采用Halo注入(晕环注入，一种半导体器件制造工艺)广泛应用于低压(例如，1.8伏)CMOS器件的制作，主要原理是在LDD(轻掺杂漏区)注入中加入相反类型的掺杂以抑制短沟道效应。This embodiment uses Halo implantation (halo ring implantation, a semiconductor device manufacturing process) which is widely used in the manufacture of low voltage (for example, 1.8 volts) CMOS devices. The main principle is to add the opposite type of doping to the LDD (lightly doped drain) implantation to suppress the short channel effect.
步骤105、如图8所示，在衬底区制作N型重掺杂区27。Step 105 , as shown in FIG. 8 , an N-type heavily doped region 27 is formed in the substrate region.
步骤106、如图9所示，在闸极24和N阱22对应的衬底区的上表面之间形成合金阻挡区29。Step 106 , as shown in FIG. 9 , an alloy barrier region 29 is formed between the gate 24 and the upper surface of the substrate region corresponding to the N-well 22 .
在闸极24边缘形成氧化层和金属电极28，在闸极24和N阱22对应的衬底区的上表面之间形成合金阻挡区29。An oxide layer and a metal electrode 28 are formed at the edge of the gate 24 , and an alloy barrier region 29 is formed between the gate 24 and the upper surface of the substrate region corresponding to the N-well 22 .
本实施例的方法形成的沟道，与传统的非对称低中压器件中的沟道相比，沟通长度变短，从而有效地降低导通电阻，并且也没有增加任何的光罩层次，降低了成本，同时还可以维持比较高的击穿电压范围，进而进一步提高Asym-DEMOS的性能。The channel formed by the method of this embodiment has a shorter communication length compared to the channel in the traditional asymmetric low and medium voltage device, thereby effectively reducing the on-resistance, and does not increase any mask layers, thereby reducing costs. At the same time, it can maintain a relatively high breakdown voltage range, thereby further improving the performance of Asym-DEMOS.
实施例2Example 2
提供一种非对称低中压器件，如图9所示，非对称低中压器件包括衬底区、位于衬底区中的N阱22和P阱23、位于N阱上方的闸极24，闸极与P阱23无重合区域、位于P阱23上方的第一掺杂区25、位于第一掺杂区内的第二掺杂区26，第一掺杂区25与第二掺杂区26在横向上的间隔形成沟道LL。An asymmetric low-medium voltage device is provided. As shown in FIG9 , the asymmetric low-medium voltage device includes a substrate region, an N-well 22 and a P-well 23 located in the substrate region, a gate 24 located above the N-well, the gate and the P-well 23 have no overlapping area, a first doping region 25 located above the P-well 23, and a second doping region 26 located in the first doping region. The first doping region 25 and the second doping region 26 are spaced apart in the lateral direction to form a channel LL.
虽然以上描述了本发明的具体实施方式，但是本领域的技术人员应当理解，这仅是举例说明，本发明的保护范围是由所附权利要求书限定的。本领域的技术人员在不背离本发明的原理和实质的前提下，可以对这些实施方式做出多种变更或修改，但这些变更和修改均落入本发明的保护范围。Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.
Claims (8)
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510279A (en) * | 1995-01-06 | 1996-04-23 | United Microelectronics Corp. | Method of fabricating an asymmetric lightly doped drain transistor device |
| WO2003017349A2 (en) * | 2001-08-17 | 2003-02-27 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Dmos transistor |
| CN101484985A (en) * | 2005-07-25 | 2009-07-15 | 飞思卡尔半导体公司 | Semiconductor devices and method of fabrication |
| CN101609841A (en) * | 2008-06-18 | 2009-12-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of metal-oxide semiconductor (MOS) (MOS) transistor arrangement and manufacture method thereof |
| CN201898135U (en) * | 2009-05-28 | 2011-07-13 | 成都芯源系统有限公司 | MOSFET device |
| CN102760734A (en) * | 2011-04-27 | 2012-10-31 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN103325834A (en) * | 2013-05-02 | 2013-09-25 | 上海华力微电子有限公司 | Transistor and method for forming channel length of transistor |
| CN103956384A (en) * | 2014-04-29 | 2014-07-30 | 无锡中星微电子有限公司 | High-voltage PMOS transistor and manufacturing method thereof |
| KR20180110703A (en) * | 2017-03-29 | 2018-10-11 | 매그나칩 반도체 유한회사 | Semiconductor Device Structure having Low Rdson and Manufacturing Method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6384457B2 (en) * | 1999-05-03 | 2002-05-07 | Intel Corporation | Asymmetric MOSFET devices |
| US6908859B2 (en) * | 2001-10-12 | 2005-06-21 | Texas Instruments Incorporated | Low leakage power transistor and method of forming |
| US20050006701A1 (en) * | 2003-07-07 | 2005-01-13 | Tzu-Chiang Sung | High voltage metal-oxide semiconductor device |
| US7365402B2 (en) * | 2005-01-06 | 2008-04-29 | Infineon Technologies Ag | LDMOS transistor |
| KR102087444B1 (en) * | 2013-11-13 | 2020-03-11 | 매그나칩 반도체 유한회사 | Semiconductor device and manufacturing method thereof |
| US10158028B2 (en) * | 2017-02-23 | 2018-12-18 | MACROIX International Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
2019
- 2019-02-26 CN CN201910142611.2A patent/CN111613533B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510279A (en) * | 1995-01-06 | 1996-04-23 | United Microelectronics Corp. | Method of fabricating an asymmetric lightly doped drain transistor device |
| WO2003017349A2 (en) * | 2001-08-17 | 2003-02-27 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Dmos transistor |
| CN101484985A (en) * | 2005-07-25 | 2009-07-15 | 飞思卡尔半导体公司 | Semiconductor devices and method of fabrication |
| CN101609841A (en) * | 2008-06-18 | 2009-12-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of metal-oxide semiconductor (MOS) (MOS) transistor arrangement and manufacture method thereof |
| CN201898135U (en) * | 2009-05-28 | 2011-07-13 | 成都芯源系统有限公司 | MOSFET device |
| CN102760734A (en) * | 2011-04-27 | 2012-10-31 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN103325834A (en) * | 2013-05-02 | 2013-09-25 | 上海华力微电子有限公司 | Transistor and method for forming channel length of transistor |
| CN103956384A (en) * | 2014-04-29 | 2014-07-30 | 无锡中星微电子有限公司 | High-voltage PMOS transistor and manufacturing method thereof |
| KR20180110703A (en) * | 2017-03-29 | 2018-10-11 | 매그나칩 반도체 유한회사 | Semiconductor Device Structure having Low Rdson and Manufacturing Method thereof |
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