CN111613533B - Method for manufacturing asymmetric low-medium voltage device and asymmetric low-medium voltage device - Google Patents
Method for manufacturing asymmetric low-medium voltage device and asymmetric low-medium voltage device Download PDFInfo
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- CN111613533B CN111613533B CN201910142611.2A CN201910142611A CN111613533B CN 111613533 B CN111613533 B CN 111613533B CN 201910142611 A CN201910142611 A CN 201910142611A CN 111613533 B CN111613533 B CN 111613533B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 150000002500 ions Chemical class 0.000 claims abstract description 23
- -1 boron ions Chemical class 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims 3
- 239000007924 injection Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 239000007943 implant Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing an asymmetric low-medium voltage device and the asymmetric low-medium voltage device, wherein the method comprises the following steps: forming an N well and a P well in a substrate region of the asymmetric low-medium voltage device; manufacturing a gate on the upper surface of the substrate area above the N well, wherein the gate and the P well have no overlapping area; opening a window from the upper surface of the substrate region above the P well, and implanting first doping ions at a large angle to form a first doping region; second doping ions are injected into the first doping region from the upper surface of the substrate region above the P well at a small angle to form a second doping region, and a channel is formed between the first doping region and the second doping region in the transverse direction. Compared with the channel in the traditional asymmetric low-medium voltage device, the channel formed in the first doping region and the second doping region has the advantages that the communication length is shortened, and the on-resistance is effectively reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a method for manufacturing an asymmetric low-medium voltage device and the asymmetric low-medium voltage device.
Background
The application of 6V-8V Asym-DEMOS (asymmetric low and medium voltage device) in the fields of SWITCH (converter) and LDO (low dropout linear voltage regulator) is very high. Fig. 1 shows a typical layout of an sym-DEMOS, in which the channel region is formed by a P-well 11 of a 5V NMOS (N-type metal oxide semiconductor), the P-well region where the gate electrode 13 on the upper surface of the substrate region coincides with the P-well 11 is a channel, the length of the channel is L, and the drift region is formed by an N-well 12 of a 5V PMOS (P-type metal oxide semiconductor).
Because the punch-through voltage and the breakdown voltage both play a role in limiting the highest working voltage of the transistor, the breakdown voltage of the P well 11 and the N well 12 is about 16V (volts), the VDD (operating voltage) of the Asym-DEMOS is within 10V, and the breakdown voltage is lower than 16V, so that the Asym-DEMOS can be ensured to work in a normal voltage range without breakdown.
And because the minimum range of the channel length Lmin of the Asym-DEMOS device is 0.5-0.6um (micrometers) due to the requirement of 5V COMS punch-through voltage, the device cannot be further reduced according to the device, the on-resistance is further improved, the resistance is larger, and the performance of the Asym-DEMOS device is not high.
Disclosure of Invention
The invention aims to overcome the defect of low performance of the Asym-DEMOS caused by larger on-resistance of the Asym-DEMOS in the prior art, and provides a method for manufacturing an asymmetric low-medium-voltage device and the asymmetric low-medium-voltage device.
The invention solves the technical problems by the following technical scheme:
A method of fabricating an asymmetric low-to-medium voltage device is provided, the method comprising:
Forming an N well and a P well in a substrate region of the asymmetric low-medium voltage device;
Manufacturing a gate on the upper surface of the substrate region above the N well, wherein the gate and the P well have no overlapping region;
Opening a window from the upper surface of the substrate region above the P well, and implanting first doping ions at a large angle to form a first doping region;
Second doping ions are implanted into the first doping region from the upper surface of the substrate region above the P well at a small angle to form a second doping region, and a channel is formed between the first doping region and the second doping region in the transverse direction.
Preferably, the step of implanting second doping ions at a small angle from the upper surface of the substrate region above the P-well further comprises:
And manufacturing an N-type heavily doped region in the substrate region.
Preferably, the step of fabricating the N-type heavily doped region in the substrate region further comprises:
And forming an alloy blocking region between the gate and the upper surface of the substrate region corresponding to the N well.
Preferably, before the step of forming the N-well and the P-well in the substrate region of the asymmetric low-medium voltage device, the method further comprises:
And forming a substrate region on the substrate of the asymmetric low-medium voltage device and manufacturing STI on the substrate of the asymmetric low-medium voltage device.
Preferably, the first doping ion is boron ion, and the doping concentration of the boron ion is 1.8E12/cubic centimeter-2.2E12/cubic centimeter.
Preferably, in the step of implanting the first dopant ions at a large angle to form the channel, the angle of the large angle implantation is in the range of 27 to 33 degrees.
Preferably, the length of the channel is in the range of 0.05 to 0.3 microns.
Preferably, the second doping ion is arsenic ion, and the doping concentration of the arsenic ion is 5.5E14/cubic centimeter-6.1E14/cubic centimeter.
Preferably, the angle of the small angle implant is in the range of 0-10 degrees.
An asymmetric low-to-medium voltage device is provided, the asymmetric low-to-medium voltage device comprising:
A substrate region;
an N-well and a P-well in the substrate region;
The gate electrode is positioned above the N well, and no overlapping area exists between the gate electrode and the P well;
The first doped region is positioned above the P well;
and the second doped region is positioned in the first doped region, and a channel is formed between the first doped region and the second doped region in the transverse direction.
The invention has the positive progress effects that:
according to the invention, the channel formed in the first doping region and the second doping region has a shorter communication length compared with the channel in the traditional asymmetric low-medium voltage device, and has a shorter communication length compared with the channel in the traditional asymmetric low-medium voltage device, so that the on-resistance is effectively reduced, and the performance of the Asym-DEMOS is further improved.
Drawings
Fig. 1 is a schematic structural diagram of an asymmetric low-medium voltage device of the prior art of the present invention.
Fig. 2 is a flow chart of a method for fabricating an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
Fig. 3 is a schematic diagram of step 100 in the method of fabricating an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of step 101 in the method for fabricating an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
Fig. 5 is a schematic diagram of step 102 in the method of fabricating an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
Fig. 6 is a schematic diagram of step 103 in the method of fabricating an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
Fig. 7 is a schematic diagram of step 104 in the method of fabricating an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
Fig. 8 is a schematic diagram of step 105 in the method of fabricating an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
Fig. 9 is a schematic diagram of step 106 in the method of fabricating an asymmetric low-medium voltage device according to embodiment 1 of the present invention.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Example 1
The embodiment provides a method for manufacturing an asymmetric low-medium voltage device, the flow chart of which is shown in fig. 2, the method comprises the following steps:
Step 100, as shown in fig. 3, forms a substrate region on a substrate of an asymmetric low-medium voltage device and fabricates STI21 on the substrate of the asymmetric low-medium voltage device.
Step 101, as shown in fig. 4, forming an N well 22 and a P well 23 in a substrate region of the asymmetric low-medium voltage device.
In step 102, as shown in fig. 5, a gate 24 is formed on the upper surface of the substrate region above the N-well 22, and the gate 24 and the P-well 23 have no overlapping region.
The gate 24 is isolated from the substrate region by an oxide layer.
Step 103, as shown in fig. 6, a window is opened from the upper surface of the substrate region above the P-well 23, and the first dopant ions are implanted at a large angle to form the first doped region 25.
Gate 24 serves as a self-blocking layer to implant first dopant ions into the P-well region at a high angle in the direction indicated by the arrow to form a first doped region, the high angle implant being a term of art, and the range of angles employed for the high angle implant will be apparent to those skilled in the art. In this embodiment, the first dopant ions are boron ions, the doping concentration of the boron ions is 1.8E12/cc-2.2E12/cc, and the angle range of the large-angle implantation is 27-33 degrees.
Step 104, as shown in fig. 7, implanting second doped ions into the first doped region from the upper surface of the substrate region above the P-well at a small angle to form a second doped region 26, and laterally spacing the first doped region 25 from the second doped region 26 to form a channel LL.
The second dopant ions are arsenic ions. The doping concentration of arsenic ions is 5.5E14/cubic centimeter-6.1E14/cubic centimeter; the small angle implantation along the direction indicated by the arrow ranges from 0 to 10 degrees, the implantation depth ranges from 0.025 to 0.03 microns, and the length of the channel LL formed by the first doped region and the second doped region at a lateral interval ranges from 0.05 to 0.3 microns.
The present embodiment is widely applied to the fabrication of low voltage (e.g., 1.8 v) CMOS devices using Halo implantation (Halo implantation, a semiconductor device fabrication process), and the main principle is to incorporate opposite type doping in LDD (lightly doped drain) implantation to suppress short channel effects.
In step 105, as shown in fig. 8, an N-type heavily doped region 27 is formed in the substrate region.
At step 106, as shown in fig. 9, an alloy barrier 29 is formed between the gate 24 and the upper surface of the corresponding substrate region of the N-well 22.
An oxide layer and a metal electrode 28 are formed at the edge of the gate 24, and an alloy barrier 29 is formed between the gate 24 and the upper surface of the corresponding substrate region of the N-well 22.
Compared with the channel in the traditional asymmetric low-medium voltage device, the channel formed by the method has the advantages that the communication length is shortened, so that the on-resistance is effectively reduced, any photomask level is not increased, the cost is reduced, a relatively high breakdown voltage range can be maintained, and the performance of the Asym-DEMOS is further improved.
Example 2
An asymmetric low-medium voltage device is provided, as shown in fig. 9, and the asymmetric low-medium voltage device comprises a substrate region, an N-well 22 and a P-well 23 which are positioned in the substrate region, a gate 24 positioned above the N-well, a non-overlapping region of the gate and the P-well 23, a first doped region 25 positioned above the P-well 23, and a second doped region 26 positioned in the first doped region, wherein the first doped region 25 and the second doped region 26 form a channel LL at a lateral interval.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (8)
1. A method of fabricating an asymmetric low-to-medium voltage device, the method comprising:
Forming an N well and a P well in a substrate region of the asymmetric low-medium voltage device;
Manufacturing a gate on the upper surface of the substrate region above the N well, wherein the gate and the P well have no overlapping region;
Opening a window from the upper surface of the substrate region above the P well, and implanting first doping ions at a large angle to form a first doping region;
implanting second doping ions into the first doping region from the upper surface of the substrate region above the P well at a small angle to form a second doping region, wherein a channel is formed between the first doping region and the second doping region in the transverse direction;
the first doping ions are boron ions;
The second doping ions are arsenic ions;
in the step of implanting first doping ions at a large angle to form a channel, the angle range of the large-angle implantation is 27-33 degrees;
the angle range of the small-angle injection is 0-10 degrees.
2. The method of fabricating an asymmetric low and medium voltage device as claimed in claim 1, wherein said implanting second dopant ions at a small angle from an upper surface of said substrate region above said P-well further comprises:
And manufacturing an N-type heavily doped region in the substrate region.
3. The method of fabricating an asymmetric low and medium voltage device according to claim 2, further comprising, after the step of fabricating an N-type heavily doped region in the substrate region:
And forming an alloy blocking region between the gate and the upper surface of the substrate region corresponding to the N well.
4. The method of fabricating an asymmetric low-medium voltage device according to claim 1, further comprising, prior to the step of forming N-wells and P-wells in the substrate region of the asymmetric low-medium voltage device:
And forming a substrate region on the substrate of the asymmetric low-medium voltage device and manufacturing STI on the substrate of the asymmetric low-medium voltage device.
5. The method of fabricating an asymmetric low and medium voltage device according to claim 1, wherein the boron ions have a doping concentration of 1.8E12 to 2.2E12 per cubic centimeter.
6. The method of fabricating an asymmetric low and medium voltage device according to claim 1, wherein the length of the channel ranges from 0.05 to 0.3 microns.
7. The method of fabricating an asymmetric low and medium voltage device according to claim 1, wherein the arsenic ions have a doping concentration of 5.5E14 to 6.1E14 per cubic centimeter.
8. An asymmetric low-medium voltage device, characterized in that it is manufactured based on the method of manufacturing an asymmetric low-medium voltage device according to any of claims 1-7, comprising:
A substrate region;
an N-well and a P-well in the substrate region;
The gate electrode is positioned above the N well, and no overlapping area exists between the gate electrode and the P well;
The first doped region is positioned above the P well;
a second doped region located within the first doped region, the first doped region and the second doped region laterally spaced apart to form a channel;
The first doped region is formed by opening a window from the upper surface of the substrate region above the P well and implanting first doped ions at a large angle;
The second doped region is formed by implanting second doped ions into the first doped region from the upper surface of the substrate region above the P-well at a small angle;
the first doping ions are boron ions;
The second doping ions are arsenic ions;
The angle range of the large-angle injection is 27-33 degrees;
the angle range of the small-angle injection is 0-10 degrees.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510279A (en) * | 1995-01-06 | 1996-04-23 | United Microelectronics Corp. | Method of fabricating an asymmetric lightly doped drain transistor device |
| WO2003017349A2 (en) * | 2001-08-17 | 2003-02-27 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Dmos transistor |
| CN101484985A (en) * | 2005-07-25 | 2009-07-15 | 飞思卡尔半导体公司 | Semiconductor devices and method of fabrication |
| CN101609841A (en) * | 2008-06-18 | 2009-12-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of metal-oxide semiconductor (MOS) (MOS) transistor arrangement and manufacture method thereof |
| CN201898135U (en) * | 2009-05-28 | 2011-07-13 | 成都芯源系统有限公司 | MOSFET device |
| CN102760734A (en) * | 2011-04-27 | 2012-10-31 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN103325834A (en) * | 2013-05-02 | 2013-09-25 | 上海华力微电子有限公司 | Transistor and method for forming channel length of transistor |
| CN103956384A (en) * | 2014-04-29 | 2014-07-30 | 无锡中星微电子有限公司 | High-voltage PMOS transistor and manufacturing method thereof |
| KR20180110703A (en) * | 2017-03-29 | 2018-10-11 | 매그나칩 반도체 유한회사 | Semiconductor Device Structure having Low Rdson and Manufacturing Method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6384457B2 (en) * | 1999-05-03 | 2002-05-07 | Intel Corporation | Asymmetric MOSFET devices |
| US6908859B2 (en) * | 2001-10-12 | 2005-06-21 | Texas Instruments Incorporated | Low leakage power transistor and method of forming |
| US20050006701A1 (en) * | 2003-07-07 | 2005-01-13 | Tzu-Chiang Sung | High voltage metal-oxide semiconductor device |
| US7365402B2 (en) * | 2005-01-06 | 2008-04-29 | Infineon Technologies Ag | LDMOS transistor |
| KR102087444B1 (en) * | 2013-11-13 | 2020-03-11 | 매그나칩 반도체 유한회사 | Semiconductor device and manufacturing method thereof |
| US10158028B2 (en) * | 2017-02-23 | 2018-12-18 | MACROIX International Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
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- 2019-02-26 CN CN201910142611.2A patent/CN111613533B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510279A (en) * | 1995-01-06 | 1996-04-23 | United Microelectronics Corp. | Method of fabricating an asymmetric lightly doped drain transistor device |
| WO2003017349A2 (en) * | 2001-08-17 | 2003-02-27 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Dmos transistor |
| CN101484985A (en) * | 2005-07-25 | 2009-07-15 | 飞思卡尔半导体公司 | Semiconductor devices and method of fabrication |
| CN101609841A (en) * | 2008-06-18 | 2009-12-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of metal-oxide semiconductor (MOS) (MOS) transistor arrangement and manufacture method thereof |
| CN201898135U (en) * | 2009-05-28 | 2011-07-13 | 成都芯源系统有限公司 | MOSFET device |
| CN102760734A (en) * | 2011-04-27 | 2012-10-31 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN103325834A (en) * | 2013-05-02 | 2013-09-25 | 上海华力微电子有限公司 | Transistor and method for forming channel length of transistor |
| CN103956384A (en) * | 2014-04-29 | 2014-07-30 | 无锡中星微电子有限公司 | High-voltage PMOS transistor and manufacturing method thereof |
| KR20180110703A (en) * | 2017-03-29 | 2018-10-11 | 매그나칩 반도체 유한회사 | Semiconductor Device Structure having Low Rdson and Manufacturing Method thereof |
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