CN111613181B

CN111613181B - Display driving circuit, display module, driving method of display screen and electronic equipment

Info

Publication number: CN111613181B
Application number: CN201910844205.0A
Authority: CN
Inventors: 韦育伦; 刘俊彦
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-02-23
Filing date: 2019-09-06
Publication date: 2022-03-29
Anticipated expiration: 2039-09-06
Also published as: EP3920172A1; CN111613181A; EP3920172A4

Abstract

The application provides a display driving circuit, a display module, a driving method of a display screen and an electronic device, which can improve the display performance of the display screen. The electronic device includes: a display screen including a first display area and a second display area; the main controller is used for respectively sending a first clock signal to the first display driving circuit and the second display driving circuit; the first display driving circuit is used for receiving a first clock signal; the first display driving circuit is further used for outputting a first GOA clock signal to the display screen, wherein the first GOA clock signal is generated based on the first clock signal; the second display driving circuit is used for receiving the first clock signal; the second display driving circuit is further configured to output a second GOA clock signal to the display screen, wherein the second GOA clock signal is generated based on the first clock signal.

Description

Display driving circuit, display module, driving method of display screen and electronic equipment

Technical Field

The application relates to the technical field of terminals, in particular to a display driving circuit, a display module, a driving method of a display screen and electronic equipment.

Background

With the rapid development of electronic technology, electronic devices such as intelligent terminals and tablet computers have greatly changed the life and working modes of people. In order to meet various different requirements of users for entertainment, office work, video watching or web page browsing, the area design of the display screen of the electronic device is getting larger, and the performance requirement of the display driving circuit is also getting higher. Therefore, there may be a case where the capability of a single display driving circuit is insufficient to drive the display panel. In this case, the driving of the display screen may be realized using a plurality of display driving circuits, and such a driving structure may be referred to as a multi-display driving circuit system. In a multi-display driving circuit system, a plurality of display driving circuits need to be synchronized with a clock signal, so that a display screen can be guaranteed to output normal video images.

In a synchronization method in a multi-display driving circuit system, a main display driving circuit and at least one auxiliary display driving circuit may be included in a plurality of display driving circuits. The main display driving circuit sends a clock signal generated in the main display driving circuit to the auxiliary display driving circuit, and the auxiliary display driving circuit carries out time synchronization based on the received clock signal so as to realize synchronization among the plurality of display driving circuits. However, this synchronization method is only used to synchronize vertical synchronization (V-Sync) and horizontal synchronization (H-Sync) signals between a plurality of display driving circuits. Among them, the vertical synchronization signal is used for synchronization between frames of a scanned image, and the horizontal synchronization signal is used for synchronization between lines (line-to-line) of the scanned image. The clock signal in the line for scanning the pixels of each line is generated based on the internal clock signal of each display drive circuit, and is not clock-synchronized. The display performance of the display screen is affected due to errors in the internal clock frequencies of the different display driving circuits.

Disclosure of Invention

The application provides a display driving circuit, a display module, a driving method of a display screen and an electronic device, which can improve the display performance of the display screen.

In a first aspect, an electronic device is provided, including: a display screen including a first display area and a second display area; the main controller comprises a first clock output end, and the first clock output end is used for respectively sending a first clock signal to the first display driving circuit and the second display driving circuit; the first display driving circuit comprises a first clock receiving end, and the first clock receiving end is used for receiving the first clock signal; the first display driving circuit further comprises a first gate driver array (GOA) clock signal output end, the first GOA clock signal output end is used for outputting a first GOA clock signal to the display screen, the first GOA clock signal is used for controlling the GOA of the first display area to be turned on or turned off, and the first GOA clock signal is generated based on the first clock signal; the second display driving circuit comprises a second clock receiving end, and the second clock receiving end is used for receiving the first clock signal; the second display driving circuit further comprises a second GOA clock signal output end, wherein the second GOA clock signal output end is used for outputting a second GOA clock signal to the display screen, and the second GOA clock signal is used for controlling the second display area to be on or off, and the second GOA clock signal is generated based on the first clock signal.

In the embodiment of the present application, each of the plurality of display driving circuits in the electronic device may receive the first clock signal sent by the main controller, and generate the GOA clock signal based on the first clock signal, so that the plurality of display driving circuits output the GOA clock signals to the display screen are all generated based on the same clock signal, which may reduce errors between frequencies of the GOA clock signals between different display driving circuits, and improve display performance of the display screen.

With reference to the first aspect, in a possible implementation manner, the first display driving circuit further includes a first vertical synchronization signal output end, configured to output a first vertical synchronization signal to the display screen, where the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the first display area; the second display driving circuit further includes a second vertical synchronization signal output terminal configured to output a second vertical synchronization signal to the display screen, where the second vertical synchronization clock signal is generated based on the first clock signal, the second vertical synchronization signal is used to perform frame synchronization of the second display region, and the first vertical synchronization signal and the second vertical synchronization signal are signals having the same phase.

In the embodiment of the application, each of the plurality of display driving circuits in the electronic device may receive the first clock signal sent by the main controller and generate the vertical synchronization signal based on the first clock signal, so that the vertical synchronization signals output by the plurality of display driving circuits to the display screen are generated based on the same signal, thereby reducing an error in frequency of the vertical synchronization signal between different display driving circuits and a timing error between the vertical synchronization signal and the GOA clock signal, and improving display performance of the display screen.

With reference to the first aspect, in a possible implementation manner, the first display driving circuit further includes a first horizontal synchronization signal output end, configured to output a first horizontal synchronization signal to the display screen, where the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform line synchronization of the first display area; the second display driving circuit further includes a second horizontal synchronization signal output terminal for outputting a second horizontal synchronization signal to the display screen, wherein the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used for performing line synchronization of the second display region.

In the embodiment of the application, each display driving circuit in a plurality of display driving circuits in the electronic device receives the first clock signal sent by the main controller and generates the horizontal synchronization signal based on the first clock signal, so that the horizontal synchronization signals output by the plurality of display driving circuits to the display screen are generated based on the same clock signal, thereby reducing the error of the frequency of the horizontal synchronization signal among different display driving circuits, reducing the timing error between the horizontal synchronization signal and the GOA clock signal and improving the display performance of the display screen.

With reference to the first aspect, in a possible implementation manner, the first display driving circuit further includes a first emission EM signal output terminal, configured to output a first EM signal to the display screen, where the first EM signal is used to control a pixel circuit in the first display area to emit light or not, and the first EM signal is generated based on the first clock signal; and/or the second display driving circuit further comprises a second EM signal output terminal for outputting a second EM signal to the display screen, the second EM signal being used for controlling the pixel circuit in the second display region to emit light or not, wherein the second EM signal is generated based on the first clock signal.

In the embodiment of the application, each display driving circuit in a plurality of display driving circuits in the electronic device receives the first clock signal sent by the main controller and generates the EM signal based on the first clock signal, so that the plurality of display driving circuits output the EM signals to the display screen based on the same clock signal, thereby reducing the frequency error of the EM signal between different display driving circuits, reducing the timing error between the EM signal and the GOA clock signal and improving the display performance of the display screen.

With reference to the first aspect, in a possible implementation manner, the first display driving circuit includes a video processing module, the video processing module is configured to process video data input by the main controller to generate a video source signal sent to the display screen, a reference clock of a digital circuit in the video processing module is a third clock signal generated by an internal clock generation module of the first display driving circuit, and a reference clock of an analog circuit in the video processing module is the first clock signal.

In the embodiment of the application, the display driving circuit uses the first clock signal sent by the main controller as the reference clock of the analog circuit in the display driving circuit, and uses the internally generated third clock signal as the reference clock of the digital circuit in the display driving circuit, so that the frequency errors among the clock signals of a plurality of display driving circuits can be reduced, and the problems of timing convergence, electromagnetic interference and the like can be reduced.

With reference to the first aspect, in a possible implementation manner, a first buffer is disposed in the video processing module, and the first buffer is disposed between a digital circuit and an analog circuit in the video processing module.

In a second aspect, there is provided a display driving circuit comprising: the first clock receiving end is used for receiving a first clock signal sent by the main controller; the display screen comprises a first gate driving array GOA clock signal output end, wherein the first GOA clock signal output end is used for outputting a first GOA clock signal to the display screen, the first GOA clock signal is used for controlling the GOA of the display screen to be turned on or turned off, and the first GOA clock signal is generated based on the first clock signal.

It should be understood that the display driving circuit of the second aspect and the electronic device of the first aspect are based on the same inventive concept, and therefore, the technical solutions of the second aspect may refer to the description of the first aspect and are not described again.

With reference to the second aspect, in a possible implementation manner, the display driving circuit further includes a first vertical synchronization signal output end, configured to output a first vertical synchronization signal to the display screen, where the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the display screen.

With reference to the second aspect, in a possible implementation manner, the display driving circuit further includes a first horizontal synchronization signal output end, configured to output a first horizontal synchronization signal to the display screen, where the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform line synchronization of the display screen.

With reference to the second aspect, in a possible implementation manner, the first display driving circuit further includes a first emission EM signal output terminal, configured to output a first EM signal to the display screen, where the first EM signal is used to control a pixel circuit of the display screen to emit light or not, and the first EM signal is generated based on the first clock signal.

With reference to the second aspect, in a possible implementation manner, the display driving circuit includes a video processing module, where the video processing module is configured to process video data input by the main controller to generate a video source signal sent to the display screen, a reference clock of a digital circuit in the video processing module is a third clock signal generated by an internal clock generation module of the display driving circuit, and a reference clock of an analog circuit in the video processing module is the first clock signal.

With reference to the second aspect, in a possible implementation manner, a first buffer is disposed in the video processing module, and the first buffer is disposed between a digital circuit and an analog circuit in the video processing module.

In a third aspect, a method for driving a display panel including a first display region and a second display region includes: the main controller respectively sends a first clock signal to the first display driving circuit and the second display driving circuit; the first display driving circuit outputs a first gate driving array (GOA) clock signal to the display screen, wherein the first GOA clock signal is used for controlling the GOA of the first display area to be turned on or off, and the first GOA clock signal is generated based on the first clock signal; the second display driving circuit outputs a second GOA clock signal to the display screen, wherein the second GOA clock signal is used for controlling the GOA of the second display area to be turned on or off, and the second GOA clock signal is generated based on the first clock signal.

It should be understood that the driving method of the display screen of the third aspect and the electronic device of the first aspect are based on the same inventive concept, and therefore, the technical solution of the third aspect may refer to the description of the first aspect and will not be described again.

With reference to the third aspect, in a possible implementation manner, the method further includes: the first display driving circuit outputs a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used for performing frame synchronization of the first display area;

the second display driving circuit outputs a second vertical synchronization signal to the display screen, wherein the second vertical synchronization clock signal is generated based on the first clock signal, the second vertical synchronization signal is used for performing frame synchronization of the second display area, and the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

With reference to the third aspect, in a possible implementation manner, the first display driving circuit further includes a first horizontal synchronization signal output end configured to output a first horizontal synchronization signal to the display screen, where the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform line synchronization of the first display area; the second display driving circuit further includes a second horizontal synchronization signal output terminal for outputting a second horizontal synchronization signal to the display screen, wherein the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used for performing line synchronization of the second display region.

With reference to the third aspect, in a possible implementation manner, the first display driving circuit further includes a first emission EM signal output terminal configured to output a first EM signal to the display screen, where the first EM signal is used to control a pixel circuit in the first display area to emit light or not, and the first EM signal is generated based on the first clock signal; the second display driving circuit further includes a second EM signal output terminal for outputting a second EM signal to the display screen, the second EM signal being for controlling the pixel circuit in the second display region to emit or not to emit light, wherein the second EM signal is generated based on the first clock signal.

With reference to the third aspect, in a possible implementation manner, the first display driving circuit includes a video processing module, where the video processing module is configured to process video data input by the main controller to generate a video source signal sent to the display screen, a reference clock of a digital circuit in the video processing module is a third clock signal generated by an internal clock generation module of the first display driving circuit, and a reference clock of an analog circuit in the video processing module is the first clock signal.

With reference to the third aspect, in a possible implementation manner, a first buffer is disposed in the video processing module, and the first buffer is disposed between a digital circuit and an analog circuit in the video processing module.

In a fourth aspect, a display module is provided, which includes: a display screen including a first display area and a second display area; the first display driving circuit comprises a first clock receiving end, wherein the first clock receiving end is used for receiving a first clock signal sent by the main controller; the first display driving circuit further comprises a first gate driver array (GOA) clock signal output end, the first GOA clock signal output end is used for outputting a first GOA clock signal to the display screen, the first GOA clock signal is used for controlling the GOA of the first display area to be turned on or turned off, and the first GOA clock signal is generated based on the first clock signal; the second display driving circuit comprises a second clock receiving end, and the second clock receiving end is used for receiving the first clock signal; the second display driving circuit further comprises a second GOA clock signal output end, wherein the second GOA clock signal output end is used for outputting a second GOA clock signal to the display screen, and the second GOA clock signal is used for controlling the second display area to be on or off, and the second GOA clock signal is generated based on the first clock signal.

It should be understood that the display module of the fourth aspect and the electronic device of the first aspect are based on the same inventive concept, and therefore, the advantageous technical effects that can be achieved by the technical solution of the fourth aspect may refer to the description of the first aspect, and are not described again.

In a fourth aspect, in a possible implementation manner, the first display driving circuit further includes a first vertical synchronization signal output end, configured to output a first vertical synchronization signal to the display screen, where the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the first display area; the second display driving circuit further includes a second vertical synchronization signal output terminal configured to output a second vertical synchronization signal to the display screen, where the second vertical synchronization clock signal is generated based on the first clock signal, the second vertical synchronization signal is used to perform frame synchronization of the second display region, and the first vertical synchronization signal and the second vertical synchronization signal are signals having the same phase.

In a fourth aspect, in a possible implementation manner, the first display driving circuit further includes a first horizontal synchronization signal output terminal, configured to output a first horizontal synchronization signal to the display screen, where the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform line synchronization of the first display area; the second display driving circuit further includes a second horizontal synchronization signal output terminal for outputting a second horizontal synchronization signal to the display screen, wherein the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used for performing line synchronization of the second display region.

In a fourth aspect, in a possible implementation manner, the first display driving circuit further includes a first emission EM signal output terminal configured to output a first EM signal to the display screen, the first EM signal being configured to control a pixel circuit in the first display area to emit or not emit light, wherein the first EM signal is generated based on the first clock signal; the second display driving circuit further includes a second EM signal output terminal for outputting a second EM signal for controlling the pixel circuit in the second display region to emit or not to emit light to the display screen, wherein the second EM signal is generated based on the first clock signal.

In a fourth aspect, in a possible implementation manner, the first display driving circuit includes a video processing module, the video processing module is configured to process video data input by the main controller to generate a video source signal sent to the display screen, a reference clock of a digital circuit in the video processing module is a third clock signal generated by an internal clock generating module of the first display driving circuit, and a reference clock of an analog circuit in the video processing module is the first clock signal.

In a fourth aspect, in a possible implementation manner, a first buffer is disposed in the video processing module, and the first buffer is disposed between a digital circuit and an analog circuit in the video processing module.

In a fifth aspect, the present application provides circuitry comprising a processor. The processor is configured to read and execute the computer program stored in the memory to perform the method of the third aspect or any possible implementation thereof, or to perform the method of the fourth aspect or any possible implementation thereof.

Optionally, the circuit further comprises a memory, and the memory and the processor are connected with the memory through a circuit or a wire.

Further optionally, the circuitry further comprises a communication interface.

In a sixth aspect, the present application provides a computer-readable storage medium having stored thereon computer instructions which, when run on a computer, cause the computer to perform the method of the third aspect or any possible implementation thereof.

In a seventh aspect, the present application provides a computer program product comprising computer program code which, when run on a computer, causes the computer to perform the method of the third aspect or any possible implementation thereof.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application. .

FIG. 2 is a flow chart of processing video data by the multi-display driving circuitry according to an embodiment of the present application.

Fig. 3 is a circuit diagram of a pixel circuit according to an embodiment of the present application.

Fig. 4 is a circuit diagram illustrating a reset phase of a pixel circuit according to an embodiment of the present application.

Fig. 5 is a circuit diagram illustrating a data voltage Vdata writing phase of the pixel circuit according to an embodiment of the present application.

Fig. 6 is a circuit diagram illustrating a light emitting stage of a pixel circuit according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram of a gate driver on array (GOA) according to an embodiment of the present disclosure.

Fig. 8 is a timing diagram of a GOA according to an embodiment of the present application.

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Fig. 10 is a schematic structural diagram of an electronic device according to another embodiment of the present application.

Fig. 11 is a schematic structural diagram of a display driving circuit according to an embodiment of the present application. A

Fig. 12 is a schematic structural diagram of a digital circuit of a video processing module in a display driving circuit according to an embodiment of the present application.

Fig. 13 is a schematic structural diagram of an analog circuit of a video processing module in a display driving circuit according to an embodiment of the present application.

Fig. 14 is a schematic structural diagram of a video processing module according to an embodiment of the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

The embodiment of the application provides a display driving circuit, a driving method of a multi-display driving circuit system and an electronic device, which can improve the display performance of a display screen. Wherein the display driving circuit may be mounted in the electronic device.

The electronic device in the embodiment of the present application may include any electronic device including a display screen, such as a user equipment, a mobile terminal, a mobile phone, a tablet computer (pad), and the like, which is not limited in the embodiment of the present application.

An electronic device in an embodiment of the present application includes a multi-display driving system including a plurality of display driving circuits. In the embodiment of the present application, a multi-display driving system including two display driving circuits is taken as an example for description, and those skilled in the art can understand that the present application can also be applied to a multi-display driving circuit system including more than two display driving circuits.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device 100 is a multi-display driving circuitry. As shown in fig. 1, the electronic device 100 includes a main controller 110, a first display driving circuit 120, a second display driving circuit 130, and a display screen 140. For ease of explanation, the definitions of terms referred to in fig. 1 are described below.

The main controller 110: for outputting video data to be processed, clock synchronization signals, signaling, etc. to the display driver circuits (120, 130). The host controller may include, but is not limited to, various types of processors such as a System On Chip (SOC), an Application Processor (AP), or a general purpose processor.

Display driver circuitry (120, 130): for receiving the video data transmitted from the main controller 110 and obtaining a video source signal after performing digital part processing and analog part processing on the video data. The video source signal is used for outputting to the display screen 130 to drive the display screen 130 to display images. The display driving circuit 120 may also perform Emission (EM) control management, gate driver on array (GOA) control management, and power supply voltage management on the display panel 130, and output an Emission (EM) signal, a light-emitting layer positive voltage (VDD, ELVDD) signal, a light-emitting layer negative voltage (ELVSS) signal, a GOA clock signal, and the like to the display panel. In the embodiments of the present application, a video source signal may also be referred to as a source signal.

Alternatively, a plurality of display driving circuits may be connected via an interface to facilitate clock synchronization or interaction. In some examples, the display driver circuit may also be referred to as a Display Driver Integrated Circuit (DDIC).

And a display screen 140 for receiving video source signals from the display driving circuit 120 and the display driving circuit 130, respectively, and displaying images. The display screen may include a folding display screen or may include a non-folding display screen. The display screen 140 may be implemented by a flexible screen or a hard display screen. The flexible screen may include, for example, an organic light-emitting diode (OLED) display screen, which is not limited in this embodiment of the present application.

FIG. 2 is a flow chart of video data at the multi-display driving circuitry according to an embodiment of the present application. As shown in fig. 2, the display screen 140 may be divided into a first display region 11 and a second display region 12, the first display region 11 corresponding to the first display driving circuit 120, and the second display region 12 corresponding to the second display driving circuit 130. Different display driver circuits (120,130) are used to drive different display areas. Optionally, an interface may exist between the first display driving circuit 120 and the second display driving circuit 130, and clock synchronization or signaling interaction is performed through the interface.

The main controller 110 may divide the video data into a plurality of sub-video data according to the plurality of display areas, and transmit the sub-video data to different display driving circuits, respectively. Each display driving circuit in the plurality of display driving circuits processes the corresponding sub video data to obtain a plurality of sub video source signals. The plurality of display driving circuits may respectively send the plurality of sub video source signals to the display screen to drive different display areas of the display screen to display images.

In order to facilitate understanding of the scheme of the present application, the following describes the structure and operation principle of the pixel circuit and the GOA in the display screen according to the embodiment of the present application, with reference to the drawings. It should be noted that the following description is only an example of the pixel circuit and does not limit the scope of the present application. Solutions or variations thereof which are not obtained by the person skilled in the art without inventive step are also within the scope of protection of the present application.

The pixel circuit is the smallest circuit unit in the display screen, one pixel circuit is equivalent to one sub-pixel (or called sub-pixel) in the display screen, and the display screen comprises a plurality of rows of sub-pixels. Based on the structure of the pixel circuit, the sub-pixels in the display screen are scanned line by line and emit light, so that when displaying a frame of image, the display of the frame of image can be realized only by keeping the light-emitting state after the first row of sub-pixels emit light until the last row of sub-pixels emit light. The GOA is used for controlling the on or off of each row of GOA in the display screen so as to control the input of gating signals for each row of pixel circuits.

Fig. 3 is a circuit diagram of a pixel circuit according to an embodiment of the present application. As shown in fig. 3, the pixel circuit 50 may include a capacitor Cst, a light emitting device L, and a plurality of transistors (M1, M2, M3, M4, M5, M6, M7). For convenience of description, the transistor M1 is referred to as a first reset transistor, the transistor M7 is referred to as a second reset transistor, the transistor M4 is referred to as a driving transistor, the transistor M6 is referred to as a first light emission control transistor, and the transistor M5 is referred to as a second light emission control transistor. It should be noted that this is merely an example of a pixel circuit, and the pixel circuit may also adopt other designs, such as a 2T1C circuit including only 2 transistors and 1 capacitor, a 4T1C circuit including 4 transistors and 1 capacitor, a 5T2C circuit including 5 transistors and 2 capacitors, and the like, and these pixel circuits may be designed to control the on and off of a transistor connected in series with a light emitting device by an EM signal, so as to control the light emission of the light emitting device, which is not limited in this embodiment of the present application.

The light emitting device L may be an Organic Light Emitting Diode (OLED). In this case, the display screen is an OLED display screen. Alternatively, the light emitting device L may be a micro light emitting diode (micro LED). In this case, the display screen is a mirco LED display screen. For convenience of description, the light emitting device L is exemplified as an OLED.

Based on the structure of the pixel circuit 50 shown in fig. 3, the working process of the pixel circuit 50 includes three stages shown in fig. 4-6, namely, a first stage (first), a second stage (second), and a third stage (third). In fig. 4, 5, and 6, for convenience of explanation, the transistors that are turned off are distinguished by adding an "x" mark.

In the first stage (i), under the control of the gate signal GN-1, as shown in fig. 4, the first reset transistor M1 and the second reset transistor M7 are turned on. The initial voltage Vint is transmitted to the gate of the driving transistor M4 through the first reset transistor M1, thereby resetting the gate of the driving transistor M4. In addition, the initial voltage Vint is transmitted to the anode (anode, a) of the OLED through the second reset transistor M7, and the anode a of the OLED is reset. At this time, the voltage Va of the anode a of the OLED, and the voltage Vg4 of the gate g of the driving transistor M4 are Vint.

In this way, in the first stage, the voltages of the gate g of the driving transistor M4 and the anode a of the OLED are reset to the initial voltage Vint, so that the influence of the voltage of the gate g of the driving transistor M4 and the anode a of the OLED remaining in the previous image frame on the next image frame is avoided. Therefore, the first phase (i) may be referred to as a reset phase.

In the second stage, under the control of the gate signal GN, as shown in fig. 5, the transistor M2 and the transistor M3 are turned on. When the transistor M3 is turned on, the gate g and the drain (d) of the driving transistor M4 are coupled, and the driving transistor M4 is in a diode conducting state. At this time, the data voltage Vdata is written to the source s of the driving transistor M4 through the turned-on transistor M2. Therefore, the second stage can be referred to as a data voltage Vdata writing stage of the pixel circuit.

In the third stage, under the control of the emission control signal EM, the second emission control transistor M5 and the first emission control transistor M6 are turned on, and the current path between the high power supply voltage ELVDD and the low power supply voltage ELVSS is turned on. The driving current I generated by the driving transistor M4 is transmitted to the OLED through the above current path to drive the OLED to emit light.

Since the OLED emits light in the third stage, the third stage may be referred to as a light emitting stage. As can be seen from the description of the third stage, the EM signal can control the pixel circuit to be in a light-emitting state or a non-light-emitting state.

The working principle of the GOA circuit in the embodiment of the present application is described below with reference to fig. 7 and 8. Fig. 7 is a schematic structural diagram of a GOA according to an embodiment of the present application. Fig. 8 is a timing diagram of a GOA circuit according to an embodiment of the present disclosure.

As shown in fig. 7, the GOA includes a GCK clock input and a GCB clock input for receiving a GCK clock signal and a GCB clock signal. The GCK clock signal and the GCB clock signal are a pair of clock signals that are inverted with respect to each other. The GCK clock signal and the GCB clock signal may be input to the display screen by the GOA management module in the display driving circuit. The GOA also includes a GN-1 signal input for receiving a strobe signal for a row of pixel circuits on the display screen. The GOA further includes a GN signal output terminal for outputting the gate signal of the pixel circuit of the current row corresponding to the GOA.

The G1 signal, G2 signal, … signal, GN-1 signal, GN signal in fig. 8 represent gate signals of the pixel circuits of the first row to the nth row in the display panel, respectively. I.e., the GN signal and the GN-1 signal correspond to the gate signals GN and GN-1 in fig. 3 to 6. The STV signal represents a start signal. Under the control of the GCK clock signal and the GCB clock signal, after the STV signal is started, the strobe signals G1 and G2 control the pixel circuits of each row to start refreshing in sequence. The GCK controls the gating signals to refresh each row of pixel circuits in sequence until all display areas in the display screen are scanned.

In order to enable a plurality of display areas in a display screen to synchronously display images, a plurality of display driving circuits in a multi-display driving system need to be synchronized in clock. In one clock synchronization scheme, the plurality of display driving circuits may be divided into one main display driving circuit and at least one auxiliary display driving circuit. The main display driving circuit outputs a clock synchronization signal to the sub display driving circuit, and the sub display driving circuit performs clock synchronization of an internal circuit of the sub display driving circuit based on the clock synchronization signal received from the main display driving circuit. For example, the clock synchronization signals may include vertical synchronization (V-Sync) signals and horizontal synchronization (H-Sync) signals. Wherein the vertical synchronization signal is used for performing frame-to-frame synchronization of the scanned image, and the horizontal synchronization signal is used for performing line-to-line synchronization of the scanned image. However, the clock signal in the line scanning each row of pixels is generated by the internal reference clock of each display driving circuit, and the internal clock frequency of different display driving circuits has errors, thereby affecting the display performance of the display screen. For example, the internal clock frequencies of different display driving circuits cannot be completely the same due to differences in operating environments (e.g., temperature, humidity, etc.), and devices themselves

In the prior art, a gate driver on array (GOA) clock signal is generated based on an internal reference clock signal of a display driving circuit, so that there is an error in the frequency of the GOA clock signals of different display driving circuits. The GOA clock signal is used for controlling the GOA of the display screen to be turned on or turned off. For the auxiliary display driving circuit, the GOA clock signal and the horizontal synchronization signal are generated based on different reference clock signals, and during the line scanning time interval, the GOA on time of the display area driven by the auxiliary display driving circuit will be reduced, resulting in insufficient charging time of the pixel circuits in the line, thereby affecting the performance of the display screen. Therein, the GOA clock signal may include the GCK signal and the GCB signal in the example of fig. 7 or 8, as an example.

In order to solve the above problem, embodiments of the present application propose a driving scheme of a multi-display driving system. In the scheme, each display driving circuit in the plurality of display driving circuits receives a first clock signal sent by the main controller and generates a GOA clock signal based on the first clock signal, and because the GOA clock signals output by the plurality of display driving circuits are generated based on the first clock signal, the error of the frequency between the GOA clock signals output by the plurality of display driving circuits is reduced, so that the GOA clock signals among the plurality of display driving circuits can be effectively synchronized in a clock manner, and the display performance of the display screen is improved.

Fig. 9 is a schematic diagram of an electronic device according to an embodiment of the present application, and as shown in fig. 9, the electronic device includes a main controller 110, a display driving circuit 120, a display driving circuit 130, and a display screen 140, and functions of the above modules are described as follows.

The display screen 140: including a first display area 11 and a second display area 12.

The main controller 110: the display device comprises a first clock output end, wherein the first clock output end is used for respectively sending a first clock signal to a first display driving circuit and a second display driving circuit.

As an example, the first clock output may be a MIPI TX interface of the main controller. The interface may output a clock frequency of a high frequency and high stability, for example, a frequency of several tens to several hundreds of mhz.

The first display driver circuit 120: the first clock receiving end is used for receiving the first clock signal; the first display driving circuit 120 further includes a first gate driver array GOA clock signal output end, the first GOA clock signal output end is configured to output a first GOA clock signal to the display screen, and the first GOA clock signal is configured to control the GOA of the first display area to be turned on or off, where the first GOA clock signal is generated based on the first clock signal.

The second display driving circuit 130: the first clock receiving end is used for receiving the first clock signal; the second display driving circuit 130 further includes a second GOA clock signal output end, where the second GOA clock signal output end is configured to output a second GOA clock signal to the display screen, and the second GOA clock signal is configured to control the second display area to turn on or off a GOA, where the second GOA clock signal is generated based on the first clock signal.

For example, in fig. 7 or 8, the first GOA clock signal may be a GCK signal corresponding to the first display region, and the second GOA clock signal may be a GCK signal corresponding to the second display region. Alternatively, the first GOA clock signal may be a GCB signal corresponding to the first display region, and the second GOA clock signal may be a GCB signal corresponding to the second display region. The GCK signal and the GCB signal are a pair of clock signals inverted to each other.

Alternatively, the first GOA clock signal and the second GOA clock signal may be signals having the same phase.

The first GOA clock signal may be generated based on the first clock signal, and may refer to the first GOA clock signal using the first clock signal as a reference clock signal. In one example, the first clock signal may be divided or multiplied to obtain a second clock signal, and the first GOA clock signal may be generated based on the second clock signal. The second GOA clock signal or other clock signals are also similar, and for brevity, are not described again here.

As shown in fig. 10, in one example, the first display driving circuit 120 includes a first GCK signal output terminal and a first GCB signal output terminal for outputting a first GCK signal and a first GCB signal, respectively. The second display driving circuit 130 includes a second GCK signal output terminal and a second GCB signal output terminal. The phases of the first and second GCK signals may be the same. The phases of the first and second GCB signals may be the same. The first GCK signal, the second GCK signal, the first GCB signal and the second GCB signal are all generated based on the first clock signal. In other words, the first GOA clock signal output of fig. 9 includes the first GCK signal output and/or the first GCB output, and the second GOA clock signal output includes the second GCK signal output and/or the second GCB signal output.

Alternatively, each of the plurality of display driving circuits may further generate a vertical synchronization signal (i.e., a V-sync signal) for synchronization between frames of a scanned image based on the first clock signal transmitted by the main controller. As an example, the duration of each time frame may be 16.67ms (milliseconds), i.e. the refresh rate of the display screen is 60Hz (hertz). The frequency of the V-sync is 60 Hz.

With continued reference to fig. 10, in one example, the first display driving circuit further includes a first vertical synchronization signal output terminal (alternatively referred to as a first V-sync signal output terminal) for outputting a first vertical synchronization signal (alternatively referred to as a first V-sync signal). Wherein the first vertical synchronization signal is generated based on the first clock signal, the first vertical synchronization signal being used for frame synchronization of the first display region; the second display driving circuit further includes a second vertical synchronization signal output terminal (alternatively referred to as a second V-sync signal output terminal) for outputting a second vertical synchronization signal (alternatively referred to as a second V-sync signal). Wherein the second vertical synchronization clock signal is generated based on the first clock signal, and the second vertical synchronization signal is used to perform frame synchronization of the second display region. Optionally, the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

Alternatively, each of the plurality of display driving circuits may further generate a horizontal synchronization signal for synchronization between lines of a scanned image based on the first clock signal transmitted by the main controller. As an example, the duration of each time frame may be 16.67ms (milliseconds), i.e. the refresh rate of the display screen is 60 hertz. The frequency of the V-sync is 60 Hz. The frequency of the horizontal synchronization signal is the refresh rate multiplied by the number of rows. For example, if the display screen has 2000 rows of pixels, the frequency of H-sync is 120kHz (kilohertz).

With continued reference to fig. 10, in one example, the first display driving circuit further includes a first horizontal synchronization signal output terminal (alternatively referred to as a first H-sync output terminal) for outputting a first horizontal synchronization signal (alternatively referred to as a first H-sync signal). Wherein the first horizontal synchronization signal is generated based on the first clock signal, the first horizontal synchronization signal being used for line synchronization of the first display region; the second display driving circuit further includes a second horizontal synchronization signal output terminal (alternatively referred to as a second H-sync output terminal) for outputting a second horizontal synchronization signal (alternatively referred to as a second H-sync signal). Wherein the second horizontal synchronization signal is generated based on the first clock signal, the second horizontal synchronization signal is used for performing line synchronization of the second display region, and the first horizontal synchronization signal and the second horizontal synchronization signal are signals having the same phase.

As an example, the vertical synchronization signal and the horizontal synchronization signal output by the display driving circuit may also adopt a scheme in the related art, that is, the auxiliary display driving circuit generates the vertical synchronization signal and the horizontal synchronization signal based on the clock signal output by the main display driving circuit. In this scheme, although there is an error between the vertical synchronization signal (or the horizontal synchronization signal) and the GOA clock signal received by different display areas of the display screen, since the GOA clock signals received by different display areas are synchronized, the time error between the vertical synchronization signal (or the horizontal synchronization signal) and the GOA clock signal is fixed in the time interval of each frame (or each line) and does not accumulate with the increase of time, so the influence on the display performance of the display screen is limited.

With continued reference to fig. 10, in one example, the first display driving circuit further includes a first EM signal output for outputting a first EM signal to the display screen, the first EM signal for controlling the pixel circuits in the first display region to emit or not to emit light, wherein the first EM signal is generated based on the first clock signal; the second display driving circuit further includes a second EM signal output terminal for outputting a second EM signal for controlling the pixel circuit in the second display region to emit or not to emit light to the display screen, wherein the second EM signal is generated based on the first clock signal.

Fig. 11 is a schematic structural diagram of a display driving circuit according to an embodiment of the present application. The display driver circuit in fig. 11 may be applied to the display driver circuit 120 and/or the display driver circuit 130 in fig. 1, 2, 9, or 10. As shown in fig. 10, the display driving circuit includes, but is not limited to, the following modules: the system comprises a video processing module, a clock processing module, an internal clock generating module, a GOA management module and an EM management module. It should be noted that the structure in fig. 11 is only an example and is not limited, and the display driving circuit may include more or less functional modules than the above modules, for example, the display driving circuit may further include a power management module, and the like, and the operation principle of each module and the connection relationship between the modules may be expanded and modified according to practical applications, which is not limited in this embodiment of the present application.

The video processing module is used for receiving video data sent by the main controller, processing the video data and generating a video source signal. The video processing module comprises a digital circuit part and an analog circuit part, and the video data is processed by the digital circuit and the analog circuit in sequence.

Fig. 12 is a schematic structural diagram of a digital circuit of a video processing module of a display driver circuit according to an embodiment of the present application. As shown in fig. 12, the digital circuit portion may include, but is not limited to: frame buffers (frame buffers), decoders (decoders), pixel pipelines (pixel pipelines). Wherein the pixel pipeline comprises a plurality of digital modules for pipeline processing of pixel data, such as a digital module for brightness adjustment, etc. The video data may be processed sequentially through the frame buffer, decoder, and pixel pipeline.

The video data stream after being processed by the digital circuit part needs to be processed by the analog circuit part to be output to the display screen. Fig. 13 is a schematic structural diagram of an analog circuit of a video processing module of a display driver circuit according to an embodiment of the present application. As shown in fig. 13, the analog circuit portion includes, but is not limited to, a shift register (shift register), a data latch, a digital to analog converter (DAC), a data output buffer, and the like. The video data stream processed by the digital circuit can be processed by modules such as a shift register, a data latch, a DAC, a data output buffer and the like in sequence, and then a video source signal is generated.

With continued reference to fig. 11, in an example, the clock processing module receives a first clock signal sent by a host controller, generates a second clock signal based on the first clock signal, and outputs the second clock signal to the GOA management module as a reference clock signal of the GOA management module. The GOA management module generates a GOA clock signal based on the second clock signal, which may include the GCK signal and/or the GCB signal described above.

In one example, the clock processing module may include a clock divider circuit. The display driving circuit needs to perform frequency division processing on the first clock signal to obtain a second clock signal with a low frequency, and then the second clock signal is used as a reference clock signal inside the display driving circuit.

With continued reference to fig. 11, in one example, an EM management module may be further included in the display driving circuit, and the EM management module may generate an EM signal based on the second clock signal, where the EM signal is used to control a pixel circuit in a display screen to emit light or not to emit light.

In one possible approach, the display driver circuit may use the first clock signal as a master reference clock signal internal to the display driver circuit. For example, the first clock signal may be used as a clock signal for a digital circuit portion and a module circuit portion in a video processing module. However, since the clock signals in the display driving circuit are generated based on the same clock signal, the frequency range of the clock signals in the display driving circuit is not flexible and adjustable, and therefore, problems such as timing convergence and electromagnetic interference (EMI) are caused to the display driving circuit.

In order to avoid the above problem, in the embodiment of the present application, the display driving circuit may use the third clock signal generated by the internal clock generating module as the reference clock signal of the digital circuit portion of the display driving circuit. And the first clock signal may be used as a reference clock signal for an analog circuit part of the display driving circuit, the EM management module, and/or the GOA management module.

With continued reference to fig. 11, in one example, the internal clock generation module is configured to generate a third clock signal that can be used as a reference clock signal for digital circuit portions of the video processing module, such as a frame buffer, a decoder, and a digital module in a pixel pipeline. The third clock signal is a clock signal generated inside the display driving circuit, and in one example, the internal clock generating module includes an Oscillator (OSC).

With continued reference to fig. 11, in one example, the first clock signal may serve as a reference clock signal for an analog circuit portion of the video processing module. As an example, the clock processing module may divide the first clock signal into a second clock signal, and the second clock signal may be used as a reference signal of an analog circuit portion in the video processing module. For example, the second clock signal may be used to control a shift register and an analog circuit block following the shift register.

As shown in fig. 11, since the reference clock signal of the digital circuit and the reference clock of the back-end analog circuit are decoupled, in order to compensate for a timing error that may occur between different reference clocks, a first buffer (buffer) may be added between the digital circuit part and the analog circuit part, and the first buffer may be used to compensate for a time delay between the digital circuit part and the analog circuit part due to a difference in the reference clock signal. The first buffer receives the second clock signal and the third clock signal, and performs buffering processing on input video data according to the clock signals to compensate timing errors. Fig. 14 is a schematic diagram of a video processing module in a display driving circuit according to an embodiment of the present application. As shown in fig. 14, the buffer may be provided between the pixel pipeline block of the digital circuit portion and the shift register of the analog circuit portion as an example.

It should be noted that, in fig. 11, the second clock signal may be further subjected to frequency division, frequency multiplication, or other types of processing one or more times before being input to each of the video processing modules, and the second clock signal is taken as an example in the embodiment of the present application for description. Alternatively, in some examples, the display driving circuit may directly input the first clock signal into each block as the reference clock signal without performing frequency division, frequency multiplication, or the like on the first clock signal. In other words, the clock processing blocks in fig. 11 are only examples, and the first clock signal may not be processed before being input to each block, or may be processed by dividing and multiplying the frequency multiple times. In fig. 11, the second clock signal may represent one or more clock signals, that is, the second clock signal input to each module may be the same signal with the same frequency or may be a plurality of signals with different frequencies, and the second clock signal is merely an exemplary illustration of the clock signal generated based on the first clock signal. Similarly, the third clock signal is merely an exemplary illustration of a clock signal generated based on the internal clock signal of the display driving circuit.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An electronic device, comprising:

a display screen including a first display area and a second display area;

the main controller comprises a first clock output end, and the first clock output end is used for respectively sending a first clock signal to the first display driving circuit and the second display driving circuit;

the first display driving circuit comprises a first clock receiving end, and the first clock receiving end is used for receiving the first clock signal;

the first display driving circuit further comprises a first GOA clock signal output end, wherein the first GOA clock signal output end is used for outputting a first GOA clock signal to the display screen, and the first GOA clock signal is used for controlling the on or off of the GOA of the first display area, and the first GOA clock signal is generated based on the first clock signal;

the second display driving circuit comprises a second clock receiving end, and the second clock receiving end is used for receiving the first clock signal;

the second display driving circuit further comprises a second GOA clock signal output end, wherein the second GOA clock signal output end is used for outputting a second GOA clock signal to the display screen, and the second GOA clock signal is used for controlling the second display area to be on or off, and the second GOA clock signal is generated based on the first clock signal.

2. The electronic device according to claim 1, wherein the first display driving circuit further includes a first vertical synchronization signal output terminal for outputting a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is generated based on the first clock signal, the first vertical synchronization signal being used for frame synchronization of the first display region;

the second display driving circuit further includes a second vertical synchronization signal output terminal configured to output a second vertical synchronization signal to the display screen, where the second vertical synchronization signal is generated based on the first clock signal, the second vertical synchronization signal is used to perform frame synchronization of the second display region, and the first vertical synchronization signal and the second vertical synchronization signal are signals having the same phase.

3. The electronic device according to claim 1 or 2, wherein the first display driving circuit further comprises a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal is generated based on the first clock signal, the first horizontal synchronization signal being used for line synchronization of the first display region;

the second display driving circuit further includes a second horizontal synchronization signal output terminal for outputting a second horizontal synchronization signal to the display screen, wherein the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used for performing line synchronization of the second display region.

4. The electronic device according to claim 1 or 2, wherein the first display driving circuit further comprises a first emission EM signal output terminal for outputting a first EM signal for controlling the pixel circuit in the first display region to emit light or not to emit light to the display screen, wherein the first EM signal is generated based on the first clock signal;

the second display driving circuit further includes a second EM signal output terminal for outputting a second EM signal to the display screen, the second EM signal being for controlling the pixel circuit in the second display region to emit or not to emit light, wherein the second EM signal is generated based on the first clock signal.

5. The electronic device as claimed in claim 1 or 2, wherein the first display driving circuit comprises a video processing module, the video processing module is configured to process video data input by the main controller to generate a video source signal sent to the display screen, the reference clock of the digital circuit in the video processing module is a third clock signal generated by the internal clock generating module of the first display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

6. The electronic device of claim 5, wherein a first buffer is disposed in the video processing module, the first buffer disposed between digital circuitry and analog circuitry in the video processing module.

7. A display driving circuit, comprising:

the first clock receiving end is used for receiving a first clock signal sent by the main controller;

a first GOA clock signal output end, configured to output a first GOA clock signal to a display screen, where the first GOA clock signal is used to control a GOA of the display screen to be turned on or off, and the first GOA clock signal is generated based on the first clock signal;

the display driving circuit further includes a first vertical synchronization signal output terminal configured to output a first vertical synchronization signal to the display screen, where the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the display screen.

8. The display driving circuit according to claim 7, wherein the display driving circuit further comprises a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used for line synchronization of the display screen.

9. The display driving circuit according to claim 7 or 8, further comprising a first emission EM signal output terminal for outputting a first EM signal for controlling a pixel circuit of the display screen to emit light or not to emit light to the display screen, wherein the first EM signal is generated based on the first clock signal.

10. The display driving circuit according to claim 7 or 8, wherein the display driving circuit comprises a video processing module, the video processing module is configured to process video data input by the main controller to generate a video source signal sent to the display screen, a reference clock of a digital circuit in the video processing module is a third clock signal generated by an internal clock generation module of the display driving circuit, and a reference clock of an analog circuit in the video processing module is the first clock signal.

11. The display driver circuit according to claim 10, wherein a first buffer is provided in the video processing module, the first buffer being provided between a digital circuit and an analog circuit in the video processing module.

12. A method of driving a display panel, the display panel including a first display region and a second display region, the method comprising:

the main controller respectively sends a first clock signal to the first display driving circuit and the second display driving circuit;

the first display driving circuit outputs a first GOA clock signal to the display screen, wherein the first GOA clock signal is used for controlling the GOA of the first display area to be turned on or turned off, and the first GOA clock signal is generated based on the first clock signal;

the second display driving circuit outputs a second GOA clock signal to the display screen, wherein the second GOA clock signal is used for controlling the GOA of the second display area to be turned on or off, and the second GOA clock signal is generated based on the first clock signal.

13. The method of claim 12, wherein the method further comprises: the first display driving circuit outputs a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used for performing frame synchronization of the first display area;

the second display driving circuit outputs a second vertical synchronization signal to the display screen, wherein the second vertical synchronization signal is generated based on the first clock signal, the second vertical synchronization signal is used for performing frame synchronization of the second display area, and the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.

14. The method of claim 12 or 13, wherein the first display driving circuit further comprises a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal is generated based on the first clock signal, the first horizontal synchronization signal being used for line synchronization of the first display region;

15. The method of claim 12 or 13, wherein the first display driving circuit further comprises a first emission EM signal output terminal for outputting a first EM signal to the display screen, the first EM signal for controlling a pixel circuit in the first display region to emit light or not, wherein the first EM signal is generated based on the first clock signal;

16. The method as claimed in claim 12 or 13, wherein the first display driving circuit comprises a video processing module, the video processing module is configured to process video data input by the main controller to generate a video source signal to be transmitted to the display screen, the reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generating module of the first display driving circuit, and the reference clock of the analog circuit in the video processing module is the first clock signal.

17. The method of claim 16, wherein a first buffer is disposed in the video processing module, the first buffer disposed between digital circuitry and analog circuitry in the video processing module.

18. A display module, comprising:

a display screen including a first display area and a second display area;

the first display driving circuit comprises a first clock receiving end, wherein the first clock receiving end is used for receiving a first clock signal sent by the main controller;

19. The display module as claimed in claim 18, wherein the first display driving circuit further comprises a first vertical synchronization signal output terminal for outputting a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used for performing frame synchronization of the first display region;

20. The display module according to claim 18 or 19, wherein the first display driving circuit further comprises a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used for performing line synchronization of the first display region;

21. The display module according to claim 18 or 19, wherein the first display driving circuit further comprises a first emission EM signal output terminal for outputting a first EM signal to the display screen, the first EM signal being for controlling the pixel circuit in the first display region to emit light or not, wherein the first EM signal is generated based on the first clock signal;

the second display driving circuit further includes a second EM signal output terminal for outputting a second EM signal for controlling the pixel circuit in the second display region to emit or not to emit light to the display screen, wherein the second EM signal is generated based on the first clock signal.

22. The display module as claimed in claim 18 or 19, wherein the first display driving circuit comprises a video processing module, the video processing module is configured to process video data input by the main controller to generate a video source signal sent to the display screen, a reference clock of a digital circuit in the video processing module is a third clock signal generated by the internal clock generating module of the first display driving circuit, and a reference clock of an analog circuit in the video processing module is the first clock signal.

23. The display module of claim 22, wherein a first buffer is disposed in the video processing module, the first buffer being disposed between the digital circuitry and the analog circuitry in the video processing module.