CN111600576A - Synchronous trigger pulse generating circuit - Google Patents

Synchronous trigger pulse generating circuit Download PDF

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Publication number
CN111600576A
CN111600576A CN202010341374.5A CN202010341374A CN111600576A CN 111600576 A CN111600576 A CN 111600576A CN 202010341374 A CN202010341374 A CN 202010341374A CN 111600576 A CN111600576 A CN 111600576A
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voltage comparator
voltage
wave signal
input end
square wave
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CN202010341374.5A
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CN111600576B (en
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王承超
盛庆华
绳春旭
李竹
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Hangzhou Dianzi University
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Hangzhou Dianzi University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a synchronous trigger pulse generating circuit, wherein a waveform output circuit comprises a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the in-phase input end of the first voltage comparator is connected with a sine wave signal, the reverse input end of the first voltage comparator is connected with a zero voltage, and the output end of the first voltage comparator outputs a first square wave signal VOUT _1 through a first RC filter; the non-inverting input end of the second voltage comparator is connected with the first square wave signal VOUT _1, and the inverting input end of the second voltage comparator is connected with the low-level reference voltage VrefThe output end of the second voltage comparator outputs a second square wave signal VOUT _2 through a second RC filter; the non-inverting input end of the first voltage comparator is connected to the second square wave signal VOUT _2, the inverting input end of the first voltage comparator is connected to the first square wave signal VOUT _1, and the output end of the third voltage comparator outputs a synchronous pulse signal. The invention has the advantages of small volume, simple structure, strong stability and the like, and the phase of the output synchronous pulse signal is synchronous with the phase of the input variable-frequency sine wave signalAnd the detection of the sensor circuit at the later stage is facilitated.

Description

Synchronous trigger pulse generating circuit
Technical Field
The invention belongs to the field of signal conversion, and particularly relates to a synchronous trigger pulse generating circuit.
Background
In the application of signal and information processing technology, it is often necessary to convert the frequency-variable and amplitude-variable sine wave signal input at the front end into a high-precision synchronous pulse signal as a trigger excitation, and send the high-precision synchronous pulse signal to a rear-end acquisition card to trigger the acquisition card to work. The traditional analog circuit or Schmitt trigger is adopted to convert sine waves into pulse output signals, the requirements on the amplitude and the frequency of input waveforms are high, the generated pulse signals have obvious hysteresis, rear-end acquisition is influenced, and the requirements on synchronous and high-precision signal acquisition at the present stage cannot be met; on the other hand, if an FPGA (Field Programmable gate array) is used to generate the synchronous pulse control signal, a large number of peripheral devices and high-precision digital processing chips including a signal receiving unit, a parameter processing unit, a phase-locked loop unit (PLL unit), a pulse generating unit, a pulse output unit, etc. are required, and although the pulse signal meeting the acquisition requirement can be generated, the FPGA is expensive in manufacturing cost, large in size, and cannot be widely installed in the sensing signal acquisition device.
In view of the above situation, it is desirable to design a synchronous pulse signal generating circuit that meets the requirement of high-precision acquisition while reducing the production cost by changing the conventional technical defects.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a synchronous trigger pulse generating circuit, which utilizes a comparator to generate a synchronous pulse signal, thereby overcoming the defects of poor stability and high delay of the pulse signal generated by the traditional gate circuit simulation technology and simultaneously reducing the circuit cost.
In order to solve the technical problems in the prior art, the technical scheme of the invention is as follows:
a synchronous trigger pulse generating circuit at least comprises a power supply converting circuit and a waveform output circuit, wherein,
the power supply conversion circuit is used for providing power supply voltage and comparison reference voltage for the waveform output circuit;
the waveform output circuit comprises a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the non-inverting input end of the first voltage comparator is connected with a sine wave signal which isThe reverse input end is connected with zero voltage, and the output end of the first voltage comparator outputs a first square wave signal VOUT _1 through a first RC filter; the non-inverting input end of the second voltage comparator is connected with the first square wave signal VOUT _1, and the inverting input end of the second voltage comparator is connected with the low-level reference voltage VrefThe output end of the second voltage comparator outputs a second square wave signal VOUT _2 through a second RC filter; the non-inverting input end of the first voltage comparator is connected with the second square wave signal VOUT _2, the inverting input end of the first voltage comparator is connected with the first square wave signal VOUT _1, and the output end of the third voltage comparator outputs a synchronous pulse signal;
the positive power supply input end of the first voltage comparator inputs +2.5V, the negative power supply input end inputs-1.2V, the high level of the first square wave signal VOUT _1 is +2.5V, and the low level thereof is-1.2V;
the positive power supply input end of the second voltage comparator inputs +3.3V, the negative power supply input end of the second voltage comparator inputs 0V, the high level of a second square wave signal VOUT _2 is +3.3V, and the low level of the second square wave signal VOUT _2 is 0V;
in the third voltage comparator, +3.3V is input to the positive power supply input end of the comparator, 0V is input to the negative power supply input end of the comparator, the high level of the synchronous pulse signal is +3.3V, and the low level of the synchronous pulse signal is 0V.
As a further improvement scheme, the first RC filter and the second RC filter are series resistors and parallel capacitors to form an RC low-pass filter and are used for filtering high-frequency noise and periodic fluctuating signals to obtain square wave signals with the rising edges becoming slow.
As a further improvement, a current-limiting resistor is arranged at the non-inverting input terminal of the second voltage comparator and the inverting input terminal of the third comparator.
As a further improvement scheme, the pulse width of the synchronous pulse signal is between several ns and tens of ns.
As a further improvement, the power conversion circuit at least comprises three independent DC-DC conversion circuits for respectively supplying power to the comparators in the waveform output circuit.
As a further improvement scheme, the power conversion circuit further comprises a resistance voltage division circuit which utilizes series voltage division to output voltage in the range of 0-2.5VLow level reference voltage Vref。
As a further improvement scheme, the variable-frequency amplitude sine wave generator further comprises a buffer circuit, wherein the buffer circuit is used for outputting the input variable-frequency amplitude sine wave signal into a low-impedance sine wave signal without bias voltage.
In the technical scheme, an input variable-frequency sine wave signal passes through a voltage follower to generate a low-impedance sine wave without a bias signal, and then the low-impedance sine wave is input to a homodromous input end of a first voltage comparator, an output signal of the first voltage comparator passes through an RC filter to generate a square wave signal VOUT _1 with a high level of +2.5V and a low level of-1.2V, then the square wave signal VOUT _1 is input to a homodromous input end of a second voltage comparator and is compared with a low-level voltage signal Vref input to an inverse input end of the second voltage comparator, an output signal of the second voltage comparator passes through the RC filter to output a square wave signal VOUT _2 with a high level of +3.3V and a low level of 0V, because a fixed phase difference exists between the square wave signal VOUT _1 and VOUT _2, the signal VOUT _1 output by the first voltage comparator is input to a positive input end of a third voltage comparator, the square wave signal VOUT _2 output by the second voltage comparator is, the third voltage comparator can generate a synchronous pulse signal, the pulse has the same phase with the input sine wave, so that the detection of a post-stage sensor circuit is convenient, and the chip power supply in the whole circuit process is provided by a power supply conversion circuit in the system.
Compared with the prior art, the technical scheme of the invention is adopted, the input variable frequency sine wave signal generates a non-bias low-impedance sine wave through the voltage follower, the square wave signal VOUT _1 and the square wave signal VOUT _2 with corresponding levels are generated through the comparator input by two different power sources, and the difference value of two rising edges can be output as an output synchronous pulse signal through the comparator due to the fixed phase difference between the two signals. The invention has the advantages of small volume, simple structure and strong stability, and the output synchronous pulse signal is synchronous with the phase of the input variable frequency sine wave signal, thereby facilitating the detection of a post-stage sensor circuit.
Drawings
FIG. 1 is a schematic circuit diagram of the system of the present invention;
FIG. 2 is a schematic diagram of the power conversion circuit of FIG. 1;
FIG. 3 is a schematic diagram of the resistor divider circuit of FIG. 1;
FIG. 4 is a schematic diagram of the buffer circuit of FIG. 1;
FIG. 5 is a schematic diagram of the waveform output circuit of FIG. 1;
Detailed Description
The invention will be further explained with reference to the drawings.
Referring to fig. 1, the present invention provides a circuit for converting a sine wave into a synchronous control pulse for output, which is mainly composed of a power conversion circuit, a resistance voltage division circuit, an isolation input circuit, a waveform output circuit, and the like. The power supply conversion circuit is used for providing power supply voltage and comparison reference voltage for the waveform output circuit;
the waveform output circuit comprises a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the non-inverting input end of the first voltage comparator is connected with a sine wave signal, the inverting input end of the first voltage comparator is connected with a zero voltage, and the output end of the first voltage comparator outputs a first square wave signal VOUT _1 through a first RC filter; the non-inverting input end of the second voltage comparator is connected with the first square wave signal VOUT _1, and the inverting input end of the second voltage comparator is connected with the low-level reference voltage VrefThe output end of the second voltage comparator outputs a second square wave signal VOUT _2 through a second RC filter; the non-inverting input end of the first voltage comparator is connected with the second square wave signal VOUT _2, the inverting input end of the first voltage comparator is connected with the first square wave signal VOUT _1, and the output end of the third voltage comparator outputs a synchronous pulse signal;
the power conversion circuit at least comprises three independent DC-DC conversion circuits which are used for respectively supplying power to comparators in the waveform output circuit. The power supply conversion circuit respectively outputs voltages of +3.3V, +2.5V and-1.2V with high precision and low noise to respectively supply power to a positive power supply input end, a negative power supply input end and a low-voltage level signal of a comparator in the waveform output circuit;
in the first voltage comparator, a positive power supply input end of a comparator inputs +2.5V, a negative power supply input end inputs-1.2V, an output end is connected with a series resistor and a parallel capacitor to form an RC low-pass filter to filter high-frequency noise and periodic fluctuation signals, and a square wave signal VOUT _1 with a slow rising edge is obtained, wherein the high level of the signal is +2.5V, and the low level of the signal is-1.2V;
the positive power input end of a comparator in the second voltage comparator inputs +3.3V, the negative power input end inputs 0V, because the voltage source of the second voltage comparator is different from that of the first voltage comparator, a current-limiting resistor needs to be added at the non-inverting input end of the comparator to prevent the comparator from being burnt, the output end of the comparator is connected with a series resistor and a parallel capacitor to form an RC filter to filter high-frequency noise and periodic fluctuation signals, and a square wave signal VOUT _2 with a gentle rising edge is obtained, the high level of the signal is +3.3V, and the low level of the signal is 0V;
the positive power input end of a comparator in the third voltage comparator inputs +3.3V, the negative power input end of the comparator inputs 0V, and because the voltage source of the third voltage comparator is different from that of the first voltage comparator, a current-limiting resistor needs to be added at the non-inverting input end of the comparator to prevent the comparator from being burnt, and the output end outputs a synchronous pulse signal with the peak value of 3.3V.
The first RC filter and the second RC filter are series resistors and parallel capacitors to form an RC low-pass filter and are used for filtering high-frequency noise and periodic fluctuating signals to obtain square signals with gentle rising edges.
Because the voltage source of the second voltage comparator is different from that of the first voltage comparator, a current-limiting resistor needs to be added at the non-inverting input end of the comparator to prevent the comparator from being burnt; since the voltage source of the third voltage comparator is different from that of the first voltage comparator, a current-limiting resistor needs to be added at the non-inverting input end of the comparator to prevent the comparator from being burnt. As a further improvement scheme, a current limiting resistor is arranged at the non-inverting input end of the second voltage comparator and the inverting input end of the third comparator.
As a further improvement scheme, the pulse width of the synchronous pulse signal is between several ns and tens of ns.
As a further improvement scheme, the power conversion circuit further comprises a resistance voltage division circuit which utilizes series voltage division to output a low-level reference voltage V in the range of 0-2.5Vref。
As a further improvement scheme, the variable-frequency amplitude sine wave generator further comprises a buffer circuit, wherein the buffer circuit is used for outputting the input variable-frequency amplitude sine wave signal into a low-impedance sine wave signal without bias voltage.
Referring to fig. 2, a schematic diagram of the power conversion circuit of the present invention is shown, which respectively outputs +3.3V, +2.5V, -1.2V levels for providing power to the voltage comparator, and the power conversion circuit further includes a voltage input terminal JP1, a precision adjustable potentiometer RP1, a precision adjustable potentiometer RP2, a precision adjustable potentiometer RP3, a first linear voltage stabilizing chip U1, a second linear voltage stabilizing chip U2, a third linear voltage stabilizing chip U3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first patch capacitor C1, a second patch capacitor C2, a third patch capacitor C3, a first patch capacitor C4, a first patch capacitor C5, a first patch capacitor C6, a first patch capacitor C7, a first capacitor C2, a first patch capacitor C867, a first capacitor C3687458, a first capacitor C368672, the voltage stabilizing circuit comprises a first patch capacitor C12, a first patch capacitor C13, a first patch capacitor C14, a first patch capacitor C15, a first patch capacitor C16, a first patch capacitor C17, a first patch capacitor C18, a first patch capacitor C19, a first patch capacitor C20, a first patch capacitor C21 and a first patch capacitor C22, wherein a voltage input terminal JP1 is KF301-5.0-3P, a first linear voltage stabilizing chip U1 and a second linear voltage stabilizing chip U2 are TPS7A4701RGWR, and a third linear voltage stabilizing chip is TPS7A3301 RGWT.
In the power conversion circuit, a voltage input terminal JP1 is connected with an external input voltage, a first pin JP1 is connected with an external input of-5V, a third pin is connected with an external input of +5V, a second pin is connected with one end of a first resistor R1, and the other end of the first resistor R1 is connected with a ground wire; one end of the first chip capacitor C1 and one end of the second chip capacitor C2 are connected with +5V, and the other ends of the first chip capacitor C1 and the second chip capacitor C2 are grounded; one ends of the third chip capacitor C3 and the fourth chip capacitor C4 are connected with-5V, and the other ends of the third chip capacitor C3 and the fourth chip capacitor C4 are connected with a ground wire; the 15 pin and the 16 pin of the first linear voltage-stabilizing chip U1 are connected with +5V of chip power supply input, and are simultaneously connected with one end of a fifth chip capacitor C5 and one end of a sixth chip capacitor C6, the other end ground wires of the fifth chip capacitor C5 and the sixth chip capacitor C6 are connected with the 1 pin and the 20 pin of the linear voltage-stabilizing chip U1 which are connected with +3.3V of power supply output, and are simultaneously connected with one end of a seventh chip capacitor C7, an eighth chip capacitor C8, a ninth chip capacitor C9 and a second resistor R2, wherein the other end ground wires of the seventh chip capacitor C7 and the eighth chip C8 are connected with the other end of the ninth chip capacitor C9 which is connected with the 3 pin of the linear voltage-stabilizing chip U1, the other end of the second resistor R2 is connected with the first pin of a precision adjustable potentiometer RP1, the 3 pin of the first linear voltage-stabilizing chip U1 is connected with the second pin and the third pin of the potentiometer 1 and the third pin R3, the other end of the third resistor R3 is grounded, a 14 pin of the linear voltage stabilization chip U1 is connected with one end of a tenth chip capacitor C10, the other end of the tenth chip capacitor C10 is grounded, 2, 7, 17, 18, 19 and 21 ground wires of the linear voltage stabilization chip U1, and the rest pins are placed in a suspended mode; the pins 15 and 16 of the second linear voltage-stabilizing chip U2 are connected with +5V of chip power input, and are connected with one end of an eleventh patch capacitor C11 and one end of a twelfth patch capacitor C12, the ground wires at the other ends of the eleventh patch capacitor C11 and the twelfth patch capacitor C12 are connected with the pins 1 and 20 of the linear voltage-stabilizing chip U2 which are connected with +2.5V of power output, and are connected with one ends of a thirteenth patch capacitor C13, a fourteenth patch capacitor C14, a fifteenth patch capacitor C15 and a fourth resistor R4, wherein the ground wires at the other ends of the thirteenth patch capacitor C13 and the fourteenth patch capacitor C14 are connected with the other end of the fifteenth patch capacitor C15 which is connected with the pin 3 of the linear voltage-stabilizing chip U2, the other end of the fourth resistor R4 is connected with the first pin of the precision adjustable potentiometer RP2, the pin 3 of the second linear voltage-stabilizing chip U2 is connected with the second pin and the third pin of the potentiometer 2, meanwhile, the other end of the fifth resistor R5 is connected with a ground wire, a 14 pin of the linear voltage stabilization chip U2 is connected with one end of a sixteenth patch capacitor C16, the other end of the sixteenth patch capacitor C16 is connected with the ground wire, 2, 7, 17, 18, 19 and 21 ground wires of the linear voltage stabilization chip U2, and the rest pins are placed in a suspended mode; the 15 pin and the 16 pin of the third linear voltage-stabilizing chip U3 are connected with +5V of chip power supply input, and are simultaneously connected with one end of a seventeenth patch capacitor C17 and one end of an eighteenth patch capacitor C18, the other ends of the seventeenth patch capacitor C17 and the eighteenth patch capacitor C18 are grounded, the 1 pin and the 20 pin of the linear voltage-stabilizing chip U3 are connected with-1.2V of power supply output, and are simultaneously connected with one ends of a nineteenth patch capacitor C19, a twentieth patch capacitor C20, a twenty-first patch capacitor C21 and a sixth resistor R6, wherein the other ends of the nineteenth patch capacitor C19 and the twentieth patch capacitor C20 are grounded, the other end of the twenty-first patch capacitor RP 21 is connected with the 3 pin of the linear voltage-stabilizing chip U3, the other end of the sixth resistor R6 is connected with a first pin of the precision adjustable potentiometer 3, the 3 pin of the third linear voltage-stabilizing chip U3 is connected with the second pin and the third pin of the potentiometer RP3, meanwhile, the other end of the seventh resistor R7 is connected with a ground wire, a 14 pin of the linear voltage stabilization chip U3 is connected with one end of a twenty-second chip capacitor C22, the other end of the twenty-second chip capacitor C22 is connected with a ground wire, 2, 7, 17, 18, 19 and 21 ground wires of the linear voltage stabilization chip U3, and the rest pins are placed in a suspended mode;
referring to fig. 3, a schematic diagram of the resistance voltage divider circuit according to the present invention is shown, in which a resistance is used to divide the +2.5V voltage output by the power conversion circuit to obtain a low level voltage Vref, and the resistance voltage divider circuit further includes an eleventh resistor R11, a twelfth resistor R12, a twenty-ninth chip capacitor C29, and a thirty-eighth chip capacitor C30;
one end of an eleventh resistor R11 in the resistor voltage division circuit is connected with +2.5V output by a linear voltage stabilizing chip U2 in the power conversion circuit, and the other end of the eleventh resistor R11 is connected with a low-level signal output Vref; one end of the twenty-ninth chip capacitor C29 is connected with +2.5V output by a linear voltage stabilizing chip U2 in the power conversion circuit, and the other end is connected with a ground wire; one end of the twelfth resistor R12 and one end of the thirtieth chip capacitor C30 are connected with a low level signal output Vref, and the other end is connected with a ground wire;
because the sine wave signal output by the sensor system in the general sense is a signal with a constantly changing peak-to-peak value, the signal bandwidth is between 1MHz and 10MHz, and a signal to be processed with burrs and noise needs to be reduced in output impedance through a filter capacitor and a voltage follower, and then is output to a comparator after being processed. Referring to fig. 4, a schematic diagram of a buffer circuit according to the present invention is shown, in which an input sine wave signal is filtered by an RC high pass filter and then connected to a positive input terminal of an operational amplifier, so as to output a signal OPAOUT; the voltage follower formed by the operational amplifier has the characteristics of high input impedance and low output impedance, blocks direct current and alternating current, isolates front and rear stage circuits, eliminates the mutual influence between the front and rear stage circuits, effectively reduces the consumption of signals and reduces the interference on a rear stage comparator.
The buffer circuit further comprises a first signal input terminal SIN _1, a fourth operational amplifier chip U4, an eighth patch resistor R8, a ninth patch resistor R9, a tenth patch resistor R10, a twenty-third patch capacitor C23, a twenty-fourth patch capacitor C24, a twenty-fifth patch capacitor C25, a twenty-sixth patch capacitor C26, a twenty-seventh patch capacitor C27 and a twenty-eighth patch capacitor C28, wherein the fourth operational amplifier chip is an OPA690, and the first signal input terminal SIN _1 is an SMA _ KE female socket.
The second pin of the signal input terminal SIN _1 of the isolated input module is connected to an analog ground, the first pin is connected to one end of a twenty-third chip capacitor C23, the other end of the twenty-third chip capacitor C23 is connected to the 3 pin of a fourth operational amplifier chip U4 and is also connected to one end of a ninth resistor R9, the other end of the ninth resistor R9 is connected to the analog ground, the 7 and 8 pins of the fourth operational amplifier chip U4 are connected to the positive power input +5V of the chip, the 4 pin is connected to the negative power input-5V of the chip, the 2 pin is connected to an eighth resistor R8, and the other end of the eighth resistor R8 is connected to the 6 pin of the operational amplifier chip U4, namely, the isolated sine wave signal OPAOUT is output; one end of the tenth resistor R10 is connected with the analog ground, and the other end is connected with the ground wire; one end of the twenty-fourth patch capacitor C24 and one end of the twenty-fifth patch capacitor C25 are connected with +5V of power input, and the other end of the twenty-fourth patch capacitor C24 and the other end of the twenty-fifth patch capacitor C25 are connected with analog ground; one end of the twenty-sixth patch capacitor C26 and one end of the twenty-seventh patch capacitor C27 are connected with a power input of-5V, and the other end of the twenty-sixth patch capacitor C26 and the other end of the twenty-seventh patch capacitor C27 are connected with an analog ground; one end of the twenty-eighth patch capacitor C28 is connected with the +5V power input, and the other end is connected with the-5V power input.
The waveform output circuit outputs a square wave signal VOUT _1 from an OPAOUT sine wave signal with low impedance through a first voltage comparator and an RC filter to form a first voltage comparator; the output square wave signal VOUT _1 passes through a current-limiting resistor and then is input to the non-inverting input end of a second voltage comparator, and a low-level voltage signal VrefInputting the square wave signal VOUT _2 to the inverting input end of the second voltage comparator, and outputting the square wave signal VOUT _2 through the second voltage comparator and the RC filter to form a second voltage comparator; the square wave signal VOUT _1 passes through the current-limiting resistor and then is input to the non-inverting input end of the third voltage comparator, the square wave signal VOUT _2 is input to the inverting input end of the second voltage comparator, and the synchronous pulse signal is output through the second voltage comparator to form the third voltage comparator.
Referring to fig. 5, which is a schematic diagram of a waveform output circuit of the present invention, the obtained isolated input sine wave is transformed and shaped to generate a synchronous pulse signal and output the synchronous pulse signal, the comparator circuit further includes a fifth voltage comparator chip U5, a sixth voltage comparator chip U6, a seventh voltage comparator chip U7, a second signal output terminal OUT _1, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a thirty-first chip capacitor C31, a thirty-second chip capacitor C32, a thirty-third chip capacitor C33, a thirty-fourth chip capacitor C34, a thirty-fifth chip capacitor C35, a thirty-sixth chip capacitor C36, a thirty-seventh chip capacitor C37, a thirty-eighth chip capacitor C38, a ninth chip capacitor C39, and a forty-fourth chip capacitor C40; the fifth voltage comparator chip U5, the sixth voltage comparator chip U6, and the seventh voltage comparator chip U7 are all TLV3501, and the second signal output terminal OUT _1 is an SMA _ KE female socket.
In the comparator circuit, pin 3 of the fifth voltage comparator chip U5 is connected to the isolated output sine wave signal OPAOUT, pin 4 and pin 8 of the voltage comparator chip U5 are connected to-1.2V output by the power conversion circuit, pin 7 is connected to +2.5V output by the power conversion circuit, pin 2 is connected to the ground line, pin 1 and pin 5 are placed in suspension, pin 6 of the voltage comparator chip U5 is connected to one end of a thirteenth resistor R13, the other end of the thirteenth resistor R13 outputs a square wave signal VOUT _1, and is simultaneously connected to one end of a thirty-third patch capacitor C33, and the other end of the thirty-third patch capacitor C33 is connected to the ground line; one end of the thirty-first patch capacitor C31 and one end of the thirty-second patch capacitor C32 are connected with +2.5V output by the power conversion circuit, and the other end of the thirty-second patch capacitor C32 is connected with the ground wire; one end of the thirty-fourth chip capacitor C34 and one end of the thirty-fifth chip capacitor C35 are connected with-1.2V output by the power conversion circuit, and the other end of the thirty-fourth chip capacitor C35 is connected with the ground wire; a pin 3 of the sixth voltage comparator chip U6 is connected to one end of a fourteenth resistor R14, the other end of the fourteenth resistor R14 is connected to the square wave signal VOUT _1 output by the fifth voltage comparator chip U5, a pin 2 of the voltage comparator chip U6 is connected to the low level signal Vref output by the voltage dividing circuit, a pin 7 is connected to the +3.3V, pin 4, pin 8 ground line output by the power conversion circuit, pin 1, pin 5 are placed in a floating manner, a pin 6 of the voltage comparator chip U6 is connected to one end of a fifteenth resistor R15, the other end of the fifteenth resistor R15 outputs the square wave signal VOUT _2 and is simultaneously connected to one end of a thirty-eighth chip capacitor C38, and the other end of the thirty-eighth chip capacitor C38 is connected to the ground line; one end of the thirty-sixth patch capacitor C36 and one end of the thirty-seventh patch capacitor C37 are connected with +3.3V output by the power conversion circuit, and the other end of the thirty-sixth patch capacitor C36 and the thirty-seventh patch capacitor C37 are connected with the ground wire; a pin 3 of the seventh voltage comparator chip U7 is connected to one end of a sixteenth resistor R16, the other end of the sixteenth resistor R16 is connected to the square wave signal VOUT _1 output by the fifth voltage comparator chip U5, a pin 2 of the voltage comparator chip U7 is connected to the square wave signal VOUT _2 output by the sixth voltage comparator chip U6, a pin 7 is connected to a +3.3V, 4, 8 pin ground line output by the power conversion circuit, pins 1, 5 are placed in a floating manner, a pin 6 of the voltage comparator chip U7 is connected to one end of a seventeenth resistor R17, the other end of the seventeenth resistor R17 is connected to a first pin of a second signal output terminal OUT _1, and a second pin of the second signal output terminal OUT _1 is connected to the ground line; one end of the thirty-ninth patch capacitor C39 and one end of the forty-fourth patch capacitor C40 are connected with +3.3V output by the power conversion circuit, and the other end of the thirty-ninth patch capacitor C40 is connected with the ground wire;
the specific working process is as follows: the external circuit provides a + 5V-5V direct-current power supply for the whole pulse circuit generating system, the power supply is provided for the power supply conversion circuit in the figure 2 after being subjected to capacitor decoupling and filtering, and the voltages of +3.3V, +2.5V and-1.2V are respectively output by setting the resistance values of the output ends of the voltage regulating pins of the linear voltage stabilizing chips U1, U2 and U3; the filtered +5V and-5V power supplies to the buffer circuit of fig. 4, the resistor R9 and the capacitor C23 in the buffer circuit of fig. 4 form an RC filter to reduce ripples and burrs of the input variable frequency sine wave signal, and then pass through the operational amplifier chip U4 to reduce the impedance of the output sine wave signal OPAOUT, reduce signal consumption, and improve load carrying capacity, the signal OPAOUT is input to the non-inverting input terminal of the comparator chip U5 in the waveform output circuit of fig. 5, the power supply voltages of U5 are +2.5V and-1.2V, respectively, the output signal passes through the RC filter formed by the resistor R13 and the capacitor C33 in fig. 5 to generate square wave signals VOUT _1 of +2.5V and-1.2V, the square wave signal VOUT _1 passes through the resistor R14 in fig. 5 and then is input to the non-inverting input terminal and inverting input terminal of the comparator chip U6 in fig. 5 and the low voltage signal Vref generated in the resistor divider circuit of fig. 3, the power supply voltage of U6 is 3.3V and 0V, the output signal passes through the RC filter formed by the resistor R15 and the capacitor C18 in fig. 5, and generates a square wave signal VOUT _2, the square wave signal VOUT _1 passes through the current limiting resistor R16 in fig. 5, and then is input to the non-inverting input terminal and the inverting input terminal of the comparator chip U7 in fig. 5, the power supply voltage of U7 is 3.3V and 0V, and the output signal passes through the protection resistor R17 in fig. 5, and then is the output synchronous pulse signal.
The above description of the embodiments is merely intended to facilitate an understanding of the method of the invention and its core concepts
Want. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. A synchronous trigger pulse generating circuit is characterized by at least comprising a power supply converting circuit and a waveform output circuit, wherein,
the power supply conversion circuit is used for providing power supply voltage and comparison reference voltage for the waveform output circuit;
the waveform output circuit comprises a first voltage comparator, a second voltage comparator and a third voltage comparator, wherein the non-inverting input end of the first voltage comparator is connected with a sine wave signal, the inverting input end of the first voltage comparator is connected with a zero voltage, and the output end of the first voltage comparator outputs a first square wave signal VOUT _1 through a first RC filter; the non-inverting input end of the second voltage comparator is connected with the first square wave signal VOUT _1, and the inverting input end of the second voltage comparator is connected with the low-level reference voltage VrefThe output end of the second voltage comparator outputs a second square wave signal VOUT _2 through a second RC filter; the non-inverting input end of the first voltage comparator is connected with the second square wave signal VOUT _2, the inverting input end of the first voltage comparator is connected with the first square wave signal VOUT _1, and the output end of the third voltage comparator outputs a synchronous pulse signal;
the positive power supply input end of the first voltage comparator inputs +2.5V, the negative power supply input end inputs-1.2V, the high level of the first square wave signal VOUT _1 is +2.5V, and the low level thereof is-1.2V;
the positive power supply input end of the second voltage comparator inputs +3.3V, the negative power supply input end of the second voltage comparator inputs 0V, the high level of a second square wave signal VOUT _2 is +3.3V, and the low level of the second square wave signal VOUT _2 is 0V;
in the third voltage comparator, +3.3V is input to the positive power supply input end of the comparator, 0V is input to the negative power supply input end of the comparator, the high level of the synchronous pulse signal is +3.3V, and the low level of the synchronous pulse signal is 0V.
2. The synchronous trigger pulse generating circuit of claim 1, wherein the first RC filter and the second RC filter are series resistors and parallel capacitors to form an RC low pass filter for filtering high frequency noise and periodic fluctuating signals to obtain a square wave signal with a slow rising edge.
3. The synchronous trigger pulse generating circuit of claim 1, wherein the non-inverting input of the second voltage comparator and the inverting input of the third comparator are provided with current limiting resistors.
4. The synchronous trigger pulse generating circuit according to claim 1, wherein a pulse width of the synchronous pulse signal is between several ns and several tens of ns.
5. The synchronous trigger pulse generating circuit of claim 1, wherein the power conversion circuit comprises at least three independent DC-DC conversion circuits for respectively powering the comparators in the waveform output circuit.
6. The synchronous trigger pulse generating circuit of claim 5, wherein the power conversion circuit further comprises a resistor voltage divider circuit for outputting a low-level reference voltage V in the range of 0-2.5V by using serial voltage divisionref。
7. The synchronized trigger pulse generating circuit of claim 1, further comprising a buffer circuit for outputting the input variable amplitude sine wave signal as a low impedance sine wave signal without a bias voltage.
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