CN216851920U

CN216851920U - Filtering denoising circuit and clock circuit

Info

Publication number: CN216851920U
Application number: CN202220103717.9U
Authority: CN
Inventors: 陈功; 刘搏
Original assignee: Shenzhen Gencotech Communication Equipment Co ltd
Current assignee: Shenzhen Gencotech Communication Equipment Co ltd
Priority date: 2022-01-14
Filing date: 2022-01-14
Publication date: 2022-06-28
Anticipated expiration: 2032-01-14

Abstract

The application is suitable for the technical field of clocks, and provides a filtering and denoising circuit and a clock circuit, wherein the filtering and denoising circuit comprises a filtering circuit, a first feedback circuit, a second feedback circuit, a comparison circuit and a low-pass filter; the input end of the filter circuit is connected with the analog signal output circuit; the first output end of the filter circuit is connected with the output end of the first feedback circuit, and the second output end of the filter circuit is connected with the output end of the second feedback circuit; the third output end of the filter circuit is connected with the non-inverting input end of the comparison circuit, and the fourth output end of the filter circuit is connected with the inverting input end; the negative output end of the comparison circuit is connected with the input end of the first feedback circuit, and the positive output end of the comparison circuit is connected with the input end of the second feedback circuit. The negative output end of the comparison circuit is fed back to the non-inverting input end through the first feedback circuit, and the positive output end is fed back to the inverting input end through the second feedback circuit, namely, negative feedback is introduced.

Description

Filtering denoising circuit and clock circuit

Technical Field

The application belongs to the technical field of clocks, and particularly relates to a filtering denoising circuit and a clock circuit.

Background

A clock circuit is an oscillating circuit that produces accurate movement like a clock. Any work is in chronological order. The circuit for generating this time is a clock circuit, which generally consists of a crystal oscillator, a master control circuit, a compensation circuit, various electronic components, and the like.

For example, when the digital signal processed by the main control circuit or the compensation circuit in the compensation chip is converted into an analog signal through digital-analog conversion and output, the analog signal needs to be filtered by a filter, so that the signal with useful frequency can pass through while the signal with useless frequency is suppressed, and the purpose of removing noise is achieved. At present, an RC (resistance-capacitance) filtering mode is generally adopted for filtering, and the filtering effect is poor.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a filtering and denoising circuit and a clock circuit, and aims to solve the problem that a filtering circuit in an existing clock circuit is poor in filtering effect.

A first aspect of an embodiment of the present application provides a filtering and denoising circuit, including a filtering circuit, a first feedback circuit, a second feedback circuit, a comparison circuit, and a low-pass filter;

the input end of the filter circuit is connected with the analog signal output circuit;

a first output end of the filter circuit is connected with an output end of the first feedback circuit, and a second output end of the filter circuit is connected with an output end of the second feedback circuit;

the third output end of the filter circuit is connected with the non-inverting input end of the comparison circuit, and the fourth output end of the filter circuit is connected with the inverting input end of the comparison circuit;

the negative output end of the comparison circuit is connected with the input end of the first feedback circuit, and the positive output end of the comparison circuit is connected with the input end of the second feedback circuit;

and the input end of the low-pass filter is respectively connected with the positive output end of the comparison circuit and the negative output end of the comparison circuit.

In one embodiment, the filter circuit includes a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a seventh switching element, an eighth switching element, a first capacitor, and a second capacitor, and the input terminals of the filter circuit include a first input terminal of the filter circuit and a second input terminal of the filter circuit;

a first end of the first switching element is a first input end of the filter circuit, a second end of the first switching element is respectively connected with a first end of the second switching element and a first end of the first capacitor, and a second end of the second switching element is grounded;

a second end of the first capacitor is a first output end of the filter circuit, and the second end of the first capacitor is respectively connected with an output end of the first feedback circuit, a first end of the third switching element and a first end of the fourth switching element;

a second end of the third switching element is grounded, and a second end of the fourth switching element is a third output end of the filter circuit;

a first end of the fifth switching element is a second input end of the filter circuit, a second end of the fifth switching element is respectively connected with a first end of the sixth switching element and a first end of the second capacitor, and a second end of the sixth switching element is grounded;

a second end of the second capacitor is a second output end of the filter circuit, and the second end of the second capacitor is respectively connected with an output end of the second feedback circuit, a first end of the seventh switching element and a first end of the eighth switching element;

a second terminal of the seventh switching element is grounded, and a second terminal of the eighth switching element is a fourth output terminal of the filter circuit.

In one embodiment, the filter circuit further comprises a third capacitor;

and the first end of the third capacitor is connected with the second end of the fourth switching element, and the second end of the third capacitor is connected with the negative output end of the comparison circuit.

In one embodiment, the filter circuit further comprises a fourth capacitor;

a first end of the fourth capacitor is connected to the second end of the eighth switching element, and a second end of the fourth capacitor is connected to the positive output end of the comparison circuit.

In one embodiment, the first feedback circuit includes a fifth capacitance, a ninth switching element, and a tenth switching element;

a first end of the fifth capacitor is an output end of the first feedback circuit, and a second end of the fifth capacitor is respectively connected with a first end of the ninth switching element and a first end of the tenth switching element;

a second terminal of the ninth switching element is grounded, and a second terminal of the tenth switching element is an input terminal of the first feedback circuit.

In one embodiment, the second feedback circuit includes a sixth capacitance, an eleventh switching element, and a twelfth switching element;

a first end of the sixth capacitor is an output end of the second feedback circuit, and a second end of the sixth capacitor is connected to a first end of the eleventh switching element and a first end of the twelfth switching element respectively;

a second terminal of the eleventh switching element is grounded, and a second terminal of the twelfth switching element is an input terminal of the second feedback circuit.

In one embodiment, the filtering and denoising circuit further comprises a gain amplification circuit;

and the first input end of the gain amplification circuit is connected with the negative output end of the comparison circuit and the positive output end of the comparison circuit.

In one embodiment, the gain amplification circuit comprises a first resistor, a second resistor, an adjustable resistor and an amplifier;

the first end of the first resistor is a first input end of the gain amplification circuit, and the first end of the second resistor is a second input end of the gain amplification circuit;

the first input end of the amplifier is respectively connected with the second end of the first resistor, the second end of the second resistor and the first end of the adjustable resistor, the second input end of the amplifier is connected with the output end of the bias voltage generating circuit, and the output end of the amplifier is connected with the second end of the adjustable resistor.

In one embodiment, the comparison circuit comprises a comparator.

A second aspect of the embodiments of the present application provides a clock circuit, which includes the filtering and denoising circuit provided in the first aspect of the embodiments of the present application.

The filtering and denoising circuit provided by the first aspect of the embodiment of the application comprises a filtering circuit, a first feedback circuit, a second feedback circuit, a comparison circuit and a low-pass filter; the input end of the filter circuit is connected with the analog signal output circuit; a first output end of the filter circuit is connected with an output end of the first feedback circuit, and a second output end of the filter circuit is connected with an output end of the second feedback circuit; the third output end of the filter circuit is connected with the non-inverting input end of the comparison circuit, and the fourth output end of the filter circuit is connected with the inverting input end of the comparison circuit; the negative output end of the comparison circuit is connected with the input end of the first feedback circuit, the positive output end of the comparison circuit is connected with the input end of the second feedback circuit, and the input end of the low-pass filter is respectively connected with the positive output end of the comparison circuit and the negative output end of the comparison circuit. The negative output end of the comparison circuit is fed back to the in-phase input end through the first feedback circuit, the positive output end is fed back to the reverse phase input end through the second feedback circuit, and negative feedback is introduced into the negative output end and the in-phase input end and the positive output end and the reverse phase input end. The negative feedback can quickly attenuate when the amplitude-frequency characteristic of the low-pass filter is high frequency, so that only low-frequency end signals can be allowed to pass through, and the low-pass filter has the characteristics of high input impedance and low output impedance, thereby efficiently filtering noise.

It is to be understood that, the beneficial effects of the second aspect may refer to the relevant description in the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a filtering and denoising circuit provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of another structure of a filtering and denoising circuit provided in the embodiment of the present application;

FIG. 3 is a schematic diagram of another structure of a filtering and denoising circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic circuit diagram of a filtering and denoising circuit provided in an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another filtering and denoising circuit provided in an embodiment of the present application;

fig. 6 is a schematic circuit diagram of a gain amplifying circuit according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing a relative importance or importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise. "plurality" means two or more.

The embodiment of the application provides a filtering and denoising circuit, which can be applied to electronic equipment with signals to be filtered, particularly to a clock circuit, so as to solve the problem that the filtering effect of the filtering circuit in the existing clock circuit is not good.

As shown in fig. 1, a filtering and denoising circuit 100 provided in the embodiment of the present application includes a filtering circuit 10, a first feedback circuit 20, a second feedback circuit 30, a comparing circuit 40, and a low-pass filter 50;

the input end of the filter circuit 10 is connected with the analog signal output circuit, and the input end of the filter circuit 10 is used for receiving an input analog signal;

a first output end of the filter circuit 10 is connected to an output end of the first feedback circuit 20, and a second output end of the filter circuit 10 is connected to an output end of the second feedback circuit 30;

a third output end of the filter circuit 10 is connected with a non-inverting input end of the comparison circuit 40, and a fourth output end of the filter circuit 10 is connected with an inverting input end of the comparison circuit 40; the negative output end of the comparison circuit 40 is connected with the input end of the first feedback circuit 20, and the positive output end of the comparison circuit 40 is connected with the input end of the second feedback circuit 30;

the input terminal of the low pass filter 50 is connected to the positive output terminal of the comparison circuit and the negative output terminal of the comparison circuit, respectively.

Specifically, the filtering and denoising Circuit is applied to a clock Circuit, which may include but is not limited to one or more of a crystal oscillator, a main control Circuit, a compensation Circuit and various electronic components, where the main control Circuit includes a control chip, and the control chip may specifically be any device capable of implementing data Processing and control functions, such as a single chip Central Processing Unit (CPU), and may also be other general purpose control chips, Digital Signal control chips (DSP), ARM microprocessors, Application Specific Integrated Circuits (ASIC), ready-made Programmable Gate arrays (FPGA) or other Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like. The general control chip may be a micro control chip or the control chip may be any conventional control chip, etc.

In application, the filter circuit, the first feedback circuit and the second feedback circuit may be implemented by a switch element and a capacitor, and the comparison circuit may be implemented by a comparator, and the comparator may employ an amplifier having a comparison function.

Specifically, the negative output end of the comparison circuit is fed back to the non-inverting input end through the first feedback circuit, and the positive output end is fed back to the inverting input end through the second feedback circuit, that is, negative feedback is introduced into both the negative output end and the non-inverting input end as well as the positive output end and the inverting input end. The negative feedback can quickly attenuate when the amplitude-frequency characteristic of the low-pass filter is high frequency, so that only low-frequency end signals can be allowed to pass through, and the low-pass filter has the characteristics of high input impedance and low output impedance, thereby efficiently filtering noise.

As shown in fig. 2, in an embodiment, the filter circuit includes a first switch element S1, a second switch element S2, a third switch element S3, a fourth switch element S4, a fifth switch element S5, a sixth switch element S6, a seventh switch element S7, an eighth switch element S8, a first capacitor C1, and a second capacitor C2, and the input terminal of the filter circuit 10 includes a first input terminal of the filter circuit 10 and a second input terminal of the filter circuit 10;

a first terminal of the first switching element S1 is a first input terminal of the filter circuit 10, a second terminal of the first switching element S1 is respectively connected to a first terminal of the second switching element S2 and a first terminal of the first capacitor C1, and a second terminal of the second switching element S2 is grounded;

a second terminal of the first capacitor C1 is a first output terminal of the filter circuit 10, and a second terminal of the first capacitor C1 is respectively connected to the output terminal of the first feedback circuit 20, the first terminal of the third switching element S3 and the first terminal of the fourth switching element S4;

a second terminal of the third switching element S3 is grounded, and a second terminal of the fourth switching element S4 is a third output terminal of the filter circuit 10;

a first terminal of the fifth switching element S5 is a second input terminal of the filter circuit 10, a second terminal of the fifth switching element S5 is connected to a first terminal of the sixth switching element S6 and a first terminal of the second capacitor C2, respectively, and a second terminal of the sixth switching element S6 is grounded;

a second terminal of the second capacitor C2 is a second output terminal of the filter circuit 10, and a second terminal of the second capacitor C2 is respectively connected to the output terminal of the second feedback circuit 30, the first terminal of the seventh switching element S7 and the first terminal of the eighth switching element S8;

a second terminal of the seventh switching element S7 is grounded, and a second terminal of the eighth switching element S8 is a fourth output terminal of the filter circuit 10.

Specifically, when the analog voltage at the first input terminal is valid, the switches S1 and S3 are closed, and the switches S2 and S4 are opened, the second terminal of the capacitor C1 is grounded, the signal voltage charges the capacitor C1 through the switch S1, and the charging voltage is u 1; when the analog voltage at the second input terminal is valid, the switches S5 and S7 are closed, and the switches S6 and S8 are opened, the second terminal of the capacitor C2 is grounded, and the signal voltage charges the capacitor C2 through the switch S5, and the charging voltage is u 3. When the switches S1 and S3 are open and the switches S2 and S4 are closed, the first terminal of the capacitor C1 is grounded and the capacitor C1 discharges at a voltage u 2. When the switching frequency fc of the switches S1 and S3 and the switches S2 and S4 is higher than the signal frequency to be filtered, the capacitor C1 is alternately charged and discharged between two voltage nodes u1 and u 2; then the charge that C1 transfers between u1 and u2 will form the average current I1:

I1＝fc*C1*(u1-u2) (1)

similarly, when the switches S5 and S7 are opened and the switches S6 and S8 are closed, the first terminal of the capacitor C2 is grounded, and the capacitor C2 discharges to obtain the voltage u 4. When the switching frequency fc of the switches S5 and S7, and the switches S6 and S8 is higher than the signal frequency to be filtered, the capacitor C2 is alternately charged and discharged between the two voltage nodes u3 and u4, so that the charge transferred by the C2 between u3 and u4 forms the average current I2,

I2＝fc*C2*(u3-u4) (2)

as can be seen from

equations

1 and 2, the equivalent resistor R1 is connected between u1 and u2, the equivalent resistor R2 is connected between u3 and u4, and the values of R1 and R2 are 1/(fc × C1) and 1/(fc × C2), respectively, so that the equivalent resistance value can be changed by adjusting the switching frequency of the switch, and the frequency of filtering is determined by the values of R and C because the current RC filter is composed of a resistor and a capacitor. For different filtering requirements, the value of the resistor R is different, if the proper filtering performance is to be achieved, a hardware resistor needs to be replaced, in addition, the resistance of the resistor is affected by tolerance and thermal drift of the resistor, the performance of the filter is further affected, and the resistor is welded on a circuit and has a large volume, so that the existing filtering effect is poor. The method can replace the traditional RC filter, the resistor R and the capacitor C in the traditional RC filter are often large in size, the value of the resistor R is different according to different filtering requirements, the resistance value of the resistor R is not common in daily life, and the resistor R needs to be customized. The filter has the characteristics of small volume and low power consumption; different equivalent resistance values can be obtained by adjusting the switching frequency of the switch, and the filter coefficient can be quickly adjusted under the condition of not changing hardware, so that the optimal filtering effect is achieved.

As shown in fig. 3, in one embodiment, the filter circuit further includes a third capacitor C3; a first terminal of the third capacitor C3 is connected to the second terminal of the fourth switching element S4, and a second terminal of the third capacitor C3 is connected to the negative output terminal of the comparison circuit 40.

The filter circuit 10 further includes a fourth capacitor C4; a first terminal of the fourth capacitor C4 is connected to the second terminal of the eighth switching element S8, and a second terminal of the fourth capacitor C4 is connected to the positive output terminal of the comparison circuit 40.

As shown in fig. 4, in one embodiment, the first feedback circuit 20 includes a fifth capacitor C5, a ninth switching element S9, and a tenth switching element S10; a first terminal of the fifth capacitor C5 is an output terminal of the first feedback circuit 20, and a second terminal of the fifth capacitor C5 is respectively connected to a first terminal of the ninth switching element S9 and a first terminal of the tenth switching element S10;

a second terminal of the ninth switching element S9 is connected to ground, and a second terminal of the tenth switching element S10 is an input terminal of the first feedback circuit 20.

The second feedback circuit 30 includes a sixth capacitor C6, an eleventh switching element S11, and a twelfth switching element S12; a first end of the sixth capacitor C6 is an output end of the second feedback circuit 30, and a second end of the sixth capacitor C6 is connected to a first end of the eleventh switch element S11 and a first end of the twelfth switch element S12, respectively;

a second terminal of the eleventh switching element S11 is grounded, and a second terminal of the twelfth switching element S12 is an input terminal of the second feedback circuit 30.

The comparison circuit 40 comprises a comparator.

Specifically, when the analog voltage at the first input terminal is valid, the switches S1, S3 and S10 are closed, and the switches S2, S4 and S9 are opened, the second terminal of the capacitor C1 is grounded, the signal voltage charges the capacitor C1 through the switch S1, and the charging voltage is u 1; when the analog voltage at the second input terminal is valid, the switches S5, S7 and S12 are closed, and the switches S6, S8 and S11 are opened, the second terminal of the capacitor C2 is grounded, the signal voltage charges the capacitor C2 through the switch S5, and the charging voltage is u 3. When the switches S1, S3, and S10 are open and the switches S2, S4, and S9 are closed, the first terminal of the capacitor C1 is grounded and the capacitor C1 discharges at a voltage u 2. When the switching frequency fc of the switches S1, S3 and S10 and the switches S2, S4 and S9 is higher than the signal frequency to be filtered, the capacitor C1 is alternately charged and discharged between the two voltage nodes u1 and u 2; then the charge that C1 transfers between u1 and u2 will form the average current I1:

I1＝fc*C1*(u1-u2) (1)

similarly, the capacitor C2 is alternately charged and discharged between the two voltage nodes u3 and u4, so that the charge transferred by the capacitor C2 between u3 and u4 forms an average current I2,

I2＝fc*C2*(u3-u4) (2)

when the switches S2, S4, and S9 are closed while the switches S1, S3, and S10 are open, the second terminal of the capacitor C5 is grounded, and the u2 charges the first terminal of the capacitor C5; when the switches S1, S3 and S10 are closed and the switches S2, S4 and S9 are opened, the first end of the capacitor C5 is grounded, the capacitor C5 discharges, and the voltage u 5; when the switching frequencies of the switches S1, S3 and S10 and the switches S2, S4 and S9 are fc which is higher than the signal frequency to be filtered, the capacitor C5 alternately charges and discharges between two voltage nodes u2 and u 5; then the charge that C5 transfers between u2 and u5 will form the average current I3:

I3＝fc*C5*(u2-u5) (3)

when the switches S5, S7, and S12 are open and the switches S6, S8, and S11 are closed, the second terminal of the capacitor C6 is grounded and the u4 charges the first terminal of the capacitor C6. When the switches S5, S7 and S12 are closed and the switches S6, S8 and S11 are opened, the first end of the capacitor C6 is grounded, the capacitor C6 discharges, and the voltage u 6; when the switching frequency fc of the switches S5, S7 and S12 and the switches S6, S8 and S11 is higher than the signal frequency to be filtered, the capacitor C6 is alternately charged and discharged between the two voltage nodes u4 and u 6; then the charge that C6 transfers between u4 and u5 will form the average current I4:

I4＝fc*C6*(u4-u5) (4)

as can be seen from

formulas

1, 2, 3 and 4, the equivalent resistance R1 is connected between u1 and u2, the equivalent resistance R2 is connected between u3 and u4, the equivalent resistance R3 is connected between u2 and u5, and the equivalent resistance R4 is connected between u4 and u 6. The values of R1, R2, R3 and R4 are 1/(fc × C1), 1/(fc × C2), 1/(fc × C3), and 1/(fc × C6), respectively.

As shown in fig. 4, when the digital signal DATA is 1, the first input terminal is active, and the signal at the second input terminal is input to the filter circuit for filtering, and when the digital signal DATA is 0, the second input terminal is active, and the signal at the second input terminal is input to the filter circuit for filtering. Therefore, the digital signal is converted into the analog signal meeting the preset requirement. When the switches S1, S3 and S10 are opened and the switches S2, S4 and S9 are closed, the capacitor C3 is charged, when the switches S1, S3 and S10 are closed and the switches S2, S4 and S9 are opened, the voltage u2 and the capacitor C3 have an infinite resistance, the voltage u2 stops charging the capacitor C3, and when the switches S2, S4 and S9 are closed, the u2 directly charges the capacitor C3. So that the switching of the fourth switch S4 can be equivalent to a resistor R5. Similarly, when the switches S5, S7 and S12 are opened and the switches S6, S8 and S11 are closed, the voltage u4 charges the capacitor C4, when the switches S5, S7 and S12 are closed and the switches S6, S8 and S11 are opened, the voltage u4 and the capacitor C4 have an infinite resistance, the voltage u4 stops charging the capacitor C4, and when the switches S6, S8 and S11 are closed, the u4 directly charges the capacitor C4. Thus, the switch of the eighth switch S8 can be equivalent to a resistor R6, and the equivalent resistance value can be changed by adjusting the switching frequency.

As shown in FIG. 5, in one embodiment, the filter denoising circuit further comprises a gain amplification circuit 60; a first input of the gain amplifier circuit 60 is connected to the output of the low pass filter.

As shown in fig. 6, in one embodiment, the gain amplifying circuit includes a first resistor R7, a second resistor R8, an adjustable resistor R9 and an amplifier U1;

the first end of the first resistor is a first input end of the gain amplifying circuit 60, and the first end of the second resistor is a second input end of the gain amplifying circuit 60;

a first input end of the amplifier U1 is connected to the second end of the first resistor R7, the second end of the second resistor R8, and the first end of the adjustable resistor R9, a second input end of the amplifier U1 is connected to an output end of the bias voltage generating circuit, and an output end of the amplifier U1 is connected to the second end of the adjustable resistor R9.

Specifically, the voltage value output from the low pass filter may be too small to meet the design requirement, and for this purpose, a certain voltage value is added to the output voltage and then an amplification process is performed. However, the output voltage may be an ac signal, so that the output voltage has different magnitudes, and thus the upper and lower alternate points (i.e. zero-crossing points) of the ac voltage are not the same voltage value, and for this reason, the 1.5V generated by the bias voltage generating circuit may be used as the reference voltage, so that the ac voltage changes up and down with 1.5V as the reference point. VDAC is output voltage passing through the comparison circuit, the VDAC and external input voltage VC are accumulated, the VDAC and the external input voltage VC can be adjusted through the external input voltage VC and then are connected to the inverting input end of the amplifier U1, the positive input end of the amplifier U1 is connected with 1.5V reference voltage for superposition and then amplification output, the output voltage is VPGAO, and the amplification factor is adjusted through the adjustable resistor R9, so that the actual requirement is met. Amplifier U1 may be an integrated operational amplifier whose output is proportional to the imaginary short and kirchhoff's law:

(1.5-VDAC)/R7+(1.5-VC)/R8＝(1.5–VPGAO)/R9

the final output voltage was 1.5- ((1.5-VDAC)/R7+ (1.5-VC)/R8) × R9.

The embodiment of the application also provides a clock circuit, which comprises the matched filter denoising circuit in any embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A filtering and denoising circuit is characterized by comprising a filtering circuit, a first feedback circuit, a second feedback circuit, a comparison circuit and a low-pass filter;

2. The filter denoising circuit of claim 1, wherein the filter circuit comprises a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, a sixth switch element, a seventh switch element, an eighth switch element, a first capacitor, and a second capacitor, and wherein the input terminals of the filter circuit comprise a first input terminal of the filter circuit and a second input terminal of the filter circuit;

3. The filter denoising circuit of claim 2, wherein the filter circuit further comprises a third capacitor;

4. The filter denoising circuit of claim 3, wherein the filter circuit further comprises a fourth capacitor;

5. The filter denoising circuit of claim 1, wherein the first feedback circuit comprises a fifth capacitor, a ninth switching element, and a tenth switching element;

a first end of the fifth capacitor is an output end of the first feedback circuit, and a second end of the fifth capacitor is connected to a first end of the ninth switching element and a first end of the tenth switching element, respectively;

6. The filter denoising circuit of claim 1, wherein the second feedback circuit comprises a sixth capacitor, an eleventh switching element, and a twelfth switching element;

7. The filter denoising circuit of claim 1, further comprising a gain amplification circuit;

and the first input end of the gain amplification circuit is connected with the output end of the low-pass filter.

8. The filtering and denoising circuit of claim 7, wherein the gain amplifying circuit comprises a first resistor, a second resistor, an adjustable resistor and an amplifier;

9. The filter denoising circuit of claim 1, wherein the comparison circuit comprises a comparator.

10. A clock circuit comprising the filter denoising circuit of any one of claims 1 through 9.