CN111599780A - 半导体封装件以及制造半导体封装件的方法 - Google Patents

半导体封装件以及制造半导体封装件的方法 Download PDF

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CN111599780A
CN111599780A CN201911070673.3A CN201911070673A CN111599780A CN 111599780 A CN111599780 A CN 111599780A CN 201911070673 A CN201911070673 A CN 201911070673A CN 111599780 A CN111599780 A CN 111599780A
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semiconductor
crystal
semiconductor package
plane
silicon
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CN201911070673.3A
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元东勳
柳在炅
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供一种半导体封装件及制造半导体封装件的方法。半导体封装件包含：基底，具有硅晶体结构；以及至少一个半导体芯片，设置于基底上且具有上表面、下表面以及多个侧表面，其中多个侧表面不同于基底的解理面。

Description

半导体封装件以及制造半导体封装件的方法
相关申请的交叉引用
本申请案要求2019年2月21日在韩国知识产权局申请的韩国专利申请案第10-2019-0020187号的优先权益，所述申请案的公开内容以全文引用的方式并入本文中。
技术领域
符合根据实例实施例的装置和方法涉及一种晶片级封装件，其中半导体芯片安装在具有硅结晶结构的基底上。
背景技术
晶片可以划分为芯片区域和用于标识芯片区域的划片槽区域，且可包含显示晶片的晶体结构的平坦区，半导体芯片在所述芯片区域中布置于晶片的表面上。由于无法用裸眼辨识的晶片的晶体结构，因此在晶片的平坦区中，通过沿特定晶面切割来使晶片的外圆周表面的一部分平坦，以显示晶片的晶体取向。通常，划片槽平行于或垂直于平坦区。
晶片级封装件可通过以下来形成：将半导体芯片安装在晶片的表面上；以及执行切割划片槽区域的切割工艺以使半导体芯片彼此分隔。在晶片级封装件的制造期间，可能因半导体芯片的冲击或因外来物质而对晶片施加弯曲力。裂纹可由于弯曲力而出现在晶片中，且主要在晶片的晶体取向上传播。
发明内容
本发明概念的实例实施例涉及提供一种半导体封装件，所述半导体封装件能够在晶片级封装件的制造期间阻止裂纹的传播，所述裂纹由因将半导体芯片安装在晶片上时产生的冲击或因外来物质而对晶片施加的弯曲力导致。
根据实例实施例，提供一种半导体封装件，所述半导体封装件包含：缓冲基底，具有硅晶体结构；以及至少一个半导体芯片，设置于缓冲基底上且具有上表面、下表面以及多个侧表面，其中多个侧表面相对于缓冲基底的解理面(cleavage planes)成倾斜角。
根据实例实施例，提供一种半导体封装件，所述半导体封装件包含：硅基底，具有硅晶体结构和作为主表面的{100}晶面；以及半导体芯片，设置于硅基底上且具有四边形的上表面，其中半导体芯片具有外侧表面，所述外侧表面在以平面图查看时相对于硅晶体结构的<110>晶体取向形成倾斜角。
根据实例实施例，提供一种制造半导体封装件的方法，所述方法包含：制备缓冲基底，所述缓冲基底具有硅晶体结构和作为主表面的(100)晶面；在缓冲基底上布置半导体芯片；形成模制构件以覆盖缓冲基底和半导体芯片；以及通过切割模制构件和缓冲基底来形成单独半导体封装件，使得单独半导体封装件中的每一个包含至少一个半导体芯片，其中在缓冲基底上的半导体芯片的布置包含布置半导体芯片使得半导体芯片的外侧表面相对于<110>晶体取向形成45°角。
附图说明
图1是示出根据本发明概念的实例实施例的晶片和半导体芯片的布局以及从晶片中个别化的半导体封装件的示意性平面图。
图2是沿图1的线I-I'截取的截面图。
图3是示出根据本发明概念的实例实施例的晶片和半导体芯片的布局以及从晶片中个别化的半导体封装件的示意性平面图。
图4是示出根据本发明概念的实例实施例的晶片和半导体芯片的布局以及从晶片中个别化的半导体封装件的示意性平面图。
图5到图10是示意性地示出根据本发明概念的实例实施例的制造半导体封装件的方法的图，其中图6是沿图5的线II-II'截取的截面图，图8是沿图7的线III-III'截取的截面图，且图10是沿图9的线IV-IV'截取的截面图。
附图标号说明
1、2：晶片；
10：缓冲基底/基底；
20、21、22、23、24、200：半导体芯片；
31、32、140、230：连接凸块；
45°：倾斜角；
50：绝缘层；
60：模制构件；
100：硅晶片/晶片/基底；
110：互连层/布线层；
120、V1、V2：硅通孔/TSV；
130：连接电极；
400：保护层；
410：离型层；
420：粘合层；
440：研磨器；
500：晶片载体；
A、B、C：半导体封装件；
As、Bs、Cs、Ds：外侧表面；
FZ：平坦区；
I-I'、II-II'、III-III'、IV-IV'：线；
SL：划片槽；
SRAM：静态RAM。
具体实施方式
在下文中，将参见附图详细地描述本发明概念的示范性实施例以清楚地阐明本发明概念的技术理念。在以下描述中，如果确定与本发明概念相关的熟知功能或构造由于不必要的细节而使本发明概念模糊，那么不详细地描述所述功能或构造。在附图中，相同附图编号或符号分配给具有基本上相同功能的组件(如果可能)，尽管组件在不同的附图中示出。为方便解释，必要时将装置与方法一起描述。
在本发明概念的技术理念中，硅晶片的晶面和其晶体取向是主要构成元素。为理解本发明的概念，下文将首先描述结晶方向和结晶平面。
关于结晶方向
结晶方向可使用向量来表示，且可使用u、v以及w的值在方括号中表示为[uvw]，所述u、v以及w指示投影到作为坐标轴的x轴、y轴以及z轴上的向量的长度。三条轴线中的每一个可具有正坐标和负坐标。负指数可使用相应指数上方的条来表示。举例来说，
Figure BDA0002260826060000044
方向具有y轴方向上负组分。在一些晶体结构中，具有一些不同方向指数的非平行方向实际上是等效的。这意味着各个方向上的原子间距离是相等的。举例来说，在立方结构中，[100]、
Figure BDA0002260826060000041
[010]、
Figure BDA0002260826060000042
[001]以及
Figure BDA0002260826060000043
是等效的。为方便解释，等效方向一起称作为一系列且可以以V形括号中表达。在以上情况中，等效方向可表达为<100>。在立方晶体中，无论指数的次序或符号如何，具有相同组的指数的方向为相同的。举例来说，[123]与[213]为等效的。这关系不施加于其它晶体系统。举例来说，在四边形晶体系统中，[100]与[010]是等效的，但[100]与[001]不同。
关于结晶平面
可类似于结晶方向指定晶体结构的面。(hkl)米勒(Miller)指数用于使用三轴坐标系的所有晶体系统，除六角系统外。两个平行面彼此等效于且具有相同指数。确定指数h、指数k以及指数l的方法将在下文描述。(1)当平面穿过所选择坐标的轴的中心时，应经由恰当的平行移动将所述平面移动到与所述平面平行的另一平面，或应在另一单位单元上创建新的坐标轴线的中心。(2)经由以上过程，结晶平面将与三条轴线相接，或平行放置。此处，与平面和中心相交的轴点之间的距离用晶格常数a、晶格常数b以及晶格常数c表达。(3)计算所获得的数a、数b以及数c的倒数。平行于平面的轴假定在无穷大处与平面相接且因此设置为零。(4)三个倒数乘以或除以公共数以变为一组最小整数，例如h、k以及l。(5)最后，在圆括号中不带逗号地表达整数指数。也就是说，整数指数表达为(hkl)。
通过在原点的指数上添加条(bar)或负符号来表达原点的负方向。每一指数的相反符号表示定位为与某一平面平行的平面，所述平面在相反方向上间隔开与某一平面相同的距离。在立方结构中，各自具有相同指数的平面和方向彼此垂直。然而，在其它晶体系统中，并不呈现平面与方向之间的这一简单关系。
晶体面中的原子的布置取决于晶体结构。在具有不同指数的许多平面中，原子堆积因子可相等，但是根据所述晶体面的晶体系统的对称度变化。在原子球模型的情况下，原子堆积因子是指由原子球占据的单位单元中的体积分数。这类平面属于等效原子平面的系列。举例来说，在立方系统中，(111)平面、
Figure BDA0002260826060000051
平面、
Figure BDA0002260826060000052
平面、
Figure BDA0002260826060000053
平面、
Figure BDA0002260826060000054
平面、
Figure BDA0002260826060000055
平面以及
Figure BDA0002260826060000056
平面属于<111>系列。另一方面，在六角结构中，<100>系列仅由(100)平面、
Figure BDA0002260826060000057
平面、(010)平面以及
Figure BDA0002260826060000058
平面构成，这是因为所述平面在结晶学上与(001)平面及
Figure BDA0002260826060000059
平面不一致。此外，在立方系统中，不同次序和不同的负/正符号的相同值的指数可相同。举例来说，
Figure BDA00022608260600000510
平面和
Figure BDA00022608260600000511
平面属于<123>系列。
图1是示出根据本发明概念的实例实施例的晶片和半导体芯片的布局以及从晶片中个别化的半导体封装件的示意性平面图。图2是沿图1的线I-I'截取的截面图。
参考图1和图2，根据本发明概念的实例实施例的半导体封装件可以是晶片级封装件，其中半导体芯片20堆叠于具有硅晶体结构的缓冲基底10上。可以通过利用切割工艺分隔堆叠于晶片(wafer)1上的半导体芯片(chip)20来形成作为晶片级封装件的半导体封装件A。根据本发明概念的半导体封装件不限于图2的半导体封装件A。本发明概念适用于各种类型的半导体封装件，其中设置缓冲基底10且至少一个半导体芯片20安装在缓冲基底10上。缓冲基底10还可称作封装基底。每一半导体芯片20可以是管芯(die)，所述管芯具有形成于其上的集成电路，且每一半导体芯片20可由晶片形成。
在一个实例实施例中，半导体封装件A可包含：缓冲基底10；第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24；连接凸块31和连接凸块32；硅通孔(TSVs)V1和V2；绝缘层50；以及模制构件60。
可通过切割晶片1来形成缓冲基底10。举例来说，缓冲基底10可以是晶片1的一部分，即通过切割晶片1而经分隔及个别化。因此，缓冲基底10可具有与晶片1相同的晶体取向。缓冲基底10可由单晶材料形成，且包含例如具有立方晶体结构(或硅晶体结构)的硅基底。缓冲基底10可以是具有四边形上表面和下表面以及四个外侧表面的长方体。缓冲基底10可包含多个外侧表面。缓冲基底10的外侧表面可包含基本上垂直于缓冲基底10的上表面和下表面的外侧表面以及在缓冲基底10的上表面与下表面之间延伸外侧表面中的任一个。缓冲基底10的外侧表面可包含如图2中所示出的外侧表面As。
缓冲基底10的外侧表面As可与硅晶体结构的解理面形成倾斜角。硅在受损(例如受冲击、破损、经切割等)时沿特定晶面(即解理面)或特定晶体取向分裂。将特定晶面称作解理面。将硅的解理面称为{110}晶面及{111}晶面。{100}晶面也可以是硅的解理面，尽管所述解理面在裂纹传播速度方面比{110}晶面和{111}晶面更慢。举例来说，在硅沿{110}晶面受损时，其中硅的裂隙(即裂纹)生长及传播的方向可与<110>晶体取向相同。在硅沿{111}晶面受损时，其中硅的裂纹生长及传播的方向可与<111>晶体取向相同。在硅沿{100}晶面受损时，其中硅的裂纹生长及传播的方向可与<100>晶体取向相同。
在一个实例实施例中，缓冲基底10的外侧表面As可与(110)晶面或<110>晶体取向(即[110]晶体取向、[-110]晶体取向、[1-10]晶体取向以及[-1-10]晶体取向)形成倾斜角。举例来说，倾斜角可为45°。
半导体芯片20可安装在缓冲基底10的上表面上。半导体芯片20可包含第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24。第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24可在垂直于缓冲基底10的主表面的方向上堆叠于缓冲基底10上。举例来说，第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24可以堆叠于缓冲基底10的上表面上。在一些实施例中，半导体芯片20可与多个绝缘层50交替堆叠。尽管图2示出例如半导体封装件A，四个半导体芯片21、半导体芯片22、半导体芯片23以及半导体芯片24堆叠于半导体封装件A上，但堆叠于半导体封装件A上的半导体芯片数目不限于四。
半导体芯片20可以是具有四边形上表面和下表面以及四个外侧表面Bs的长方体，类似于缓冲基底10。外侧表面Bs中的每一面基本上可为平面，且外侧表面Bs中的每一面基本上可为垂直于缓冲基底10的顶表面。半导体芯片20可布置在缓冲基底10上，使得外侧表面Bs与缓冲基底10的外侧表面As平行。半导体芯片20的外侧表面Bs可与硅晶体结构的解理面形成倾斜角，类似于缓冲基底10的外侧表面As。在一个实施例中，半导体芯片20的外侧表面Bs可与(110)晶面或<110>晶体取向(即[110]晶体取向、[-110]晶体取向、[1-10]晶体取向以及[-1-10]晶体取向)形成倾斜角。举例来说，倾斜角可为45°。
举例来说，半导体芯片20可以是存储器半导体芯片。存储器半导体芯片可以是：易失性存储器半导体芯片，例如动态随机存取存储器(dynamic random access memory；DRAM)或静态RAM(static RAM；SRAM)；或非易失性存储器半导体芯片，例如相变RAM(phase-change RAM；PRAM)、磁性RAM(magneto-resistive RAM；MRAM)、铁电RAM(ferroelectricRAM；FeRAM)或磁阻RAM(resistive RAM；RRAM)。在一实施例中，第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24可以是高带宽存储器(highbandwidth memory；HBM)DRAM半导体芯片。
连接凸块31和连接凸块32可包含下连接凸块31和上连接凸块32。下连接凸块31可布置在缓冲基底10的下表面上。上连接凸块32可插入于缓冲基底10与第一半导体芯片21之间，插入于第一半导体芯片21与第二半导体芯片22之间，插入于第二半导体芯片22与第三半导体芯片23之间，以及插入于第三半导体芯片23与第四半导体芯片24之间，且可将第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24电连接。举例来说，连接凸块31和连接凸块32可包含导电垫、焊料球或焊料凸块中的至少一个。
下连接凸块31可布置在半导体封装件A的最底表面，且可以是用于将半导体封装件A安装在外部基底或插入件上的芯片基底连接凸块。下连接凸块31可由用于从外部操作第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24的控制信号、电力信号或接地信号中的至少一个供应，可由用以从外部将数据存储在第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24中的数据信号供应，或可将存储于第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24中的数据提供到外部。
TSV V1和TSV V2可包含第一TSV V1和第二TSV V2。第一TSV V1可从缓冲基底10的上表面延伸到缓冲基底10的下表面。第二TSV V2可分别从第一半导体芯片21的上表面、第二半导体芯片22的上表面以及第三半导体芯片23的上表面延伸到第一半导体芯片21的下表面、第二半导体芯片22的下表面以及第三半导体芯片23的下表面。TSV V1和TSV V2中的至少一些可具有柱形状。
绝缘层50可以插入于缓冲基底10与第一半导体芯片21之间，插入于第一半导体芯片21与第二半导体芯片22之间，插入于第二半导体芯片22与第三半导体芯片23之间，以及插入于第三半导体芯片23与第四半导体芯片24之间。绝缘层50可围绕上连接凸块32的侧表面。如图2中所示出，绝缘层50的外侧表面Cs可以朝向半导体芯片20的外侧突出一定宽度。然而，本发明概念不限于此。绝缘层50的外侧表面Cs可沿半导体芯片20的外侧表面Bs延伸。举例来说，绝缘层50的外侧表面Cs基本上可与半导体芯片20的外侧表面Bs共延和/或平行。在一个实施例中，其中绝缘层50的外侧表面Cs延伸的方向可与缓冲基底10的硅晶体结构的解理面形成倾斜角。举例来说，绝缘层50可包含底部填充材料，例如绝缘聚合物、环氧树脂或类似物。
模制构件60可围绕绝缘层50的侧表面和第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24的侧表面。模制构件60可在第四半导体芯片24的上表面上形成为一定厚度。模制构件60的下表面可形成在基底10的上表面的一部分上。举例来说，模制构件60可形成在基底10的一部分上，所述基底10的一部分延伸到堆叠在其上的第一半导体芯片21、第二半导体芯片22、第三半导体芯片23以及第四半导体芯片24的区域之外。或者，与图2中所示出的不同，模制构件可不形成在第四半导体芯片24的上表面上，且第四半导体芯片24的上表面可暴露在半导体封装件A的外部。举例来说，模制构件60可包含环氧模塑料(epoxy mold compound；EMC)或类似物。模制构件60的外侧表面Ds可形成与缓冲基底10的外侧表面As相同的平面。
参考图1，在一个实施例中，在晶片1中，平坦区(flat zone)FZ可形成为垂直于或平行于晶片1的[100]晶体取向。举例来说，平坦区FZ可具有与晶片1的(100)晶面相同的平面。当在加工设备中使用具有与(100)晶面具有相同平面的平坦区FZ的晶片1以用于相对于平坦区FZ沿平坦区FZ的法线方向(normal direction)规律地布置半导体芯片20时，半导体芯片20可沿[100]晶体取向在晶片1上排成一列。在这种情况下，半导体芯片20中的每一个的侧表面可与晶片1的[100]晶体取向平行，且可与晶片1的[110]晶体取向形成45°角。划片槽SL可以在晶片1的<100>晶体取向中延伸以与[110]晶体取向形成45°角。当沿在晶片1的<100>晶体取向中延伸的划片槽SL切割晶片1时，可形成具有侧表面的半导体封装件A，所述侧表面与晶片1的解理面(即{110}晶面)和<110>晶体取向形成倾斜角。
通常，半导体芯片在晶片上布置于<110>晶体取向中，所述半导体芯片的主表面是(100)晶面且所述半导体芯片的平坦区FZ具有(110)晶面，且划片槽在<110>晶体取向中延伸。因此，在裂纹于晶片中在<110>晶体取向(其为解理取向)中出现的情况下，由于在半导体封装件的组合期间在安装半导体芯片时对晶片施加的冲击，裂纹可轻易地沿划片槽传播。因此，在本发明概念中，半导体芯片20布置在与解理取向(或解理面)形成倾斜角的方向上，使得即使在裂纹与晶片1中在解理方向上出现时，仍可由于半导体芯片20而阻止裂纹的传播。举例来说，多个半导体芯片20可布置在晶片1上的阵列中，使得切割线SL与[110]晶体取向成一角度(例如45°角)。因此，可极大地提高半导体封装件的制造产量。
在一个实施例中，布置于缓冲基底10上的半导体芯片20中的至少一个可具有与缓冲基底10(或晶片1)类似的硅晶体结构，且半导体芯片20可布置为使得半导体芯片20的<110>晶面与晶片1或缓冲基底10的解理面形成倾斜角。举例来说，半导体封装件A的缓冲基底10的{110}晶面与半导体芯片20的{110}晶面相对于彼此形成45°角。
图3是示出根据本发明概念的实例实施例的晶片和半导体芯片的布局以及从晶片中个别化的半导体封装件的示意性平面图。沿图3的线I-I'截取的截面图可与沿图1的线I-I'截取的截面图相同。图4是示出根据本发明概念的实例实施例的晶片和半导体芯片的布局以及从晶片中个别化的半导体封装件的示意性平面图。沿图4的线I-I'截取的截面图可与沿图1的线I-I'截取的截面图相同。在图1到图4中，相同的附图编号表示相同组件，且为了简洁描述起见，本文将不会重复描述。
参考图3，在一个实施例中，可以在晶片2上形成垂直于或平行于[110]晶体取向的平坦区FZ。也就是说，平坦区FZ可具有与(110)晶面相同的平面。当在平坦区FZ与[110]晶面具有相同的平面的情况下使用加工设备以在晶片2上于[100]晶体取向中规律地布置半导体芯片20时，半导体芯片20可在晶片2上在[100]晶体取向中排成一列。或者，在光刻工艺中，可将掩模图案的布置的方向设置为平行于[100]晶体取向，使得半导体芯片20可在[100]晶体取向中布置于晶片2上。类似于图1，划片槽SL可以在<100>晶体取向中延伸以与[110]晶体取向以形成45°。当沿在<100>晶体取向中延伸的划片槽SL切割晶片2时，可形成半导体封装件B，所述半导体封装件B包含与晶片2的解理面(即{110}晶面)和<110>晶体取向形成倾斜角的侧表面。
在一个实施例中，如上文参考图1所描述，布置在半导体封装件B的缓冲基底10上半导体芯片20中的至少一个的可具有与缓冲基底10(或晶片2)类似的硅晶体结构，且半导体芯片20可布置为使得半导体芯片20的{110}晶面(即(110)晶面)与晶片2或缓冲基底10的解理面(即{110}晶面)形成倾斜角。举例来说，半导体封装件A的缓冲基底10的{110}晶面与半导体芯片20的{110}晶面可以相对于彼此形成45°角。
参考图4，半导体封装件C的外侧表面As可相对于多个解理面中的每一个形成倾斜角α°。倾斜角α°可大于或等于1°且小于45°。在一些实例实施例中，倾斜角α°可以小于或等于44°。在一个实施例中，多个解理面可包含{110}晶面和{100}晶面。半导体封装件C的外侧表面As和半导体芯片20中的每一个的外侧表面Bs可以分别不同于{110}晶面和{100}晶面。举例来说，半导体芯片20中的每一个的外侧表面Bs可以相对于{110}晶面和{100}晶面成倾斜角。
图5到图10示意性地示出根据本发明概念的实例实施例的制造半导体封装件的方法的图。图6是沿图5的线II-II'截取的截面图。图8是沿图7的线III-III'截取的截面图。图10是沿图9的线IV-IV'截取的截面图。
参考图5和图6，TSV 120可形成为穿过硅晶片100(还称作硅基底)，且互连层110可形成在硅晶片100上。尽管为方便解释，图6示出TSV 120具有柱形状且连接到连接电极130，但本发明概念不限于此，且多个TSV 120可根据电信号形成且可单独地连接到连接电极130。电连接到TSV 120的连接电极130可布置在互连层110上。电连接到连接电极130的连接凸块140可分别形成在互连层110上。在一个实施例中，硅晶片100可包含平坦区FZ或缺口(未绘示)。举例来说，平坦区FZ的法线方向可与硅晶体结构的<100>晶体取向相同。
参考图7和图8，可形成覆盖互连层110和连接凸块140的离型层410，且可在离型层410上形成保护层400。离型层410形成为易于移除保护层400，且可由与布线层110和连接凸块140具有低粘合力的材料形成。举例来说，离型层410可由聚合物或UV膜形成。离型层410的厚度可小于布线层110的厚度。保护层400可覆盖离型层410。保护层400可以在之后加工期间中保护基底100免受外部侵害。保护层400可以由具有高强度、高热阻以及高弹力系数的材料形成。举例来说，保护层400可包括环氧树脂系列材料、热固性物材料、热塑性材料或UV处理材料。
粘合层420可形成在晶片载体500上，且保护层400的上表面可通过翻转具有保护层400的硅晶片100而粘附到粘合层420上。晶片载体500可以是用于促进叠加半导体芯片及形成模制构件的过程的临时载体。硅晶片100的暴露表面可由研磨器440研磨以暴露TSV120。
参考图9和图10，多个半导体芯片200可布置在硅晶片100的表面上。多个半导体芯片200可以电和/或物理连接到TSV 120。举例来说，多个半导体芯片200可经由连接凸块230电和/或物理连接到TSV 120。多个半导体芯片200可布置为使得所述多个半导体芯片的外侧表面平行于[100]晶体取向且相对于[110]晶体取向成一角度。尽管附图中未绘示，但覆盖多个半导体芯片200和晶片100的模制构件60可随后形成。晶片100可经倒转，且晶片载体500、粘合层420、保护层400以及离型层410可经移除。沿划片槽SL的晶片100和模制构件60可切割为单独半导体封装件。举例来说，沿切割线SL切割晶片100可通过沿相对于晶片100的<110>晶体方向为45°的方向切割晶片100来执行。
根据本发明概念的实例实施例，可控制晶片级封装件中使用的基底的晶体取向和基底上的半导体芯片的布置方向，从而当在基底上安装半导体芯片时，阻止可能出现在基底中的裂纹的传播。因此，可降低晶片级封装件的制造期间的缺陷率。
虽然已参考附图描述本发明概念的实施例，但所属领域的技术人员应理解，可在不脱离本发明概念的范围且不改变本发明的基本特征的情况下进行各种修改。因此，应当仅在描述性意义上而非出于限制目的考虑上述实施例。

Claims (20)

1.一种半导体封装件，包括：
缓冲基底，包括硅晶体结构；以及
至少一个半导体芯片，设置于所述缓冲基底上且具有上表面、下表面以及多个侧表面，
其中所述多个侧表面相对于所述缓冲基底的解理面成倾斜角。
2.根据权利要求1所述的半导体封装件，其中所述缓冲基底的所述解理面包括所述硅晶体结构的{110}晶面、{111}晶面以及{100}晶面中的至少一个。
3.根据权利要求1所述的半导体封装件，其中所述多个侧表面中的至少一个相对于所述缓冲基底的所述解理面形成45°角。
4.根据权利要求1所述的半导体封装件，
其中所述缓冲基底的所述解理面包括所述硅晶体结构的{110}晶面和{100}晶面，以及
其中所述多个侧表面中的至少一个相对于所述{110}晶面形成大于1°且小于45°的角度。
5.根据权利要求1所述的半导体封装件，
其中所述缓冲基底包括作为主表面的所述硅晶体结构的{100}晶面，以及
其中所述多个侧表面中的至少一个相对于{110}晶面形成倾斜角，所述{110}晶面是所述缓冲基底的所述解理面。
6.根据权利要求5所述的半导体封装件，其中所述倾斜角为45°。
7.根据权利要求6所述的半导体封装件，其中所述多个侧表面中的至少一个与所述硅晶体结构的所述{100}晶面相同。
8.根据权利要求1所述的半导体封装件，
其中所述缓冲基底包括划片槽，在以平面图查看时，所述划片槽延伸以包围所述至少一个半导体芯片，以及
其中所述划片槽延伸的方向与所述硅晶体结构的晶体取向形成倾斜角。
9.根据权利要求1所述的半导体封装件，
其中所述至少一个半导体芯片包括硅晶体结构，以及
其中所述至少一个半导体芯片的所述硅晶体结构的{110}晶面相对于所述缓冲基底的所述解理面形成倾斜角。
10.根据权利要求1所述的半导体封装件，其中所述至少一个半导体芯片于其中包括多个硅通孔。
11.根据权利要求10所述的半导体封装件，
其中所述至少一个半导体芯片包括电连接到所述多个硅通孔的多个连接凸块，以及
其中所述多个连接凸块包括导电垫、焊料球以及焊料凸块中的至少一个。
12.一种半导体封装件，包括：
硅基底，包括硅晶体结构和作为主表面的{100}晶面；以及
半导体芯片，设置于所述硅基底上且具有四边形的上表面，
其中所述半导体芯片包括外侧表面，在以平面图查看时，所述外侧表面相对于所述硅晶体结构的<110>晶体取向形成倾斜角。
13.根据权利要求12所述的半导体封装件，其中所述倾斜角为45°。
14.根据权利要求12所述的半导体封装件，其中所述外侧表面平行于所述硅晶体结构的所述<100>晶体取向延伸。
15.根据权利要求12所述的半导体封装件，其中所述半导体芯片于其中包括多个硅通孔。
16.根据权利要求15所述的半导体封装件，
其中所述半导体芯片包括电连接到所述多个硅通孔的多个连接凸块，以及
其中所述多个连接凸块包括导电垫、焊料球以及焊料凸块中的至少一个。
17.根据权利要求12所述的半导体封装件，其中在所述半导体封装件中，多个半导体芯片与多个绝缘层交替地堆叠。
18.根据权利要求17所述的半导体封装件，其中所述多个绝缘层的外侧表面在相对于所述硅晶体结构的所述<110>晶体取向成一角度的方向上延伸。
19.一种制造半导体封装件的方法，包括：
制备缓冲基底，所述缓冲基底包括硅晶体结构和作为主表面的(100)晶面；
在所述缓冲基底上布置半导体芯片；
形成模制构件以覆盖所述缓冲基底和所述半导体芯片；以及
通过切割所述模制构件和所述缓冲基底来形成单独半导体封装件，使得所述单独半导体封装件中的每一个包括至少一个半导体芯片，
其中在所述缓冲基底上布置所述半导体芯片包括布置所述半导体芯片使得所述半导体芯片的外侧表面相对于<110>晶体取向形成45°角。
20.根据权利要求19所述的制造半导体封装件的方法，其中形成所述单独半导体封装件包括在相对于所述<110>晶体取向形成所述45°角的方向上切割所述缓冲基底。
CN201911070673.3A 2019-02-21 2019-11-05 半导体封装件以及制造半导体封装件的方法 Pending CN111599780A (zh)

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