CN111586985A - Manufacturing method of high-flatness multilayer circuit board - Google Patents
Manufacturing method of high-flatness multilayer circuit board Download PDFInfo
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- CN111586985A CN111586985A CN202010356622.3A CN202010356622A CN111586985A CN 111586985 A CN111586985 A CN 111586985A CN 202010356622 A CN202010356622 A CN 202010356622A CN 111586985 A CN111586985 A CN 111586985A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 90
- 229910052802 copper Inorganic materials 0.000 claims abstract description 87
- 239000010949 copper Substances 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000011347 resin Substances 0.000 claims abstract description 26
- 229920005989 resin Polymers 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000005553 drilling Methods 0.000 claims abstract description 11
- 238000003466 welding Methods 0.000 claims abstract description 10
- 238000007747 plating Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 157
- 238000003825 pressing Methods 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 5
- 239000011241 protective layer Substances 0.000 claims description 3
- 238000012360 testing method Methods 0.000 claims description 3
- 230000008685 targeting Effects 0.000 claims 2
- 238000010030 laminating Methods 0.000 abstract 2
- 238000001035 drying Methods 0.000 abstract 1
- 239000002904 solvent Substances 0.000 description 10
- 239000000126 substance Substances 0.000 description 10
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000001680 brushing effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0085—Apparatus for treatments of printed circuits with liquids not provided for in groups H05K3/02 - H05K3/46; conveyors and holding means therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/282—Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides a method for manufacturing a high-flatness multilayer circuit board, which comprises the following steps: preparing materials, treating a first copper substrate, treating a second copper substrate, filling resin for one time, laminating for one time, treating an inner layer plate, filling resin for two times, laminating for two times, drilling, plating copper, drying a film, etching, plating tin, preventing welding for two times, writing and fishing. The invention can solve the problems of uneven surface of the multilayer circuit board and overlarge circuit etching amount in the prior art.
Description
Technical Field
The invention relates to the technical field of circuit board processing, in particular to a manufacturing method of a high-flatness multilayer circuit board.
Background
Circuit boards, also known as printed circuit boards, are providers of electrical connections for electronic components. The development of the circuit board has been over 100 years old, the design is mainly a layout design, and the circuit board has the main advantages of greatly reducing errors of wiring and assembly and improving the automation level and the production labor rate. The printed circuit board can be divided into a single-sided board, a double-sided board, a four-layer board, a six-layer board and other multi-layer circuit boards according to the number of layers of the circuit board.
For a multilayer circuit board, as shown in fig. 1, a part of the processing process is generally to laminate a first copper substrate 3, a second prepreg 4 and a second copper substrate 5 to manufacture an inner layer board, and then laminate an upper layer board, an inner layer board and a lower layer board to prepare a multilayer board, which needs to be subjected to two lamination processes, because the inner layer board and the multilayer board need to be etched to manufacture an inner layer circuit in the manufacturing process, a hollowed-out area 8 can be formed after the surfaces of the first copper substrate 3 and the second copper substrate 5 are etched, and in the two lamination processes, due to the existence of the hollowed-out area, depressions 9 can be formed on the upper end surface and the lower end surface of the formed inner layer board or multilayer board, which affects the surface smoothness of the circuit board and further affects the wiring precision.
On the other hand, the etching process of the circuit board is usually chemical solvent etching, and the chemical solvent etching copper foil has a certain amount of undercut, so that when the circuit exposure pattern is actually designed, a compensation area is usually added at the edge of the circuit, that is, the width of the circuit is increased, so that the actual circuit is close to the ideal circuit. Normally, the compensation width of the compensation circuit is 2.4mil, however, in the actual process, as shown in fig. 2, in a partial area of the circuit board, such as near the integrated circuit module, due to the wide etching range, more chemical solvent needs to be coated at the position, after etching, the circuit edge near the position will generate a bite 10, i.e. one side of the actual circuit is shortened by 2.0mil, thereby affecting the conductive performance of the circuit.
Disclosure of Invention
Aiming at the problems, the invention provides a method for manufacturing a multilayer circuit board with high flatness, which can solve the problems of uneven surface and overlarge circuit corrosion of the multilayer circuit board manufactured by the prior art.
In order to achieve the purpose, the invention is solved by the following technical scheme:
a manufacturing method of a high-flatness multilayer circuit board comprises the following steps:
s1, preparing materials: preparing an upper plate, a first semi-solidified plate, a first copper substrate, a second semi-solidified plate, a second copper substrate, a third semi-solidified plate and a lower plate;
s2 first copper substrate treatment: film pasting, developing, exposing and etching are carried out on the lower end face of the first copper substrate, a first inner-layer circuit which is formed in a hollow mode is obtained after the film is removed, and a target hole is formed in the first copper substrate;
s3 second copper substrate treatment: film pasting, developing, exposing and etching are carried out on the lower end face of the second copper substrate, a second inner-layer circuit which is formed in a hollow mode is obtained after the film is removed, and a target hole is formed in the second copper substrate;
s4 primary resin caulking: performing resin printing on the hollow areas formed by etching on the first copper substrate and the second copper substrate to enable resin to be filled in the hollow areas;
s5, primary pressing, namely pressing and molding the first copper substrate, the second prepreg and the second copper substrate to obtain an inner layer plate;
s6, processing the inner layer plate, namely, pasting, developing, exposing and etching the upper end surface and the lower end surface of the inner layer plate, removing the film to obtain a third inner layer circuit and a fourth inner layer circuit which are formed in a hollow way, and shooting holes on the inner layer plate;
s7 secondary resin caulking: performing resin printing on a hollow area formed by etching the inner layer plate to fill resin in the hollow area;
s8, secondary pressing, namely pressing and molding the upper layer plate, the first semi-solidified plate, the inner layer plate, the third semi-solidified plate and the lower layer plate to obtain a multilayer plate;
s9, drilling, namely drilling the multilayer board to form a through hole;
s10, copper plating, namely, performing copper electroplating on the upper end face and the lower end face of the multilayer board, and forming a first surface copper layer and a second surface copper layer on the surfaces of the third inner-layer circuit and the fourth inner-layer circuit;
s11 dry film: carrying out film pasting, developing and exposure on the surfaces of the first surface copper layer and the second surface copper layer to form a first outer layer circuit pattern and a second outer layer circuit pattern;
s12 etching: etching off the non-circuit part on the first outer layer circuit pattern and the second outer layer circuit pattern to form a first outer layer circuit and a second outer layer circuit, and then removing the dry film;
s13 tin plating: electroplating tin on two end faces of the first outer layer circuit and the second outer layer circuit, and covering a tin film protective layer on the upper ends of the first outer layer circuit and the second outer layer circuit after film pasting, developing, exposing and etching;
s14 solder mask: printing a layer of uniform solder mask ink on the upper sides of the first outer layer circuit and the second outer layer circuit, and defoaming in vacuum to obtain a first solder mask ink layer;
s15 secondary solder mask: a layer of uniform second welding-resistant ink layer is printed on the upper side of the first welding-resistant ink layer, so that short circuit caused during welding is prevented;
characters S16: printing characters;
s17 type fishing: and (5) routing the appearance according to the structure of the finished product, and completing the manufacture after V-CUT and testing.
Specifically, after etching and stripping, the steps S2, S3, and S6 all need to be microetched to roughen the surfaces of the first inner layer circuit, the second inner layer circuit, the third inner layer circuit, and the fourth inner layer circuit.
Specifically, after the drilling in step S9, the multi-layer board is further subjected to a dry brushing machine to grind the burrs on the edges of the through holes.
Specifically, after the first copper layer and the second copper layer are manufactured in step S10, the surfaces of the first copper layer and the second copper layer need to be subjected to microetching treatment to roughen the surfaces of the first copper layer and the second copper layer.
Specifically, in the process of step S11, a normal compensation line and a widened compensation line need to be marked off on the first outer layer line pattern and the second outer layer line pattern, the compensation width of the normal compensation line is 2.4mil, and the compensation width of the widened compensation line is 4.4 mil.
The invention has the beneficial effects that:
the manufacturing method of the multilayer circuit board increases two resin joint filling processes, resin printing is carried out on the hollow areas formed on the first copper substrate and the second copper substrate through etching, and resin printing is carried out on the hollow areas formed on the inner layer board through etching, so that the resin is filled in the hollow areas, the problem of uneven surface generated after subsequent pressing can be prevented, and a flat and reliable reference plane is provided for manufacturing the circuit layer;
secondly, the compensation width is increased aiming at the position with large etching amount on the circuit board, the phenomenon that the edge of the circuit is reduced or lost due to overlarge etching amount of a chemical solvent is prevented, and the circuit layer is ensured to have reliable conductive capability.
Drawings
FIG. 1 is a schematic diagram of a prior art process for forming an inner layer board.
Fig. 2 is a schematic structural view of a copper foil after etching in the prior art.
FIG. 3 is a schematic structural diagram of steps S1-S5 according to the present invention.
FIG. 4 is a schematic structural diagram of steps S6-S8 according to the present invention.
Fig. 5 is a schematic structural diagram of the first outer layer circuit and the second outer layer circuit obtained in step S12.
The reference signs are: the copper-clad laminate comprises an upper plate 1, a first semi-cured plate 2, a first copper substrate 3, a second semi-cured plate 4, a second copper substrate 5, a third semi-cured plate 6, a lower plate 7, a hollow area 8, a concave part 9 and an undercut part 10.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but the embodiments of the present invention are not limited thereto.
Referring to FIGS. 3-5:
a manufacturing method of a high-flatness multilayer circuit board comprises the following steps:
s1, preparing materials: preparing an upper plate 1, a first semi-solidified plate 2, a first copper substrate 3, a second semi-solidified plate 4, a second copper substrate 5, a third semi-solidified plate 6 and a lower plate 7;
s2 first copper substrate treatment: the lower end face of the first copper substrate 3 is subjected to film pasting, developing, exposing and etching, a first inner-layer circuit formed in a hollowed mode is obtained after the film is removed, a target hole is formed in the first copper substrate 3 after the first copper substrate 3 is subjected to target hole punching, the target hole is needed to be used for counterpoint after the first copper substrate 3, the second prepreg 4 and the second copper substrate 5 are pressed and molded, so that the counterpoint accuracy can meet the production requirement, otherwise, the open circuit condition is caused due to dislocation among layers, and the reliability is influenced;
s3 second copper substrate treatment: the lower end face of the second copper substrate 5 is subjected to film pasting, developing, exposing and etching, a second inner-layer circuit formed in a hollowed mode is obtained after the film is removed, a target hole is formed in the second copper substrate 5 after the second copper substrate 5 is subjected to target hole punching, and the target hole is needed to be used for counterpoint due to the fact that the first copper substrate 3, the second prepreg 4 and the second copper substrate 5 need to be pressed and formed subsequently, so that the counterpoint accuracy can meet the production requirement, otherwise, the layers are staggered, an open-circuit condition is caused, and reliability is affected;
s4 primary resin caulking: resin printing is carried out on the hollowed-out areas 8 formed by etching on the first copper substrate 3 and the second copper substrate 5, so that the resin is filled in the hollowed-out areas 8, the surface of the resin layer is not required to be ground after printing, and direct pressing is carried out, wherein in order to improve the adhesion degree, the resin material is consistent with the material of the first semi-cured plate 2;
s5, primary pressing, namely pressing and molding the first copper substrate 3, the second prepreg 4 and the second copper substrate 5 to obtain an inner layer plate;
s6, processing the inner layer plate, namely, pasting, developing, exposing and etching the upper end surface and the lower end surface of the inner layer plate, removing the film to obtain a third inner layer circuit and a fourth inner layer circuit which are formed in a hollow way, and shooting holes on the inner layer plate;
s7 secondary resin caulking: performing resin printing on a hollow area 8 formed on the inner-layer plate through etching, and filling resin into the hollow area 8;
s8, secondary pressing, namely pressing and molding the upper layer plate 1, the first semi-solidified plate 2, the inner layer plate, the third semi-solidified plate 6 and the lower layer plate 7 to obtain a multilayer plate;
s9, drilling, namely drilling the multilayer board to form a through hole;
s10, copper plating, namely, performing copper electroplating on the upper end face and the lower end face of the multilayer board, and forming a first surface copper layer and a second surface copper layer on the surfaces of the third inner-layer circuit and the fourth inner-layer circuit;
s11 dry film: carrying out film pasting, developing and exposure on the surfaces of the first surface copper layer and the second surface copper layer to form a first outer layer circuit pattern and a second outer layer circuit pattern;
s12 etching: etching off the non-circuit part on the first outer layer circuit pattern and the second outer layer circuit pattern to form a first outer layer circuit and a second outer layer circuit, and then removing the dry film;
s13 tin plating: electroplating tin on two end faces of the first outer layer circuit and the second outer layer circuit, and covering a tin film protective layer on the upper ends of the first outer layer circuit and the second outer layer circuit after film pasting, developing, exposing and etching;
s14 solder mask: printing a layer of uniform solder mask ink on the upper sides of the first outer layer circuit and the second outer layer circuit, and defoaming in vacuum to obtain a first solder mask ink layer;
s15 secondary solder mask: a layer of uniform second welding-resistant ink layer is printed on the upper side of the first welding-resistant ink layer, so that short circuit caused during welding is prevented;
characters S16: printing characters;
s17 type fishing: and (5) routing the appearance according to the structure of the finished product, and completing the manufacture after V-CUT and testing.
Preferably, after etching and stripping in steps S2, S3, and S6, microetching is performed to roughen the surfaces of the first inner layer circuit, the second inner layer circuit, the third inner layer circuit, and the fourth inner layer circuit, so as to improve the adhesion between the laminated interlayer boards, and ammonium persulfate or sodium persulfate may be used in the microetching process.
Preferably, after the drilling step S9, the multi-layer board is further processed by a dry brushing machine to grind the burrs on the edges of the through holes.
Preferably, after the first copper layer and the second copper layer are manufactured in step S10, the surfaces of the first copper layer and the second copper layer need to be subjected to microetching treatment to roughen the surfaces of the first copper layer and the second copper layer, so as to improve the adhesion between the first copper layer and the tin film protection layer, and ammonium persulfate or sodium persulfate can be used in the microetching treatment process.
Preferably, in the step S11, the etching process of the present application is performed by using a chemical solvent to perform a chemical etching treatment, the chemical solvent may be a common circuit board etching solution such as copper chloride, ferric chloride, ammonium persulfate, sulfuric acid, and the like, and since the reaction process of the chemical solvent and the copper foil is difficult to control, the reaction speed is usually determined by adjusting factors such as the concentration of the chemical solvent, the reaction temperature, or the reaction time, but the reaction process is difficult to accurately control. Particularly, for a partial area of the circuit board, such as the vicinity of the integrated circuit module, since a larger area for accommodating the chip needs to be reserved, the etching range is wider, more chemical solvent needs to be coated at the position, and after etching, as the excessive chemical solvent is deposited at the position, a bite part is generated at the edge of the circuit near the position, thereby affecting the conductive performance of the circuit. Therefore, the normal compensation line and the widened compensation line are divided from the first outer layer line pattern and the second outer layer line pattern, the compensation width of the normal compensation line is 2.4mil, the widened compensation line, namely the line at the position near the integrated circuit module, is to ensure that the line width at the position is consistent with the line width at other positions, and the compensation width of the widened compensation line is set to be 4.4mil to compensate the bite part caused by the excessive bite amount at the position.
The above examples only show one embodiment of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (5)
1. A manufacturing method of a multilayer circuit board with high flatness is characterized by comprising the following steps:
s1, preparing materials: preparing an upper plate (1), a first prepreg (2), a first copper substrate (3), a second prepreg (4), a second copper substrate (5), a third prepreg (6) and a lower plate (7);
s2 first copper substrate treatment: pasting a film on the lower end face of the first copper substrate (3), developing, exposing and etching, removing the film to obtain a hollowed-out first inner-layer circuit, and performing targeting hole drilling on the first copper substrate (3);
s3 second copper substrate treatment: pasting, developing, exposing and etching the lower end face of the second copper substrate (5), removing the film to obtain a hollowed-out second inner-layer circuit, and performing targeting hole drilling on the second copper substrate (5);
s4 primary resin caulking: resin printing is carried out on the hollowed-out areas (8) formed by etching on the first copper substrate (3) and the second copper substrate (5), so that the resin is filled in the hollowed-out areas (8);
s5, primary pressing, namely pressing and molding the first copper substrate (3), the second prepreg (4) and the second copper substrate (5) to obtain an inner layer plate;
s6, processing the inner layer plate, namely, pasting, developing, exposing and etching the upper end surface and the lower end surface of the inner layer plate, removing the film to obtain a third inner layer circuit and a fourth inner layer circuit which are formed in a hollow way, and shooting holes on the inner layer plate;
s7 secondary resin caulking: carrying out resin printing on a hollow area (8) formed on the inner-layer plate through etching, and filling resin into the hollow area (8);
s8, secondary pressing, namely pressing and molding the upper layer plate (1), the first semi-solidified plate (2), the inner layer plate, the third semi-solidified plate (6) and the lower layer plate (7) to obtain a multilayer plate;
s9, drilling, namely drilling the multilayer board to form a through hole;
s10, copper plating, namely, performing copper electroplating on the upper end face and the lower end face of the multilayer board, and forming a first surface copper layer and a second surface copper layer on the surfaces of the third inner-layer circuit and the fourth inner-layer circuit;
s11 dry film: carrying out film pasting, developing and exposure on the surfaces of the first surface copper layer and the second surface copper layer to form a first outer layer circuit pattern and a second outer layer circuit pattern;
s12 etching: etching off the non-circuit part on the first outer layer circuit pattern and the second outer layer circuit pattern to form a first outer layer circuit and a second outer layer circuit, and then removing the dry film;
s13 tin plating: electroplating tin on two end faces of the first outer layer circuit and the second outer layer circuit, and covering a tin film protective layer on the upper ends of the first outer layer circuit and the second outer layer circuit after film pasting, developing, exposing and etching;
s14 solder mask: printing a layer of uniform solder mask ink on the upper sides of the first outer layer circuit and the second outer layer circuit, and defoaming in vacuum to obtain a first solder mask ink layer;
s15 secondary solder mask: a layer of uniform second welding-resistant ink layer is printed on the upper side of the first welding-resistant ink layer, so that short circuit caused during welding is prevented;
characters S16: printing characters;
s17 type fishing: and (5) routing the appearance according to the structure of the finished product, and completing the manufacture after V-CUT and testing.
2. The method as claimed in claim 1, wherein the etching and stripping steps S2, S3, and S6 are performed to form micro-etching treatment to roughen the surfaces of the first, second, third, and fourth inner traces.
3. The method as claimed in claim 1, wherein after the step S9, the multi-layer board is further processed by a dry-brushing machine to smooth the edge of the through hole.
4. The method as claimed in claim 1, wherein after the step S10 of fabricating the first and second copper layers, the surfaces of the first and second copper layers are further processed by micro etching to roughen the surfaces of the first and second copper layers.
5. The method as claimed in claim 1, wherein in the step S11, the normal compensation trace and the widened compensation trace are required to be separated from the first outer trace pattern and the second outer trace pattern, the compensation width of the normal compensation trace is 2.4mil, and the compensation width of the widened compensation trace is 4.4 mil.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010356622.3A CN111586985A (en) | 2020-04-29 | 2020-04-29 | Manufacturing method of high-flatness multilayer circuit board |
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| CN202010356622.3A CN111586985A (en) | 2020-04-29 | 2020-04-29 | Manufacturing method of high-flatness multilayer circuit board |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112937021A (en) * | 2021-02-24 | 2021-06-11 | 惠州联合铜箔电子材料有限公司 | Reverse copper foil processing equipment |
| CN113923894A (en) * | 2021-09-07 | 2022-01-11 | 广州兴森快捷电路科技有限公司 | Super-flatness PCB manufacturing method for chip testing and PCB |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104918419A (en) * | 2014-03-11 | 2015-09-16 | 深南电路有限公司 | Thick copper circuit board processing method |
| CN105188269A (en) * | 2015-10-28 | 2015-12-23 | 广州杰赛科技股份有限公司 | Ultra-thick copper circuit board and manufacturing method thereof |
| CN108024455A (en) * | 2017-12-14 | 2018-05-11 | 悦虎电路(苏州)有限公司 | A kind of production method of 1.5mil wiring boards |
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2020
- 2020-04-29 CN CN202010356622.3A patent/CN111586985A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104918419A (en) * | 2014-03-11 | 2015-09-16 | 深南电路有限公司 | Thick copper circuit board processing method |
| CN105188269A (en) * | 2015-10-28 | 2015-12-23 | 广州杰赛科技股份有限公司 | Ultra-thick copper circuit board and manufacturing method thereof |
| CN108024455A (en) * | 2017-12-14 | 2018-05-11 | 悦虎电路(苏州)有限公司 | A kind of production method of 1.5mil wiring boards |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112937021A (en) * | 2021-02-24 | 2021-06-11 | 惠州联合铜箔电子材料有限公司 | Reverse copper foil processing equipment |
| CN113923894A (en) * | 2021-09-07 | 2022-01-11 | 广州兴森快捷电路科技有限公司 | Super-flatness PCB manufacturing method for chip testing and PCB |
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Application publication date: 20200825 |