CN111584593A

CN111584593A - Display panel, display device, and method for manufacturing display panel

Info

Publication number: CN111584593A
Application number: CN202010448063.9A
Authority: CN
Inventors: 谢学武; 艾雨; 孙诗; 孔玉宝; 刘博文; 刘浩; 张阿猛
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2020-05-25
Filing date: 2020-05-25
Publication date: 2020-08-25
Anticipated expiration: 2040-05-25
Also published as: CN111584593B; WO2021238549A1

Abstract

The application discloses a display panel, a display device and a manufacturing method of the display panel. The sub-pixel area of the display panel comprises a driving area and a display area, the driving area comprises a transistor area and a functional area, the functional area comprises a light shielding layer, a buffer layer, an active layer, a grid insulation layer, a first metal layer, a dielectric layer, a second metal layer, a passivation layer and a first electrode layer which are sequentially stacked, and orthographic projections of the light shielding layer, the active layer, the first metal layer, the second metal layer and the first electrode layer on a substrate respectively have a public overlapping area. According to the technical scheme that this application embodiment provided, set up a plurality of capacitive electrode through the drive area at display panel, can solve and set up a plurality of electric capacity and obtain the little and big energy storage capacitor of capacitance value of area occupied.

Description

Display panel, display device, and method for manufacturing display panel

Technical Field

The present disclosure relates generally to the field of display technologies, and more particularly, to a display panel, a display device, and a method of manufacturing a display panel.

Background

Organic Light Emitting Diode (OLED) display devices have good image quality, self-luminescence, no viewing angle impediment, large operating temperature range, and the like, and have been considered as a new generation of flat panel display devices that are the most valuable in the market after liquid crystal display and plasma display devices. The design structure of the TFT circuit is also important in order to obtain an OLED device with good display performance. In the design process of TFT circuits, it is desirable to obtain a large enough capacitance to enhance the charging effect during driving, and for bottom-emitting OLED devices, it is also desirable to increase the aperture ratio, and the increase of the area of the capacitor electrode will decrease the aperture ratio.

Disclosure of Invention

In view of the above-mentioned drawbacks or disadvantages in the related art, it is desirable to provide a display panel having a large capacitance and an improved aperture ratio, a display device, and a method of manufacturing the display panel.

In a first aspect, a display panel is provided, where a sub-pixel region of the display panel includes a driving region and a display region, the driving region includes a transistor region and a functional region, and the functional region includes a substrate, a light shielding layer, a buffer layer, an active layer, a gate insulating layer, a first metal layer, a dielectric layer, a second metal layer, a passivation layer, and an electrode layer, which are sequentially stacked, where orthographic projections of the light shielding layer, the active layer, the first metal layer, the second metal layer, and the first electrode layer on the substrate have a common overlapping region.

In some embodiments of the present invention, the,

the light shielding layer, the active layer, the first metal layer, the second metal layer and the first electrode layer are respectively used as electrodes of the energy storage capacitor.

In some embodiments of the present invention, the,

the shading layer and the active layer are respectively used as a first electrode and a second electrode of the first capacitor;

the first metal layer and the active layer are used as a first electrode and a second electrode of the second capacitor;

the first metal layer and the second metal layer are respectively used as a first electrode and a second electrode of the third capacitor;

the first electrode layer and the second metal layer are respectively used as a first electrode and a second electrode of the fourth capacitor.

In some embodiments, the second metal layer and the active layer are connected by a first via.

In some embodiments, the light shielding layer and the first metal layer are connected by a second via

(ii) a The first metal layer is connected with the first electrode layer through the third through hole.

In some embodiments, the second metal layer and the first electrode layer are used for external electrical connection, respectively.

In some embodiments, the driving region includes a thin film transistor including a metal shielding layer, an active layer, a gate electrode, a source drain electrode, and a second electrode layer sequentially stacked,

the shading layer and the metal shielding layer are arranged on the same layer;

the active layer and the active layer are arranged in the same layer;

the first metal layer and the grid are arranged on the same layer;

the second metal layer and the source and drain electrodes are arranged on the same layer;

the first electrode layer and the second electrode layer are arranged on the same layer.

In a second aspect, a display device is provided, which includes the display panel included in the embodiments of the present application.

In a third aspect, a method for manufacturing a display panel is provided, in which a sub-pixel region of the display panel includes a driving region and a display region, the driving region includes a functional region and a transistor region, and the method includes the following steps:

forming a light shielding layer and a metal shielding layer in the functional region and the transistor region respectively;

forming a buffer layer;

forming an active layer and an active layer in the functional region and the transistor region, respectively;

forming a gate insulating layer and patterning the gate insulating layer in the transistor region;

coating photoresist, forming a photoresist pattern on the active layer which does not need to be conducted, and conducting the active layer and part of the active layer which needs to be conducted;

removing the photoresist pattern, and respectively forming a first metal layer and a grid in the functional area and the transistor area;

forming a dielectric layer;

forming a second metal layer and a source drain electrode in the functional area and the transistor area respectively;

and forming a passivation layer and an electrode layer.

In a fourth aspect, a method for manufacturing a display panel is provided, in which a sub-pixel region of the display panel includes a driving region and a display region, the driving region includes a functional region and a transistor region, and the method includes the following steps:

forming a buffer layer;

forming a gate in the transistor region;

a conductor active layer and a part of active layer needing to be conductor;

forming a first metal layer in the functional region;

forming a dielectric layer;

and forming a passivation layer and an electrode layer.

According to the technical scheme that this application embodiment provided, set up a plurality of capacitive electrode through the drive area at display panel, can solve and set up a plurality of electric capacity and obtain the little and big energy storage capacitor of capacitance value of area occupied.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 illustrates an exemplary structural block diagram of a display panel according to an embodiment of the present application;

FIG. 2 shows an exemplary cross-sectional view of AA' according to an embodiment of the present application;

fig. 3 illustrates an exemplary flowchart of a method of manufacturing a display panel according to an embodiment of the present application;

fig. 4 illustrates an exemplary flowchart of a method of manufacturing a display panel according to another embodiment of the present application;

fig. 5 to 12 show specific exemplary diagrams according to the method of manufacturing the display panel of fig. 3;

fig. 13 to 15 show specific exemplary diagrams according to the method of manufacturing the display panel in fig. 4.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Referring to fig. 1 and 2, the sub-pixel region of the display panel includes a driving region 20 and a display region 10, the driving region 20 includes a transistor region D1 and a functional region D2, the functional region D2 includes a substrate (not shown), a light shielding layer 101, a buffer layer 102, an active layer 103, a gate insulating layer 104, a first metal layer 105, a dielectric layer 106, a second metal layer 107, a passivation layer 108, and a first electrode layer 109, which are sequentially stacked, wherein orthographic projections of the light shielding layer 101, the active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109 on the substrate respectively have a common overlapping region.

The common overlapping region here refers to a common overlapping region of five of the light-shielding layer 101, the active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109, and is not any two or three of them. The provision of the multi-layered structure of the functional region in the amorphous region of the drive region makes it possible to provide more components in a limited area.

In some embodiments, the light shielding layer 101, the active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109 are respectively used as electrodes of the energy storage capacitor.

The driving circuit of the sub-pixel comprises an energy storage capacitor, the size of the energy storage capacitor directly influences the driving effect of the electroluminescent device, and the driving capability of the electroluminescent device is stronger when the capacitance of the energy storage capacitor is larger. The larger the area of the two oppositely arranged electrodes in the energy storage capacitor is, the larger the capacitance value thereof is, and the increase of the area of the capacitor electrode will increase the occupation ratio of the driving area in the whole sub-pixel area, thereby reducing the occupation ratio of the display area 10 and reducing the aperture ratio of the sub-pixel. The capacitor electrode adopts a mode of connecting a plurality of capacitors in parallel, and the area of the capacitor electrode is reduced. Therefore, how to arrange the electrode level in the functional region will be a key to solve the above-mentioned problems.

The functional region is provided with a plurality of levels capable of being used as capacitance electrodes, and the levels comprise a shading layer 101, an active layer 103, a first metal layer 105, a second metal layer 107 and a first electrode layer 109. The capacitive electrode may be disposed according to the needs of the application scenario, which is not limited herein. In the remaining layers, the buffer layer 102, the gate insulating layer 104, the dielectric layer 106, and the passivation layer 108 may be used as insulating layers between the capacitor electrodes, and may form a thin film capacitor or a parasitic capacitor with the electrodes on both sides.

For example, 2 capacitors can be provided in the functional region of the present application: the light shielding layer 101 and the active layer 103 are respectively arranged as a first electrode and a second electrode of a first capacitor, and the first metal layer 105 and the second metal layer 107 are respectively used as the first electrode and the second electrode of a second capacitor; alternatively, the active layer 103 and the first metal layer 105 are respectively configured as a first electrode and a second electrode of the first capacitor, and the second metal layer 107 and the first electrode layer 109 are respectively configured as a first electrode and a second electrode of the second capacitor. In addition, other setting modes for setting 2 capacitors are also available, and are not described herein again. The capacitors are connected in parallel by connecting the first electrode of the first capacitor with the first electrode of the second capacitor through the via hole and connecting the second electrode of the first capacitor with the second electrode of the second capacitor.

For another example, 3 capacitors may be provided in the functional region: the light shielding layer 101 and the active layer 103 are respectively used as a first electrode and a second electrode of a first capacitor, the first metal layer 105 and the second metal layer 107 are respectively used as a first electrode and a second electrode of a second capacitor, and the first electrode layer 109 and the second metal layer 107 are respectively used as a first electrode and a second electrode of a third capacitor. The second electrode of the second capacitor and the second electrode of the third capacitor are common electrodes. The first electrode of the first capacitor, the first electrode of the second capacitor and the first electrode of the third capacitor are connected through the via holes, and the second electrode of the first capacitor and the second electrode of the second capacitor are connected in parallel. Alternatively, the light shielding layer 101 and the active layer 103 serve as a first electrode and a second electrode of the first capacitor, the first metal layer 105 and the active layer 103 serve as a first electrode and a second electrode of the second capacitor, and the second metal layer 107 and the first electrode layer 109 serve as a first electrode and a second electrode of the third capacitor, respectively. The second electrode of the first capacitor and the second electrode of the second capacitor are common electrodes. The first electrode of the first capacitor, the first electrode of the second capacitor and the first electrode of the third capacitor are connected through the via hole, and the second electrode of the first capacitor and the second electrode of the third capacitor are connected in parallel. In addition, there may be other parallel connection modes with 3 capacitors, which are not described herein.

Note that the display region 10 is used for disposing an electroluminescent device; the drive region 20 is used to provide pixel drive circuitry for driving the electroluminescent devices of the display region 10. The pixel driving circuit comprises an energy storage capacitor and a plurality of thin film transistors, and specifically can comprise structures such as 6T1C (6 thin film transistors plus 1 energy storage capacitor), 7T1C (7 thin film transistors plus 1 energy storage capacitor) and the like. Therefore, the driving region 20 may be divided into a transistor region D1 for disposing a thin film transistor and a functional region D2 for disposing a storage capacitor, as shown in fig. 2. In addition, other transistors in the transistor region, such as a transistor 31, a transistor 32, and a transistor 33, are given in fig. 1. For convenience of representation, fig. 2 shows only one transistor, and in practice, the transistor region may include a plurality of transistors.

In some embodiments, the energy storage capacitor comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor,

the light shielding layer 101 and the active layer 103 are respectively used as a first electrode and a second electrode of the first capacitor;

the first metal layer 105 and the active layer 103 are used as a first electrode and a second electrode of the second capacitor;

the first metal layer 105 and the second metal layer 107 are respectively used as a first electrode and a second electrode of the third capacitor;

the first electrode layer 109 and the second metal layer 107 serve as a first electrode and a second electrode of the fourth capacitor, respectively.

In the above arrangement of the capacitor electrodes, the second electrode of the first capacitor and the second electrode of the second capacitor are common electrodes, the first electrode of the second capacitor and the first electrode of the third capacitor are common electrodes, and the second electrode of the third capacitor and the second electrode of the fourth capacitor are common capacitors. By providing a plurality of common electrodes, 4 capacitors are provided in the functional region by 5 electrodes. The present application provides an electrode arrangement of 4 capacitors as described above. Under the condition that the capacitance size is the same, the area of the capacitance electrode can be further reduced compared with the mode that 2 capacitors are connected in parallel or 3 capacitors are connected in parallel, and therefore the aperture opening ratio of the pixel is further improved.

In some embodiments, second metal layer 107 and active layer 103 are connected by a first via 201. The connection between the second electrodes of the 4 capacitors is realized through the first via holes 201.

In some embodiments, the light shielding layer 101 and the first metal layer 105 are connected by the second via 202. A connection between the first electrode of the first capacitor and the first electrode of the second capacitor is realized.

In some embodiments, the first metal layer 105 and the first electrode layer 109 are connected by a third via 203. A connection between the first electrode of the third capacitance and the first electrode of the fourth capacitance is realized. The parallel connection of the 4 capacitances is achieved by the first via 201, the second via 202 and the third via 203.

In some embodiments, the second metal layer 107 and the first electrode layer 109 are used to receive external electrical signals, respectively. The energy storage capacitor with the 4 capacitors connected in parallel needs to be connected with a peripheral transistor to drive the electroluminescent device, so that the electrode of the energy storage capacitor is connected with the transistor or is externally connected with the electroluminescent device.

Referring to fig. 2, in some embodiments, the driving region D1 includes a thin film transistor, the thin film transistor includes a metal shielding layer 302, an active layer 301, a gate electrode 303, a source drain 304 and a second electrode layer 305 sequentially stacked,

the light shielding layer 101 and the metal shielding layer 302 of the thin film transistor are arranged on the same layer;

the active layer 103 and the active layer 301 of the thin film transistor are arranged on the same layer;

the first metal layer 105 and the grid electrode 303 of the thin film transistor are arranged on the same layer;

the second metal layer 107 and the source and drain electrodes 304 of the thin film transistor are arranged on the same layer;

the first electrode layer 109 is provided on the same layer as the second electrode layer 305 of the thin film transistor.

As shown in fig. 1, the arrangement of the plurality of capacitors should not affect the structure and process of the transistor as much as possible, and therefore, a structure in which the capacitors are arranged in layers with a part of the levels of the transistor is adopted. The light shielding layer 101 of the functional region and the metal shielding layer 302 of the thin film transistor may be connected or disconnected, which is not limited herein and may be set according to an application scenario. Similarly, the first electrode layer 109 of the functional region and the second electrode layer 305 of the thin film transistor may be connected or disconnected, which is not limited herein and may be set according to an application scenario.

The application also provides a display device which comprises the display panel provided by the embodiments of the application.

Referring to fig. 3, the present application further discloses a manufacturing method of a display panel, in which a sub-pixel region of the display panel includes a driving region 20 and a display region 10, the driving region 20 includes a functional region D2 and a transistor region D1, and the manufacturing method includes the following steps:

step S101: forming a light shielding layer and a metal shielding layer in the functional region and the transistor region respectively;

step S102: forming a buffer layer;

step S103: forming an active layer and an active layer in the functional region and the transistor region, respectively;

step S104: forming a gate insulating layer and patterning the gate insulating layer in the transistor region;

step S105: coating photoresist, forming a photoresist pattern on the active layer which does not need to be conducted, and conducting the active layer and part of the active layer which needs to be conducted;

step S106: removing the photoresist pattern, and respectively forming a first metal layer and a grid in the functional area and the transistor area;

step S107: forming a dielectric layer;

step S108: forming a second metal layer and a source drain electrode in the functional area and the transistor area respectively;

step S109: and forming a passivation layer and an electrode layer.

The steps will be described with reference to fig. 5 to 12 and fig. 2.

In step S101, as shown in fig. 5, the light-shielding layer 101 and the metal shield layer 302 are formed in the functional region D2 and the transistor D1, respectively. In this embodiment, the light-shielding layer 302 in the functional region is connected to the metal shielding layer 101 in the transistor region, and a disconnected structure may be adopted in the application. The light-shielding layer 302 in the functional region and the metal shielding layer 101 in the transistor region may be made of the same material or different materials, and are not limited herein.

In step S102, as shown in fig. 6, a buffer layer 102 is formed. The buffer layer 102 covers the entire driving region.

In step S103, as shown in fig. 7, the active layer 103 and the active layer 301 are formed in the functional region D2 and the transistor region D1, respectively, wherein the active layer 301 and the active layer 103 may be formed of IGZO (indium gallium zinc oxide) material, which has high electron mobility and is used as a channel material in a thin film transistor, so as to improve the resolution of the display panel. The active layer 103 and the active layer 301 are not made of a conductor at this time.

In step S104, as shown in fig. 8, the gate insulating layer 104 is formed and the gate insulating layer of the transistor region D1 is patterned such that the gate insulating layer is patterned in a region of the active layer 301 where electrical conduction is not required and the region of the active layer 301 where electrical conduction is required is exposed.

In step S105, as shown in fig. 9, a photoresist pattern is formed on the active layer 301-1, which does not require electrical conduction. Since the first metal layer 105 is required to be provided in the functional region D2, if the first metal layer is formed first, the active layer 104 cannot be conducted into a conductor, and the active layer 301-1 for conducting is not required in the active layer active portion, a photoresist is provided in the active layer 301-1 for conducting before conducting, and conducting is performed before forming the first metal layer. When the photoresist pattern is formed, a common etching method can be adopted, the photoresist pattern is only reserved on the active layer 301-1 which does not need to be conducted, or a Half Tone Mask (Half Tone Mask) process can be adopted for exposure, thicker photoresist is reserved on the active layer 301-1 which does not need to be conducted, and the photoresist in the rest area is thinner, so that the adverse effect of the conduction on other areas can be reduced. During the photoresist exposure process, a via 202 connecting the first metal layer 105 and the shielding layer 101 may also be formed. After that, the conductive active layer 103 and the active layer 301 partially requiring the conduction, the conductive active layer 301-2 and the non-conductive active layer 301-1 as shown in fig. 9, and the conductive active layer 103 are obtained. Indium gallium zinc oxide can be made conductive using gases such as H2, He, or NH 3.

In step S106, as shown in fig. 10, the photoresist pattern in step S105 is removed, and a first metal layer 105 and a gate electrode 303 are formed in the functional region and the transistor region, respectively. The first metal layer 105 and the gate electrode 303 are made of the same material, and a metal layer with excellent conductivity and light shielding property, such as a Mo, Cu, or Al film layer or a conformal metal layer, may be used. In manufacturing, PVD (Physical Vapor Deposition) may be used to deposit the gate and first metal layers and etch them to form the desired pattern.

In step S107, as shown in fig. 11, a dielectric layer 106 is formed. A via 201 connecting the second metal layer and the first metal layer may be formed at this time.

In step S108, as shown in fig. 12, a second metal layer 107 and source and drain electrodes 304 are formed in the functional region and the transistor region, respectively. The same metal material may be used for second metal layer 107 and source/drain 304. The second metal layer 107 and the source/drain 304 may be connected or disconnected with each other according to the requirements of the application scenario, which is not limited herein.

In step S109, as shown in fig. 2, the passivation layer 108 and the electrode layer 109 are formed. After the passivation layer 108 is formed, a via hole 203 connecting the electrode layer 109 and the first metal layer 105 may be formed. The electrode layer includes a first electrode layer of the functional region and a second electrode layer of the transistor region, and the first electrode layer and the second electrode layer may be connected to each other or disconnected from each other, which is not limited herein. The material of the electrode layer may be ITO (indium Tin oxides).

Through the above process, a hierarchical structure of a functional region having 5 layers of capacitor electrodes is obtained.

Referring to fig. 4, the present application further discloses a manufacturing method of a display panel, in which a sub-pixel region of the display panel includes a driving region and a display region, the driving region includes a functional region and a transistor region, and the manufacturing method includes the following steps:

step S102: forming a buffer layer;

step S105: forming a gate in the transistor region;

step S106: conductive active layer and active layer partially requiring conductivity

Step S107: forming a first metal layer in the functional region;

step S108: forming a dielectric layer;

step S109: forming a second metal layer and a source drain electrode in the functional area and the transistor area respectively;

step S110: and forming a passivation layer and an electrode layer.

The steps will be described with reference to fig. 5 to 8, 13 to 15, 10 to 12, and 2.

In step S101, as shown in fig. 5, the light-shielding layer 101 and the metal shielding layer 302 are formed in the functional region D2 and the transistor region D1, respectively. In this embodiment, the light-shielding layer 302 in the functional region is connected to the metal shielding layer 101 in the transistor region, and may be disconnected in application, which is not limited herein. The light-shielding layer 302 in the functional region and the metal shielding layer 101 in the transistor region may be made of the same material or different materials, and are not limited herein.

In step S103, as shown in fig. 7, the active layer 103 and the active layer 301 are formed in the functional region D2 and the transistor region D1, respectively, wherein the active layer 301 and the active layer 103 may be formed of IGZO (indium gallium zinc oxide) material, which has high electron mobility and is used as a channel material in a thin film transistor, so as to improve the resolution of the display panel. The active layer 301 and the active layer 103 are not made conductive at this time.

In step S104, as shown in fig. 8, the gate insulating layer 104 is formed and the gate insulating layer of the transistor region D1 is patterned such that the gate insulating layer is patterned in a region of the active layer 301 where electrical conduction is not required and the region of the active layer 301 where electrical conduction is required is exposed. .

In step S105, as shown in fig. 13, a gate electrode 302 is formed on the gate insulating layer 104 of the transistor region, and the gate electrode 302 of the transistor region D1 is patterned, so that a region of the active layer 301, which does not require to be subjected to the electrical conduction, forms a gate pattern and the region of the active layer 301, which requires to be subjected to the electrical conduction, is exposed.

In step S106, as shown in FIG. 14, the conductive active layer 103 and a part of the active layer 301-2 requiring to be conducted are obtained, the conductive active layer 301-2 and the non-conductive active layer 301-1 as shown in FIG. 14, and the conductive active layer 103 are obtained. Indium gallium zinc oxide can be made conductive using gases such as H2, He, or NH 3. After the conductor formation, a via hole 202 connecting the first metal layer 105 and the shielding layer 101 may be formed.

In step S107, as shown in fig. 15, the first metal layer 105 is formed in the functional region. The first metal layer 105 and the gate electrode 303 are made of the same material, and a metal layer with excellent conductivity and light shielding property, such as a Mo, Cu, or Al film layer or a conformal metal layer, may be used. In manufacturing, a first metal layer may be deposited by PVD (Physical Vapor Deposition) and etched to form a desired pattern.

In step S108, as shown in fig. 11, a dielectric layer 106 is formed. A via 201 connecting the second metal layer and the first metal layer may be formed at this time.

In step S109, as shown in fig. 12, a second metal layer 107 and source and drain electrodes 304 are formed in the functional region and the transistor region, respectively. The same metal material may be used for second metal layer 107 and source/drain 304. The second metal layer 107 and the source/drain 304 may be connected or disconnected with each other according to the requirements of the application scenario, which is not limited herein.

In step S110, as shown in fig. 2, a passivation layer 108 and an electrode layer 109 are formed, and after the passivation layer 108 is formed, a via hole 203 connecting the first electrode layer 109 and the first metal layer 105 may be formed. The electrode layer includes a first electrode layer 109 of the functional region and a second electrode layer 305 of the transistor region, and the first electrode layer and the second electrode layer may be connected to each other or disconnected, which is not limited herein. The material of the electrode layer may be ITO (indium Tin oxides).

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. The display panel is characterized in that a sub-pixel area of the display panel comprises a driving area and a display area, the driving area comprises a transistor area and a functional area, the functional area comprises a substrate, a light shielding layer, a buffer layer, an active layer, a grid electrode insulating layer, a first metal layer, a dielectric layer, a second metal layer, a passivation layer and a first electrode layer which are sequentially stacked, and orthographic projections of the light shielding layer, the active layer, the first metal layer, the second metal layer and the first electrode layer on the substrate respectively have a common overlapping area.

2. The display panel according to claim 1,

the light shielding layer, the active layer, the first metal layer, the second metal layer and the first electrode layer are respectively used as electrodes of an energy storage capacitor.

3. The display panel according to claim 1,

the energy storage capacitor comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;

the light shielding layer and the active layer are respectively used as a first electrode and a second electrode of the first capacitor;

4. The display panel of claim 1, wherein the second metal layer and the active layer are connected by a first via.

5. The display panel according to claim 1, wherein the light-shielding layer and the first metal layer are connected by a second via hole;

the first metal layer is connected with the first electrode layer through a third through hole.

6. The display panel according to claim 1, wherein the second metal layer and the first electrode layer are each used for external electrical connection.

7. The display panel according to claim 1, wherein the driving region comprises a thin film transistor comprising a metal shielding layer, an active layer, a gate electrode, a source drain electrode, and a second electrode layer sequentially stacked,

the light shielding layer and the metal shielding layer are arranged on the same layer;

the active layer and the active layer are arranged at the same layer;

the first metal layer and the grid electrode are arranged on the same layer;

8. A display device characterized by comprising the display panel according to any one of claims 1 to 7.

9. A manufacturing method of a display panel is characterized in that a sub-pixel area of the display panel comprises a driving area and a display area, the driving area comprises a function area and a transistor area, and the manufacturing method comprises the following steps:

forming a buffer layer;

coating photoresist, forming a photoresist pattern on the active layer which does not need to be conducted, conducting the active layer and the active layer which partially needs to be conducted;

forming a dielectric layer;

and forming a passivation layer and an electrode layer.

10. A manufacturing method of a display panel is characterized in that a sub-pixel area of the display panel comprises a driving area and a display area, the driving area comprises a function area and a transistor area, and the manufacturing method comprises the following steps:

forming a buffer layer;

forming a gate in the transistor region;

conductivating the active layer and a portion of the active layer requiring conductivation;

forming a first metal layer in the functional region;

forming a dielectric layer;

and forming a passivation layer and an electrode layer.