WO2021238549A1 - Display panel, display device, and method for manufacturing display panel - Google Patents

Abstract

Disclosed in the present disclosure are a display panel, a display device, and a method for manufacturing a display panel. A sub-pixel area of the display panel comprises a driving area and a display area, the driving area comprises a functional area, and the functional area comprises a shading layer, a buffer layer, a first active layer, a gate insulating layer, a first metal layer, a dielectric layer, a second metal layer, a passivation layer and a first electrode layer which are sequentially stacked, wherein orthographic projections of the shading layer, the first active layer, the first metal layer, the second metal layer and the first electrode layer on a substrate have a common overlapping area.

Description

Display panel, display device, and manufacturing method of display panel

Cross-references to related applications

This application claims the priority of Chinese Patent Application No. 202010448063.9 filed in China on May 25, 2020, the entire content of which is incorporated herein by reference.

Technical field

The present disclosure generally relates to the field of display technology, and particularly relates to a display panel, a display device, and a manufacturing method of the display panel.

Background technique

Organic light-emitting diode (OLED) display devices have good image quality, self-luminescence, no viewing angle obstacles, and large operating temperature range. OLED display devices have been considered to be the most valuable in the market after liquid crystal displays and plasma display devices. A new generation of flat panel display devices.

Summary of the invention

In a first aspect, a display panel is provided. The sub-pixel area of the display panel includes a driving area and a display area. The driving area includes a functional area. The functional area includes a substrate, a light-shielding layer, a buffer layer, and a first active Layer, gate insulating layer, first metal layer, dielectric layer, second metal layer, passivation layer and electrode layer, wherein the light shielding layer, the first active layer, the first metal layer, the second metal layer, the The orthographic projections of an electrode layer on the substrate respectively have a common overlapping area.

In some embodiments,

At least four of the light shielding layer, the first active layer, the first metal layer, the second metal layer, and the first electrode layer respectively serve as electrodes of the energy storage capacitor.

In some embodiments,

The light-shielding layer and the first active layer serve as the first electrode and the second electrode of the first capacitor, respectively;

The first metal layer and the first active layer serve as the first electrode and the second electrode of the second capacitor;

The first metal layer and the second metal layer respectively serve as the first electrode and the second electrode of the third capacitor;

The first electrode layer and the second metal layer respectively serve as the first electrode and the second electrode of the fourth capacitor.

In some embodiments, the energy storage capacitor includes a first capacitor and a second capacitor; the light shielding layer and the first active layer respectively serve as the first electrode and the second electrode of the first capacitor, and the first The metal layer and the second metal layer respectively serve as the first electrode and the second electrode of the second capacitor.

In some embodiments, the energy storage capacitor includes a first capacitor and a second capacitor; the first active layer and the first metal layer serve as the first electrode and the second electrode of the first capacitor, respectively. The second metal layer and the first electrode layer respectively serve as the first electrode and the second electrode of the second capacitor.

In some embodiments, the energy storage capacitor includes a first capacitor, a second capacitor, and a third capacitor; the light-shielding layer and the first active layer serve as the first electrode and the second electrode of the first capacitor, respectively, The first metal layer and the second metal layer respectively serve as the first electrode and the second electrode of the second capacitor, and the first electrode layer and the second metal layer respectively serve as the first electrode and the second electrode of the third capacitor. The second electrode.

In some embodiments, the energy storage capacitor includes a first capacitor, a second capacitor, and a third capacitor; the light-shielding layer and the first active layer serve as the first electrode and the second electrode of the first capacitor, respectively, The first metal layer and the first active layer respectively serve as the first electrode and the second electrode of the second capacitor, and the second metal layer and the first electrode layer respectively serve as the first electrode of the third capacitor And the second electrode.

In some embodiments, the second metal layer and the first active layer are connected through a first via hole.

In some embodiments, the light shielding layer and the first metal layer are connected through a second via hole; the first metal layer and the first electrode layer are connected through a third via hole.

In some embodiments, the second metal layer and the first electrode layer are respectively used for external electrical connection.

In some embodiments, the driving area further includes a transistor area, the transistor area includes a thin film transistor, and the thin film transistor includes a metal shielding layer, a second active layer, a gate electrode, a source drain and a second electrode layer stacked in sequence,

The light-shielding layer and the metal shielding layer are arranged on the same layer;

The first active layer and the second active layer are arranged in the same layer;

The first metal layer and the gate are arranged in the same layer;

The second metal layer is arranged in the same layer as the source and drain electrodes;

The first electrode layer and the second electrode layer are arranged in the same layer.

In a second aspect, a display device is provided, including the display panel included in each embodiment of the present disclosure.

In a third aspect, a method for manufacturing a display panel is provided. The sub-pixel area of the display panel includes a driving area and a display area, and the driving area includes a functional area and a transistor area. The manufacturing method includes the following steps:

Form a light-shielding layer and a metal shielding layer in the functional area and the transistor area respectively;

Form a buffer layer;

Forming a first active layer and a second active layer in the functional area and the transistor area respectively;

Forming a gate insulating layer, and patterning the gate insulating layer in the transistor area;

Coating photoresist, forming a photoresist pattern on the second active layer that does not need to be conductive, and conducts the conductiveization of the first active layer and part of the second active layer that needs to be conductive;

Remove the photoresist pattern, and form a first metal layer and a gate in the functional area and the transistor area respectively;

Forming a dielectric layer;

A second metal layer and source and drain are formed in the functional area and the transistor area respectively;

A passivation layer and an electrode layer are formed.

In some embodiments, the electrode layer includes a first electrode layer in a functional area and a second electrode layer in a transistor area, the display panel includes an energy storage capacitor, and the energy storage capacitor includes a first capacitor, a second electrode layer, and a second electrode layer. Capacitors, third capacitors, and fourth capacitors; the light-shielding layer and the first active layer serve as the first electrode and the second electrode of the first capacitor, respectively; the first metal layer and the first have The source layer serves as the first electrode and the second electrode of the second capacitor; the first metal layer and the second metal layer serve as the first electrode and the second electrode of the third capacitor, respectively; The electrode layer and the second metal layer respectively serve as the first electrode and the second electrode of the fourth capacitor;

After coating the photoresist, the method further includes:

Exposing the photoresist, and simultaneously forming a second via connecting the first metal layer and the shielding layer.

In some embodiments, the forming of the dielectric layer includes:

The dielectric layer and a first via hole penetrating the dielectric layer are formed to connect the second metal layer and the first metal layer.

In some embodiments, the forming the passivation layer includes:

A passivation layer and a third via hole are formed to connect the first electrode layer and the first metal layer through the third via hole.

In a fourth aspect, a manufacturing method of a display panel is provided. The sub-pixel area of the display panel includes a driving area and a display area, and the driving area includes a functional area and a transistor area. The manufacturing method includes the following steps:

Form a light-shielding layer and a metal shielding layer in the functional area and the transistor area respectively;

Form a buffer layer;

Forming a first active layer and a second active layer in the functional area and the transistor area respectively;

Forming a gate insulating layer, and patterning the gate insulating layer in the transistor area;

Forming a gate in the transistor area;

Conducting the first active layer and part of the second active layer that needs to be conductive;

Forming a first metal layer in the functional area;

Forming a dielectric layer;

A second metal layer and source and drain are formed in the functional area and the transistor area respectively;

A passivation layer and an electrode layer are formed.

In some embodiments, the electrode layer includes a first electrode layer in a functional area and a second electrode layer in a transistor area, the display panel includes an energy storage capacitor, and the energy storage capacitor includes a first capacitor, a second electrode layer, and a second electrode layer. Capacitors, third capacitors, and fourth capacitors; the light-shielding layer and the first active layer serve as the first electrode and the second electrode of the first capacitor, respectively; the first metal layer and the first have The source layer serves as the first electrode and the second electrode of the second capacitor; the first metal layer and the second metal layer serve as the first electrode and the second electrode of the third capacitor, respectively; The electrode layer and the second metal layer respectively serve as the first electrode and the second electrode of the fourth capacitor;

After conductorizing the first active layer and part of the second active layer that needs to be conductorized, the method further includes:

A second via connecting the first metal layer and the shielding layer is formed.

In some embodiments, the forming of the dielectric layer includes:

The dielectric layer and a first via hole penetrating the dielectric layer are formed to connect the second metal layer and the first metal layer.

In some embodiments, the forming the passivation layer includes:

A passivation layer and a third via hole are formed to connect the first electrode layer and the first metal layer through the third via hole.

According to the technical solution provided by the embodiments of the present disclosure, by arranging multiple capacitor electrodes in the driving area of the display panel, it is possible to solve the problem of arranging multiple capacitors to obtain an energy storage capacitor with a small area and a large capacitance value.

Description of the drawings

By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present disclosure will become more apparent:

Fig. 1 shows an exemplary structural block diagram of a display panel according to an embodiment of the present disclosure;

FIG. 2 shows an exemplary cross-sectional view of AA′ according to an embodiment of the present disclosure;

FIG. 3 shows an exemplary flowchart of a method of manufacturing a display panel according to an embodiment of the present disclosure;

FIG. 4 shows an exemplary flowchart of a manufacturing method of a display panel according to another embodiment of the present disclosure;

5 to 12 show specific exemplary schematic diagrams according to the manufacturing method of the display panel in FIG. 3;

13 to 15 show specific exemplary schematic diagrams according to the manufacturing method of the display panel in FIG. 4.

Detailed ways

The present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described here are only used to explain the related invention, but not to limit the invention. In addition, it should be noted that, for ease of description, only the parts related to the invention are shown in the drawings.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "include" and other similar words mean that the element or item appearing before the word encompasses the element or item listed after the word and its equivalents, but does not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate the relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other if there is no conflict. Hereinafter, the present disclosure will be described in detail with reference to the drawings and in conjunction with the embodiments.

In order to obtain an OLED device with good display performance, the design structure of the TFT circuit is also very important. In the design process of the TFT circuit, we hope to obtain a large enough capacitance to enhance the charging effect during driving. At the same time, for bottom-emitting OLED devices, we also hope to increase the aperture ratio, and the increase in the area of the capacitor electrode will reduce The opening rate, how to solve the above problems is an urgent problem to be solved.

In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a display panel, a display device, and a manufacturing method of the display panel that have a large capacitance and increase the aperture ratio.

1 and 2, the sub-pixel area of the display panel includes a driving area 20 and a display area 10. The driving area 20 includes a transistor area D1 and a functional area D2. The functional area D2 includes a substrate (not marked in the figure) stacked in sequence. Out), the light shielding layer 101, the buffer layer 102, the first active layer 103, the gate insulating layer 104, the first metal layer 105, the dielectric layer 106, the second metal layer 107, the passivation layer 108 and the first electrode layer 109, wherein the orthographic projections of the light shielding layer 101, the first active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109 respectively on the substrate have a common overlapping area.

The common overlapping area here refers to the common overlapping area of the light-shielding layer 101, the first active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109, and is not some of them. One or three. Setting the functional area of the above-mentioned multilayer structure in the non-transistor area of the driving area provides the possibility to arrange more components in a limited area.

In some embodiments, at least four of the light shielding layer 101, the first active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109 can be used as electrodes of the energy storage capacitor, respectively.

The driving circuit of the sub-pixel includes an energy storage capacitor, and the size of the energy storage capacitor will directly affect the driving effect of the electroluminescent device. The larger the capacitance of the energy storage capacitor, the stronger the driving ability. The larger the area of the two oppositely arranged electrodes in the energy storage capacitor, the greater the capacitance value, and the increase in the area of the capacitor electrode will increase the proportion of the driving area in the entire sub-pixel area, thereby reducing the proportion of the display area 10. , Which reduces the aperture ratio of the sub-pixels. In the present disclosure, multiple capacitors are connected in parallel to reduce the area of capacitor electrodes. Therefore, how to set the level of the electrodes in the functional area will be the key to solving the above-mentioned problems.

In the present disclosure, multiple levels that can be used as capacitor electrodes are provided in the functional area, including the light shielding layer 101, the first active layer 103, the first metal layer 105, the second metal layer 107, and the first electrode layer 109. Among them, the capacitor electrode can be set according to the needs of the application scenario, which is not limited here. At the other levels, the buffer layer 102, the gate insulating layer 104, the dielectric layer 106, and the passivation layer 108 can be used as an insulating layer between capacitor electrodes, and can form a film capacitor or a parasitic capacitor with the electrodes on both sides thereof.

For example, two capacitors can be provided in the functional area of the present disclosure: the light shielding layer 101 and the first active layer 103 are respectively set as the first electrode and the second electrode of the first capacitor, the first metal layer 105 and the second metal layer 107 Respectively serve as the first electrode and the second electrode of the second capacitor; or, the first active layer 103 and the first metal layer 105 are respectively set as the first electrode and the second electrode of the first capacitor, and the second metal layer 107, the first electrode An electrode layer 109 serves as the first electrode and the second electrode of the second capacitor, respectively. In addition, there can be other setting methods for setting two capacitors, which will not be repeated here. Connect the first electrode of the first capacitor and the first electrode of the second capacitor through the via hole, and connect the second electrode of the first capacitor and the second electrode of the second capacitor to connect the capacitors in parallel.

For another example, three capacitors can be provided in the functional area: the light-shielding layer 101 and the first active layer 103 serve as the first electrode and the second electrode of the first capacitor, respectively, and the first metal layer 105 and the second metal layer 107 serve as the first electrode respectively. The first electrode and the second electrode of the two capacitors, the first electrode layer 109 and the second metal layer 107 respectively serve as the first electrode and the second electrode of the third capacitor. Wherein, the second electrode of the second capacitor and the second electrode of the third capacitor are common electrodes. Connect the first electrode of the first capacitor, the first electrode of the second capacitor, and the first electrode of the third capacitor through the via hole, and connect the second electrode of the first capacitor and the second electrode of the second capacitor to connect the capacitors in parallel. . Alternatively, the light shielding layer 101 and the first active layer 103 serve as the first electrode and the second electrode of the first capacitor, respectively, and the first metal layer 105 and the first active layer 103 serve as the first electrode and the second electrode of the second capacitor, respectively. The electrodes, the second metal layer 107 and the first electrode layer 109 respectively serve as the first electrode and the second electrode of the third capacitor. Wherein, the second electrode of the first capacitor and the second electrode of the second capacitor are common electrodes. Connect the first electrode of the first capacitor, the first electrode of the second capacitor, and the first electrode of the third capacitor through the via hole, and connect the second electrode of the first capacitor and the second electrode of the third capacitor to connect the capacitors in parallel. . In addition, there can also be other ways of setting three capacitors in parallel, which will not be repeated here.

It should be noted that the display area 10 is used for arranging electroluminescent devices; the driving area 20 is used for arranging pixel driving circuits, and the pixel driving circuit is used for driving the electroluminescent devices of the display area 10. The pixel driving circuit includes an energy storage capacitor and a plurality of thin film transistors, and specifically may include 6T1C (6 thin film transistors plus 1 energy storage capacitor), 7T1C (7 thin film transistors plus 1 energy storage capacitor) and other structures. Therefore, the driving area 20 can be divided into a transistor area D1 for arranging thin film transistors and a functional area D2 for arranging energy storage capacitors, as shown in FIG. 2. In addition, other transistors in the transistor area are shown in FIG. 1, such as transistor 31, transistor 32, and transistor 33. For the convenience of presentation, FIG. 2 only shows one transistor. In fact, the transistor area may include multiple transistors.

In some embodiments, the energy storage capacitor includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor,

The light shielding layer 101 and the first active layer 103 serve as the first electrode and the second electrode of the first capacitor, respectively;

The first metal layer 105 and the first active layer 103 serve as the first electrode and the second electrode of the second capacitor;

The first metal layer 105 and the second metal layer 107 serve as the first electrode and the second electrode of the third capacitor, respectively;

The first electrode layer 109 and the second metal layer 107 serve as the first electrode and the second electrode of the fourth capacitor, respectively.

In the above arrangement of capacitor electrodes, the second electrode of the first capacitor and the second electrode of the second capacitor are common electrodes, the first electrode of the second capacitor and the first electrode of the third capacitor are common electrodes, and the second electrode of the third capacitor is a common electrode. The two electrodes and the second electrode of the fourth capacitor are shared capacitors. By arranging multiple common electrodes, 5 electrodes are used to set 4 capacitors in the functional area. As above, this disclosure provides four capacitor electrode settings. In the case of the same size of the capacitors, the parallel connection of the two capacitors or the parallel connection of the three capacitors can further reduce the area of the capacitor electrode, thereby further increasing the aperture ratio of the pixel.

In some embodiments, the second metal layer 107 and the first active layer 103 are connected through the first via 201. Through the first via 201, the connection between the second electrodes of the four capacitors is realized.

In some embodiments, the light shielding layer 101 and the first metal layer 105 are connected through the second via 202. The connection between the first electrode of the first capacitor and the first electrode of the second capacitor is realized.

In some embodiments, the first metal layer 105 and the first electrode layer 109 are connected by a third via 203. The connection between the first electrode of the third capacitor and the first electrode of the fourth capacitor is realized. The parallel connection of four capacitors is realized through the first via 201, the second via 202, and the third via 203.

In some embodiments, the second metal layer 107 and the first electrode layer 109 are used to receive external electrical signals, respectively. The energy storage capacitor with the above four capacitors in parallel needs to be connected to the surrounding transistors to drive the electroluminescent device. Therefore, the electrode of the energy storage capacitor is connected to the transistor or externally connected to the electroluminescent device.

Referring to FIG. 2, in some embodiments, the driving area D1 includes a thin film transistor. The thin film transistor includes a metal shielding layer 302, a second active layer 301, a gate 303, a source drain 304, and a second electrode layer stacked in sequence. 305,

The light shielding layer 101 and the metal shielding layer 302 of the thin film transistor are arranged in the same layer;

The first active layer 103 and the second active layer 301 of the thin film transistor are arranged in the same layer;

The first metal layer 105 is provided in the same layer as the gate 303 of the thin film transistor;

The second metal layer 107 is provided in the same layer as the source and drain 304 of the thin film transistor;

The first electrode layer 109 and the second electrode layer 305 of the thin film transistor are arranged in the same layer.

As shown in Fig. 1, the arrangement of multiple capacitors should not affect the structure and process of the transistor as much as possible, so a structure that is arranged at the same level as part of the transistor is adopted. Wherein, the light shielding layer 101 of the functional area and the metal shielding layer 302 of the thin film transistor can be connected or disconnected, which is not limited here, and can be set according to application scenarios. In the same way, the first electrode layer 109 of the functional area and the second electrode layer 305 of the thin film transistor can be connected or disconnected, which is not limited here, and can be set according to application scenarios.

The present disclosure also provides a display device, which includes the display panel provided by each embodiment of the present disclosure.

3, the present disclosure also discloses a manufacturing method of a display panel. The sub-pixel area of the display panel includes a driving area 20 and a display area 10. The driving area 20 includes a functional area D2 and a transistor area D1. The manufacturing method includes the following steps:

Step S101: forming a light shielding layer and a metal shielding layer in the functional area and the transistor area respectively;

Step S102: forming a buffer layer;

Step S103: forming a first active layer and a second active layer in the functional area and the transistor area, respectively;

Step S104: forming a gate insulating layer, and patterning the gate insulating layer in the transistor region;

Step S105: applying photoresist, forming a photoresist pattern on the second active layer that does not need to be conductive, and conducting the first active layer and a part of the second active layer that needs to be conductive;

Step S106: Remove the photoresist pattern, and form a first metal layer and a gate in the functional area and the transistor area, respectively;

Step S107: forming a dielectric layer;

Step S108: forming a second metal layer and a source and drain respectively in the functional area and the transistor area;

Step S109: forming a passivation layer and an electrode layer.

Hereinafter, each step will be described with reference to FIG. 5 to FIG. 12 and FIG. 2.

In step S101, as shown in FIG. 5, a light shielding layer 101 and a metal shielding layer 302 are formed in the functional area D2 and the transistor D1 area, respectively. In this embodiment, the light shielding layer 302 of the functional area is connected to the metal shielding layer 101 of the transistor area, and a disconnected structure can also be adopted in the application. In addition, the light shielding layer 302 of the functional area and the metal shielding layer 101 of the transistor area can be made of the same material or different, which is not limited here. In some embodiments, the light shielding layer 302 in the functional area and the metal shielding layer 101 in the transistor area can be formed at the same time by using the same mask and in the same patterning process.

In step S102, as shown in FIG. 6, a buffer layer 102 is formed. The buffer layer 102 covers the entire driving area.

In step S103, as shown in FIG. 7, a first active layer 103 and a second active layer 301 are formed in the functional area D2 and the transistor area D1, respectively, wherein the second active layer 301 and the first active layer 103 can be Using IGZO (indium gallium zinc oxide, indium gallium zinc oxide) material, IGZO has a higher electron mobility and is used as a channel material in thin film transistors to improve the resolution of the display panel. At this time, the first active layer 103 and the second active layer 301 are not conductive.

In step S104, as shown in FIG. 8, a gate insulating layer 104 is formed, and the gate insulating layer of the transistor region D1 is patterned, so that the gate insulating layer is formed in the region of the second active layer 301 that does not need to be conductive. , And expose the area of the second active layer 301 that needs to be conductive.

In step S105, as shown in FIG. 9, a photoresist pattern 401 is formed on the second active layer 301-1 that does not need to be conductive.

Here, the photoresist pattern 401 is formed on the second active layer 301-1 that does not need to be conductive, so as to shield the second active layer 301-1, thereby avoiding the second active layer 301-1. Conductive. Further, the second active layer 301-2 and the first active layer 103 that are not covered by the photoresist pattern 401 are conductive.

When forming the photoresist pattern, an ordinary etching method can be used, and only the photoresist pattern is left in the second active layer 301-1 that does not need to be conductive, or a half tone mask (Half Tone Mask) process can also be used for exposure In the second active layer 301-1 that does not need to be conductive, a thicker photoresist is reserved, while the photoresist in the remaining regions is thinner, which can reduce the adverse effects of conductiveization on other regions. During the process of photoresist exposure, a second via 202 connecting the first metal layer 105 and the shielding layer 101 may also be formed. After that, the first active layer 103 and a part of the second active layer 301 that need to be conductive are made to be conductive, to obtain a conductive second active layer 301-2 and an unconductive second active layer as shown in FIG. 9. Layer 301-1, and a conductive first active layer 103. _{H 2} , He or NH ₃ can be used to conduct conduction of indium gallium zinc oxide.

In step S106, as shown in FIG. 10, the photoresist pattern in step S105 is removed, and a first metal layer 105 and a gate 303 are formed in the functional area and the transistor area, respectively. The first metal layer 105 and the gate electrode 303 are made of the same material, and a metal layer with excellent conductivity and good light-shielding property may be used, such as a Mo, Cu, Al film layer or a conforming metal layer. During manufacturing, PVD (Physical Vapor Deposition, physical vapor deposition) can be used to deposit the gate and the first metal layer, and etch to form the desired pattern. In this step, the first metal layer 105 and the gate electrode 303 are formed at the same time using the same mask plate and in the same patterning process. Compared with the method shown in FIG. 4, the first metal layer 105 and the gate 303 can save the manufacturing process, thereby saving the manufacturing cost.

In step S107, as shown in FIG. 11, a dielectric layer 106 is formed. At this time, a first via 201 connecting the second metal layer and the first metal layer may be formed. It can be seen from FIG. 11 that the first via 201 penetrates the dielectric layer 106.

In step S108, as shown in FIG. 12, a second metal layer 107 and a source and drain 304 are formed in the functional area and the transistor area, respectively. The second metal layer 107 and the source and drain electrodes 304 can use the same metal material. According to the needs of the application scenario, the second metal layer 107 and the source and drain electrodes 304 can be connected or disconnected, which is not limited here. In some embodiments, the second metal layer 107 and the source and drain electrodes 304 can be formed at the same time by using the same mask and in the same patterning process.

In step S109, as shown in FIG. 2, a passivation layer 108 and an electrode layer 109 are formed. After the passivation layer 108 is formed, a third via 203 connecting the electrode layer 109 and the first metal layer 105 may be formed. The electrode layer includes a first electrode layer in the functional area and a second electrode layer in the transistor area. The first electrode layer and the second electrode layer can be connected to each other or disconnected, which is not limited here. The material of the electrode layer may be ITO (indium tin oxide, indium tin oxide).

After the above process, a hierarchical structure with 5 layers of functional regions of capacitor electrodes is obtained.

4, the present disclosure also discloses a manufacturing method of a display panel. The sub-pixel area of the display panel includes a driving area and a display area, and the driving area includes a functional area and a transistor area. The manufacturing method includes the following steps:

Step S201: forming a light shielding layer and a metal shielding layer in the functional area and the transistor area respectively;

Step S202: forming a buffer layer;

Step S203: forming a first active layer and a second active layer in the functional area and the transistor area, respectively;

Step S204: forming a gate insulating layer, and patterning the gate insulating layer in the transistor area;

Step S205: forming a gate in the transistor area;

Step S206: Conducting the first active layer and part of the second active layer that needs to be conductive

Step S207: forming a first metal layer in the functional area;

Step S208: forming a dielectric layer;

Step S209: forming a second metal layer and a source and drain respectively in the functional area and the transistor area;

Step S210: forming a passivation layer and an electrode layer.

Hereinafter, each step will be described with reference to FIG. 5 to FIG. 8, FIG. 13 to FIG. 15, FIG. 11 to FIG. 12, and FIG. 2.

In step S201, as shown in FIG. 5, a light shielding layer 101 and a metal shielding layer 302 are formed in the functional area D2 and the transistor area D1, respectively. In this embodiment, the light shielding layer 302 of the functional area is connected to the metal shielding layer 101 of the transistor area, and it can also be disconnected in application, which is not limited here. In addition, the light shielding layer 302 of the functional area and the metal shielding layer 101 of the transistor area can be made of the same material or different, which is not limited here. In some embodiments, the light shielding layer 302 in the functional area and the metal shielding layer 101 in the transistor area can be formed at the same time by using the same mask and in the same patterning process.

In step S202, as shown in FIG. 6, a buffer layer 102 is formed. The buffer layer 102 covers the entire driving area.

In step S203, as shown in FIG. 7, a first active layer 103 and a second active layer 301 are formed in the functional area D2 and the transistor area D1, respectively, wherein the second active layer 301 and the first active layer 103 can be Using IGZO (indium gallium zinc oxide, indium gallium zinc oxide) material, IGZO has a higher electron mobility and is used as a channel material in thin film transistors to improve the resolution of the display panel. At this time, the second active layer 301 and the first active layer 103 are not conductive.

In step S204, as shown in FIG. 8, the gate insulating layer 104 is formed, and the gate insulating layer of the transistor region D1 is patterned, so that the gate insulating layer is formed in the region of the second active layer 301 that does not need to be conductive. , And expose the area of the second active layer 301 that needs to be conductive.

In step S205, as shown in FIG. 13, a gate 303 is formed on the gate insulating layer 104 of the transistor area, and the gate 303 of the transistor area D1 is patterned so that the second active layer 301 does not need to be conductive. The gate pattern is formed in the region, and the region of the second active layer 301 that needs to be conductive is exposed.

In this step, the gate 303 covers the area that does not need to be conductive, so as to prevent the active layer that does not need to be conductive from being conductive.

In step S206, as shown in FIG. 14, the conductive first active layer 103 and a part of the second active layer 301-2 that need to be conductive are obtained to obtain the conductive second active layer 301- as shown in FIG. 2 and the unconducted second active layer 301-1, and the conductorized first active layer 103. _{H 2} , He or NH ₃ can be used to conduct conduction of indium gallium zinc oxide. After the conductorization, a second via 202 connecting the first metal layer 105 and the shielding layer 101 can be formed.

In step S207, as shown in FIG. 15, a first metal layer 105 is formed in the functional area. The first metal layer 105 and the gate electrode 303 are made of the same material, and a metal layer with excellent conductivity and good light-shielding property may be used, such as a Mo, Cu, Al film layer or a conforming metal layer. During manufacturing, PVD (Physical Vapor Deposition, physical vapor deposition) can be used to deposit the first metal layer and etch to form the desired pattern.

It can be seen from FIG. 15 that the first metal layer 105 and the gate 303 are provided in the same layer. The difference between the method shown in Fig. 4 and the method shown in Fig. 3 is that the steps shown in Figs. 13-15 are: forming a gate 303—conducting—forming a first metal layer 105, while Figs. 9-10 The steps shown are: coating photoresist+conducting-forming the gate 303 and the first metal layer 105 at the same time.

In the method shown in FIG. 4, the first metal layer 105 is formed after the conductorization is because, if the first metal layer 105 and the gate 303 are formed at the same time, the first metal layer 105 will make the first 103 of the active layer cannot be made into a conductor. Therefore, in the method shown in FIG. 4, the first metal layer 105 and the gate 303 are provided in the same layer, but are formed in different processes.

In step S208, as shown in FIG. 11, a dielectric layer 106 is formed. At this time, a first via 201 connecting the second metal layer and the first metal layer may be formed. It can be seen from FIG. 11 that the first via 201 penetrates the dielectric layer 106.

In step S209, as shown in FIG. 12, a second metal layer 107 and a source and drain 304 are formed in the functional area and the transistor area, respectively. The second metal layer 107 and the source and drain electrodes 304 can use the same metal material. According to the needs of the application scenario, the second metal layer 107 and the source and drain electrodes 304 can be connected or disconnected, which is not limited here. In some embodiments, the second metal layer 107 and the source and drain electrodes 304 can be formed at the same time by using the same mask and in the same patterning process.

In step S210, as shown in FIG. 2, a passivation layer 108 and an electrode layer 109 are formed. After the passivation layer 108 is formed, a third via 203 connecting the first electrode layer 109 and the first metal layer 105 may be formed. The electrode layer includes the first electrode layer 109 in the functional area and the second electrode layer 305 in the transistor area. The first electrode layer and the second electrode layer can be connected to each other or disconnected, which is not limited here. The material of the electrode layer may be ITO (indium tin oxide, indium tin oxide).

After the above process, a hierarchical structure with 5 layers of functional regions of capacitor electrodes is obtained.

The above description is only a preferred embodiment of the present disclosure and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover the technical solutions based on the above technical features without departing from the inventive concept. Or other technical solutions formed by any combination of its equivalent features. For example, the above-mentioned features and the technical features disclosed in the present disclosure (but not limited to) having similar functions are replaced with each other to form a technical solution.

Claims (20)

1. A display panel. The sub-pixel area of the display panel includes a driving area and a display area. The driving area includes a functional area. The insulating layer, the first metal layer, the dielectric layer, the second metal layer, the passivation layer and the first electrode layer, wherein the light shielding layer, the first active layer, the first metal layer, the The orthographic projections of the second metal layer and the first electrode layer on the substrate respectively have a common overlapping area.
2. The display panel according to claim 1, wherein:

   At least four of the light shielding layer, the first active layer, the first metal layer, the second metal layer, and the first electrode layer respectively serve as electrodes of an energy storage capacitor.
3. The display panel according to claim 2, wherein:

   The energy storage capacitor includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

   The light shielding layer and the first active layer respectively serve as the first electrode and the second electrode of the first capacitor;

   The first metal layer and the first active layer serve as the first electrode and the second electrode of the second capacitor;

   The first metal layer and the second metal layer respectively serve as the first electrode and the second electrode of the third capacitor;

   The first electrode layer and the second metal layer serve as the first electrode and the second electrode of the fourth capacitor, respectively.
4. 3. The display panel of claim 2, wherein the energy storage capacitor includes a first capacitor and a second capacitor; the light shielding layer and the first active layer serve as the first electrode and the second capacitor of the first capacitor, respectively. Electrodes, the first metal layer and the second metal layer respectively serve as the first electrode and the second electrode of the second capacitor.
5. 3. The display panel of claim 2, wherein the energy storage capacitor includes a first capacitor and a second capacitor; the first active layer and the first metal layer serve as the first electrode and the second capacitor of the first capacitor, respectively. The second electrode, the second metal layer and the first electrode layer respectively serve as the first electrode and the second electrode of the second capacitor.
6. The display panel according to claim 2, wherein the energy storage capacitor includes a first capacitor, a second capacitor, and a third capacitor; the light shielding layer and the first active layer respectively serve as the first capacitor of the first capacitor. The first metal layer and the second metal layer are respectively used as the first electrode and the second electrode of the second capacitor, and the first electrode layer and the second metal layer are respectively used as the third electrode. The first electrode and the second electrode of the capacitor.
7. 3. The display panel of claim 2, wherein the energy storage capacitor comprises a first capacitor, a second capacitor, and a third capacitor; the light shielding layer and the first active layer respectively serve as the first capacitor of the first capacitor. Electrode and second electrode, the first metal layer and the first active layer respectively serve as the first electrode and the second electrode of the second capacitor, and the second metal layer and the first electrode layer respectively serve as the first electrode and the second electrode. The first electrode and the second electrode of the three capacitors.
8. 3. The display panel of claim 3, wherein the second metal layer and the first active layer are connected through a first via hole.
9. 8. The display panel of claim 8, wherein the light shielding layer and the first metal layer are connected through a second via;

   The first metal layer and the first electrode layer are connected through a third via hole.
10. 9. The display panel of claim 9, wherein the second metal layer and the first electrode layer are respectively used for external electrical connection.
11. The display panel according to claim 1, wherein the driving area further includes a transistor area, the transistor area includes a thin film transistor, and the thin film transistor includes a metal shielding layer, a second active layer, and a gate electrode that are stacked in sequence. , Source drain and second electrode layer,

    The light shielding layer and the metal shielding layer are provided in the same layer;

    The first active layer and the second active layer are arranged in the same layer;

    The first metal layer and the gate electrode are provided in the same layer;

    The second metal layer and the source and drain electrodes are provided in the same layer;

    The first electrode layer and the second electrode layer are arranged in the same layer.
12. A display device comprising the display panel according to any one of claims 1-11.
13. A method for manufacturing a display panel. The sub-pixel area of the display panel includes a driving area and a display area. The driving area includes a functional area and a transistor area. The manufacturing method includes the following steps:

    Form a light-shielding layer and a metal shielding layer in the functional area and the transistor area respectively;

    Form a buffer layer;

    Forming a first active layer and a second active layer in the functional area and the transistor area respectively;

    Forming a gate insulating layer, and patterning the gate insulating layer in the transistor area;

    Coating photoresist, forming a photoresist pattern on the second active layer that does not need to be conductive, and conducts the first active layer and part of the second active layer that needs to be conductive;

    Remove the photoresist pattern, and form a first metal layer and a gate in the functional area and the transistor area, respectively;

    Forming a dielectric layer;

    A second metal layer and source and drain are formed in the functional area and the transistor area respectively;

    A passivation layer and an electrode layer are formed.
14. The method according to claim 13, wherein the electrode layer includes a first electrode layer in a functional area and a second electrode layer in a transistor area, the display panel includes an energy storage capacitor, and the energy storage capacitor includes a first electrode layer. A capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the light-shielding layer and the first active layer serve as the first electrode and the second electrode of the first capacitor, respectively; the first metal layer and The first active layer serves as the first electrode and the second electrode of the second capacitor; the first metal layer and the second metal layer serve as the first electrode and the second electrode of the third capacitor, respectively ; The first electrode layer and the second metal layer respectively serve as the first electrode and the second electrode of the fourth capacitor;

    After coating the photoresist, the method further includes:

    Exposing the photoresist, and simultaneously forming a second via connecting the first metal layer and the shielding layer.
15. The method of claim 14, wherein said forming a dielectric layer comprises:

    The dielectric layer and a first via hole penetrating the dielectric layer are formed to connect the second metal layer and the first metal layer.
16. The method according to claim 15, wherein said forming a passivation layer comprises:

    A passivation layer and a third via hole are formed to connect the first electrode layer and the first metal layer through the third via hole.
17. A method for manufacturing a display panel. The sub-pixel area of the display panel includes a driving area and a display area. The driving area includes a functional area and a transistor area. The manufacturing method includes the following steps:

    Form a light-shielding layer and a metal shielding layer in the functional area and the transistor area respectively;

    Form a buffer layer;

    Forming a first active layer and a second active layer in the functional area and the transistor area respectively;

    Forming a gate insulating layer, and patterning the gate insulating layer in the transistor area;

    Forming a gate in the transistor area;

    Conductorizing the first active layer and part of the second active layer that needs to be conductorized;

    Forming a first metal layer in the functional area;

    Forming a dielectric layer;

    A second metal layer and source and drain are formed in the functional area and the transistor area respectively;

    A passivation layer and an electrode layer are formed.
18. 17. The method of claim 17, wherein the electrode layer includes a first electrode layer in a functional area and a second electrode layer in a transistor area, the display panel includes an energy storage capacitor, and the energy storage capacitor includes a first electrode layer. A capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the light-shielding layer and the first active layer serve as the first electrode and the second electrode of the first capacitor, respectively; the first metal layer and The first active layer serves as the first electrode and the second electrode of the second capacitor; the first metal layer and the second metal layer serve as the first electrode and the second electrode of the third capacitor, respectively ; The first electrode layer and the second metal layer respectively serve as the first electrode and the second electrode of the fourth capacitor;

    After conductorizing the first active layer and part of the second active layer that needs to be conductorized, the method further includes:

    A second via connecting the first metal layer and the shielding layer is formed.
19. The method of claim 18, wherein said forming a dielectric layer comprises:

    The dielectric layer and a first via hole penetrating the dielectric layer are formed to connect the second metal layer and the first metal layer.
20. The method according to claim 19, wherein said forming a passivation layer comprises:

    A passivation layer and a third via hole are formed to connect the first electrode layer and the first metal layer through the third via hole.

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