CN113193033B - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN113193033B
CN113193033B CN202110476546.4A CN202110476546A CN113193033B CN 113193033 B CN113193033 B CN 113193033B CN 202110476546 A CN202110476546 A CN 202110476546A CN 113193033 B CN113193033 B CN 113193033B
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electrode
active layer
layer
display panel
substrate
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CN113193033A (en
Inventor
范文志
万云海
李瑶
朱超
刘家昌
曹曙光
淮兆祥
施文峰
蔡伟民
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Hefei Visionox Technology Co Ltd
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Hefei Visionox Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

The embodiment of the application relates to the technical field of display, and discloses a display panel and a display device, wherein the display panel comprises: a substrate; the first thin film transistor comprises a first active layer, a first gate insulating layer and a first gate electrode which are sequentially stacked, and the first active layer is arranged on the substrate; the second thin film transistor comprises a second active layer, the second active layer is arranged on one side of the first gate insulating layer, which is away from the substrate, and the second active layer and the first gate electrode are arranged on the same layer; the storage capacitor comprises a first electrode, wherein the first electrode and the first active layer or the second active layer are arranged on the same layer, and the material of the first electrode is the same as that of the active layer arranged on the same layer. The display panel and the display device provided by the application have low preparation process difficulty and low preparation cost.

Description

Display panel and display device
Technical Field
The embodiment of the application relates to the technical field of display, in particular to a display panel and a display device.
Background
The conventional organic light emitting diode display (Organic Light Emitting Display, OLED) module has the advantages of high image quality, power saving, thin body, wide application range, etc., and is widely applied to various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers, etc., and becomes the mainstream of the display module. In the related art, a display device using Low Temperature Polysilicon (LTPS) and metal Oxide (Oxide) as materials of an active layer of a thin film transistor, respectively, has been attracting attention.
However, the inventors found that there are at least the following problems in the related art: the thin film transistor made of polysilicon material and the thin film transistor made of metal oxide material are combined together to form the display device, so that the preparation process is complex and the preparation cost is high.
Disclosure of Invention
The embodiment of the application aims to provide a display panel and a display device, which have low preparation process difficulty and low preparation cost.
To solve the above technical problems, an embodiment of the present application provides a display panel, including:
a substrate; the first thin film transistor comprises a first active layer, a first gate insulating layer and a first gate electrode which are sequentially stacked, and the first active layer is arranged on the substrate; the second thin film transistor comprises a second active layer, the second active layer is arranged on one side of the first gate insulating layer, which is away from the substrate, and the second active layer and the first gate electrode are arranged on the same layer; the storage capacitor comprises a first electrode, wherein the first electrode and the first active layer or the second active layer are arranged on the same layer, and the material of the first electrode is the same as that of the active layer arranged on the same layer.
In addition, the material of the second active layer is metal oxide, the material of the first grid electrode comprises metal oxide and first ions, and the metal oxide forming the first grid electrode is the same as the metal oxide forming the second active layer; wherein the first ions are used to dope within the metal oxide to convert the first gate to a conductor.
In addition, the storage capacitor further comprises a second electrode, and when the first electrode and the first active layer are arranged in the same layer, the first gate insulating layer covers the first electrode, and the second electrode and the second active layer are arranged in the same layer.
In addition, the material of the second active layer is metal oxide, the material of the second electrode comprises metal oxide and second ions, and the metal oxide forming the second electrode is the same as the metal oxide forming the second active layer; wherein the second ions are for doping within the metal oxide to convert the second electrode to a conductor.
In addition, the second thin film transistor further comprises a second gate insulating layer arranged on one side of the second active layer, which is away from the substrate, and a second gate electrode arranged on one side of the second gate insulating layer, which is away from the substrate; the storage capacitor further comprises a second electrode, and when the first electrode and the first active layer are arranged in the same layer, the first gate insulating layer covers the first electrode, and the second electrode and the second gate are arranged in the same layer; when the first electrode and the second active layer are arranged in the same layer, the second gate insulating layer covers the first electrode, and the second electrode and the second gate electrode are arranged in the same layer.
In addition, the second electrode and the second grid electrode are made of the same material and are made of metal.
In addition, the orthographic projection of the first active layer on the substrate is not overlapped with the orthographic projection of the second active layer on the substrate.
In addition, the orthographic projection of the first grid electrode on the substrate is positioned in the orthographic projection of the first active layer on the substrate.
In addition, the material of the first active layer is low-temperature polysilicon.
The embodiment of the application also provides a display device which comprises the display panel.
Compared with the related art, the embodiment of the application has at least the following advantages:
the second active layer and the first grid are arranged on the same layer, so that the number of process layers in the preparation process of the display panel can be reduced, and the complexity of the preparation process of the display panel is reduced; the first electrode and the first active layer or the second active layer of the storage capacitor are arranged in the same layer, and the material of the first electrode is the same as that of the active layer arranged in the same layer, that is, the first electrode and the active layer of the storage capacitor can be prepared through the same process (namely, one mask plate can be used for simultaneously preparing the first electrode and the active layer), so that the number of mask plates required for preparing the display panel is reduced, and the preparation cost of the display panel is reduced.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
Fig. 1 is a schematic structural view of a display panel according to a first embodiment of the present application;
fig. 2 is a schematic diagram of another structure of a display panel according to a first embodiment of the present application;
fig. 3 is a schematic structural view of a display panel according to a first embodiment of the present application;
fig. 4 is a schematic view of another structure of the display panel according to the first embodiment of the present application;
fig. 5 is a flow chart of the preparation of a part of the structure of the display panel according to the first embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the claimed technical solution of the present application can be realized without these technical details and various changes and modifications based on the following embodiments.
A first embodiment of the present application relates to a display panel, and a schematic structural diagram of the display panel in this embodiment is shown in fig. 1, including:
a substrate 1; a first thin film transistor 2, the first thin film transistor 2 including a first active layer 21, a first gate insulating layer 22, and a first gate electrode 23, which are sequentially stacked, the first active layer 21 being disposed on the substrate 1; the second thin film transistor 3, the second thin film transistor 3 includes a second active layer 31, the second active layer 31 is disposed on a side of the first gate insulating layer 22 facing away from the substrate 1, and the second active layer 31 and the first gate electrode 23 are disposed in the same layer; the storage capacitor 4, the storage capacitor 4 includes a first electrode 42, the first electrode 42 and the first active layer 21 or the second active layer 31 are disposed on the same layer, and the material of the first electrode 42 is the same as the material of the active layer disposed on the same layer.
Specifically, the substrate 1 in the present embodiment may include, for example, a glass material, a ceramic material, a metal material, or a flexible or bendable material. For example, when the substrate 1 is a flexible or bendable material, the substrate 1 may include a polymer such as Polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or Cellulose Acetate Propionate (CAP). For example, the substrate 1 may have a single-layer or multi-layer structure formed of the above-described materials. When the substrate 1 has a multilayer structure, the substrate 1 may include, for example, an inorganic material layer. In some embodiments, the substrate 1 may have a multi-layered structure in which organic material layers, inorganic material layers, and organic material layers are sequentially stacked.
In this embodiment, the front projection of the first active layer 21 on the substrate 1 does not overlap with the front projection of the second active layer 31 on the substrate 1. By the arrangement of such a structure, the first active layer 21 and the second active layer 31 are prevented from contacting each other to affect the transistor characteristics formed later, and the stability of the display panel 100 is improved.
Preferably, in the present embodiment, the material of the second active layer 31 is a metal oxide, the material of the first gate electrode 23 includes a metal oxide and a first ion, and the metal oxide forming the first gate electrode 23 is the same as the metal oxide forming the second active layer 31; wherein the first ions are used to dope within the metal oxide to convert the first gate 23 into a conductor. In this way, the second active layer 31 and the first gate electrode 23 can be prepared by the same process (i.e., one mask plate can be used to simultaneously prepare the second active layer 31 and the first gate electrode 23), so that the number of mask plates required for preparing the display panel is reduced, and the preparation cost of the display panel is reduced. Specifically, the metal oxide may include, for example, znO-based materials such as ZnO, in-ZnO, ga-In-ZnO, and the like. In some embodiments, the second active layer 31 may be an In-Ga-ZnO (IGZO) semiconductor including metals such as In and Ga In ZnO.
More specifically, since the conductivity of the metal oxide is poor, in order to improve the conductivity of the first gate electrode 23, a first ion implantation (the first ion may be boron ion, fluorine ion, or the like) is performed on the first gate electrode 23 to convert the first gate electrode 23 into a conductor. Specifically, the method of ion implantation is to accelerate impurity ions in vacuum at low temperature to obtain impurity ions with larger kinetic energy, namely, the impurity ions can directly enter the metal oxide and cause the surface composition, structure and performance of the metal oxide to change, so that the surface performance (conductivity increase) of the metal oxide is optimized.
Compared with the related art, the embodiment of the application has at least the following advantages: the second active layer 31 and the first grid electrode 23 are arranged in the same layer, so that the number of process layers in the preparation process of the display panel can be reduced, and the complexity of the preparation process of the display panel is reduced; by arranging the first electrode 42 of the storage capacitor 4 and the first active layer 21 or the second active layer 31 in the same layer, and the material of the first electrode 42 is the same as that of the active layer arranged in the same layer, that is, the first electrode 42 of the storage capacitor 4 and the active layer can be prepared by the same process (that is, one mask plate can be used to prepare the first electrode 42 and the active layer simultaneously), the number of masks required for preparing the display panel is reduced, and thus the preparation cost of the display panel is reduced.
With continued reference to fig. 1, the storage capacitor 4 further includes a second electrode 41, the first electrode 42 is disposed in the same layer as the first active layer 21, the first gate insulating layer 22 covers the first electrode 42, and the second electrode 41 is disposed in the same layer as the second active layer 31. By the arrangement of the structure, the first gate insulating layer 22 can be used as a capacitance insulating layer between the first electrode 42 and the second electrode 41, so that leakage current is reduced, stability of the display panel is improved, the number of process layers of the display panel can be reduced, and process complexity is reduced.
Note that, since the thickness of the first gate insulating layer 22 determines the pixel capacitance value of the storage capacitor, the thickness of the first gate insulating layer 22 may be set according to actual requirements, and the embodiment is not particularly limited.
It should be noted that the material of the second electrode 41 shown in fig. 1 includes a metal oxide and a second ion, and the metal oxide forming the second electrode 41 is the same as the metal oxide forming the second active layer 31; wherein the second ions are used to dope within the metal oxide to convert the second electrode 41 into a conductor. Specifically, the metal oxide may include, for example, znO-based materials such as ZnO, in-ZnO, ga-In-ZnO, and the like. In some embodiments, the second active layer 31 may be an In-Ga-ZnO (IGZO) semiconductor including metals such as In and Ga In ZnO. In this way, the second electrode 41 and the second active layer 31 can be prepared by the same process (i.e., one mask plate can be used to simultaneously prepare the second electrode 41 and the second active layer 31), so that the number of mask plates required for preparing the display panel is reduced, and the preparation cost of the display panel is reduced.
It should be noted that, since the conductivity of the metal oxide is poor, in order to improve the conductivity of the second electrode 41, ion implantation (such as boron ion implantation, fluorine ion implantation, etc.) is performed on the second electrode 41 to ensure that the performance of the storage capacitor 4 is not affected; in addition, the material of the first active layer 21 is usually low-temperature polysilicon, and when the first active layer 21 and the first electrode 42 are prepared by the same process, the first electrode 42 needs to be ion implanted to improve the conductivity.
Referring to fig. 2, the second thin film transistor 4 further includes a second gate insulating layer 32 disposed on a side of the second active layer 31 facing away from the substrate, and a second gate electrode 33 disposed on a side of the second gate insulating layer 32 facing away from the substrate 1; the storage capacitor 4 further includes a second electrode 41, the first electrode 42 is disposed in the same layer as the first active layer 21, the first gate insulating layer 22 covers the first electrode 42, and the second electrode 41 is disposed in the same layer as the second gate electrode 33. As can be seen from fig. 2, the second gate insulating layer 32 covers the first gate insulating layer 22, that is, the first gate insulating layer 22 and the second gate insulating layer 32 together form a capacitor insulating layer of the storage capacitor 4, which can reduce leakage current, improve stability of the display panel, reduce the number of process layers of the display panel, and reduce process complexity.
Referring to fig. 3, the second thin film transistor 4 further includes a second gate insulating layer 32 disposed on a side of the second active layer 31 facing away from the substrate, and a second gate electrode 33 disposed on a side of the second gate insulating layer 32 facing away from the substrate 1; the storage capacitor 4 further includes a second electrode 41, the first electrode 42 is disposed in the same layer as the second active layer 31, the second gate insulating layer 32 covers the first electrode 42, and the second electrode 41 is disposed in the same layer as the second gate electrode 33. By the arrangement of the structure, the second gate insulating layer 32 is used as a capacitance insulating layer of the storage capacitor 4, so that leakage current can be reduced, stability of the display panel can be improved, the number of process layers of the display panel can be reduced, and process complexity can be reduced.
Note that the first gate insulating layer 22 and the second gate insulating layer 32 may include an inorganic material including, for example, oxide or nitride. For example, the second gate insulating layer 32 may include, for example, silicon oxide (SiO 2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al 2O 3), titanium oxide (TiO 2), tantalum oxide (Ta 2O 5), hafnium oxide (HfO 2), or zinc oxide (ZnO 2). The materials of the first gate insulating layer 22 and the second gate insulating layer 32 may be the same or different.
Referring to fig. 2 to 3, the materials of the second electrode 41 and the second gate 33 may be the same in this embodiment. In this way, the second electrode 41 and the second gate electrode 33 can be manufactured by the same process (i.e., one mask plate can be used to simultaneously manufacture the second electrode 41 and the second gate electrode 33), so that the number of mask plates required for manufacturing the display panel is reduced, and the manufacturing cost of the display panel is reduced.
Specifically, the materials of the second electrode 41 and the second gate electrode 33 may include, for example, molybdenum (Mo), copper (Cu), and titanium (Ti), and may have a single-layer structure or a multi-layer structure. For example, the second electrode 41 and the second gate electrode 33 are of a composite structure made of titanium-aluminum-titanium, and the second electrode 41 and the second gate electrode 33 having such structures have strong conductivity and Fang Zuxiao, so that the storage capacitor 4 can discharge the stored charge more rapidly. For example, the second electrode 41 and the second gate electrode 33 have a single-layer structure made of molybdenum, so that the entire thickness of the display panel can be effectively reduced, and the bending performance of the display panel can be improved.
It should be noted that, since the first active layer 21 shown in fig. 2 is prepared by the same process as the first electrode 42 of the storage capacitor 4, and the second active layer 31 shown in fig. 3 is prepared by the same process as the first electrode 42 of the storage capacitor 4, in order to improve the conductivity of the first electrode 42, ion implantation (such as boron ion implantation and fluorine ion implantation) is performed on the first electrode 42 to ensure that the performance of the storage capacitor 4 is not affected.
It should be noted that, in this example, the orthographic projection of the first gate electrode 23 on the substrate 1 is located within the orthographic projection of the first active layer 21 on the substrate 1. Since the first active layer 21 also needs ion implantation to determine the type of the first thin film transistor 2 (NMOS transistor or PMOS transistor), by the arrangement of this structure, the first active layer 21 which is not blocked by the first gate 23 can be ion implanted while the first gate 23 is ion implanted, so that no additional process is required to separately ion implant the first active layer 21, and the process complexity is reduced.
Referring to fig. 1 to 3, the display panel further includes: an interlayer dielectric layer 5, wherein the interlayer dielectric layer 5 is arranged on one side of the second gate insulation layer 32, which is away from the substrate 1, and the interlayer dielectric layer 5 covers the second electrode 41 and the second gate electrode 33; the first wiring 6 is arranged on one side of the interlayer dielectric layer 5, which is away from the substrate 1, and is connected with the first active layer 21 through a contact hole defined in the interlayer dielectric layer 5; the planarization layer 7 is arranged on one side, away from the substrate 1, of the interlayer dielectric layer 5, and the planarization layer 7 covers the first wiring 6; a connection electrode 8 (anode), the connection electrode 8 being disposed on a side of the planarization layer 7 facing away from the substrate 1 and being connected to the first trace 6 through a contact hole defined in the planarization layer 7.
Specifically, the material of the first active layer 21 may be low-temperature polysilicon. The first active layer 21 includes a first source region and a first drain region, which may be doped with impurities, and may have conductivity. The first source region and the first drain region may be connected to the first trace 6 through contact holes in the interlayer dielectric layer, respectively.
Specifically, the interlayer dielectric layer 5 is a stacked structure of a silicon oxide layer and a silicon nitride layer, the thickness of the silicon nitride layer is typically 40 to 60 nm, preferably 50 nm, and the thickness of the silicon oxide layer is typically 240 to 250 nm, preferably 250 nm.
Specifically, the planarization layer 7 may include an organic material, for example, acryl, BCB, PI, or HMDSO. In an embodiment, the planarization layer 7 may also comprise an inorganic material. The planarization layer 7 may serve as a protective layer covering the first wirings 6, and may have a smooth upper surface. In some embodiments, the planarization layer 7 may have a single-layer structure or a multi-layer structure.
Referring to fig. 4, the display panel further includes: an interlayer dielectric layer 5, wherein the interlayer dielectric layer 5 is arranged on one side of the second gate insulating layer 33, which is away from the substrate 1, and the interlayer dielectric layer 5 covers the second electrode 41 and the second gate electrode 33; a first trace 61, the first trace 61 being disposed on a side of the interlayer dielectric layer 5 facing away from the substrate 1 and connected to the first active layer 21 through a contact hole defined in the interlayer dielectric layer 5; a first planarization layer 71, wherein the first planarization layer 71 is disposed on a side of the interlayer dielectric layer 5 facing away from the substrate 1, and the first planarization layer 71 covers the first electrode 42; a second wiring 62, the second wiring 62 being disposed on a side of the first planarization layer 71 facing away from the substrate 1 and connected to the first wiring 61 through a contact hole defined in the first planarization layer 71; a second planarization layer 72, where the second planarization layer 72 is disposed on a side of the first planarization layer 71 facing away from the substrate 1, and the second planarization layer 72 covers the second trace 62; and a connection electrode 8, the connection electrode 8 being disposed on a side of the second planarization layer 72 facing away from the substrate 1 and being connected to the second trace 62 through a contact hole defined in the second planarization layer 72. By the arrangement of the structure, the sheet resistance in the surface of the display panel can be reduced, so that the voltage drop is reduced, and the display effect of the display panel is improved.
For easy understanding, the following specifically describes the preparation process of the film layer of the display panel portion in this embodiment with reference to fig. 5 by taking the film layer structure shown in fig. 1 as an example:
(1) As shown in fig. 5 (a), the first active layer 21 and the first electrode 42 are formed on the substrate 1. Specifically, the materials of the first active layer 21 and the first electrode 42 are the same, and PSI (polysilicon), in order to improve the conductivity of the first electrode 42 and ensure that the semiconductor property of the first active layer 21 is not affected, after the first active layer 21 and the first electrode 42 are formed, a mask plate is used to cover the first active layer 21 and expose the first electrode 42, and then ion implantation (such as boron ions and fluorine ions) is performed on the first electrode 42.
(2) As shown in fig. 5 (B), a first gate insulating layer 22 is formed on the substrate 1, the first gate insulating layer covering the first active layer 21 and the first electrode 42.
(3) As shown in fig. 5 (C), the first gate electrode 23, the second active layer 31, and the second electrode 41 are formed on the first gate insulating layer 22. The first gate electrode 23, the second active layer 31 and the second electrode 41 are all made of the same material and are all made of metal oxide (e.g. IGZO). In order to improve the conductivity of the second electrode 41 and the first gate electrode 23 and ensure that the semiconductor property of the second active layer 31 is not affected, after the first gate electrode 23, the second active layer 31 and the second electrode 41 are formed, a mask plate is used to cover the second active layer 31 and expose the first gate electrode 23 and the second electrode 41, and then ion implantation (such as boron ions, fluorine ions and the like) is performed on the first gate electrode 23 and the second electrode 41.
(4) As shown in fig. 5 (D), a second gate insulating layer 32 is formed on the first gate insulating layer 22, and the second gate insulating layer 32 covers the first gate electrode 23, the second active layer 31, and the second electrode 41.
(5) As shown in fig. 5 (E), a second gate electrode 33 is formed on a region of the second gate insulating layer 32 facing the second active layer 31, and the second gate electrode 33 is made of metal, and the second gate electrode 33 may have a single-layer structure or a composite structure.
A second embodiment of the present application relates to a display device including the display panel mentioned in the above embodiment.
The display panel can be a flexible organic light-emitting display module or a non-flexible organic light-emitting display module. The light emitting mode of the organic light emitting display module can be top light emitting, bottom light emitting or double-sided light emitting. The display module can also be packaged in a display device, and the display device can be applied to intelligent wearable equipment (such as an intelligent bracelet and an intelligent watch) and also can be applied to equipment such as an intelligent mobile phone, a tablet personal computer and a display.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the application and that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims (10)

1. A display panel, comprising:
a substrate;
the first thin film transistor comprises a first active layer, a first gate insulating layer and a first gate electrode which are sequentially stacked, and the first active layer is arranged on the substrate;
the second thin film transistor comprises a second active layer, the second active layer is arranged on one side of the first gate insulating layer, which is away from the substrate, and the second active layer and the first gate electrode are arranged on the same layer;
the storage capacitor comprises a first electrode, wherein the first electrode and the first active layer are arranged on the same layer, and the material of the first electrode is the same as that of the first active layer.
2. The display panel according to claim 1, wherein a material of the second active layer is a metal oxide, a material of the first gate electrode includes a metal oxide and a first ion, and the metal oxide forming the first gate electrode is the same as the metal oxide forming the second active layer;
wherein the first ions are used to dope within the metal oxide to convert the first gate to a conductor.
3. The display panel according to claim 1, wherein the storage capacitor further comprises a second electrode, the first gate insulating layer covers the first electrode, and the second electrode is disposed in the same layer as the second active layer.
4. The display panel according to claim 3, wherein a material of the second active layer is a metal oxide, a material of the second electrode includes a metal oxide and a second ion, and the metal oxide forming the second electrode is the same as the metal oxide forming the second active layer;
wherein the second ions are for doping within the metal oxide to convert the second electrode to a conductor.
5. The display panel according to claim 1, wherein the second thin film transistor further comprises a second gate insulating layer disposed on a side of the second active layer facing away from the substrate, and a second gate electrode disposed on a side of the second gate insulating layer facing away from the substrate;
the storage capacitor further comprises a second electrode, the first electrode is covered by the first gate insulating layer, and the second electrode and the second gate are arranged in the same layer.
6. The display panel according to claim 5, wherein the second electrode and the second gate electrode are made of the same material and are made of metal.
7. The display panel of claim 1, wherein an orthographic projection of the first active layer on the substrate does not coincide with an orthographic projection of the second active layer on the substrate.
8. The display panel of claim 1, wherein an orthographic projection of the first gate electrode on the substrate is within an orthographic projection of the first active layer on the substrate.
9. The display panel according to any one of claims 1 to 8, wherein the material of the first active layer is low-temperature polysilicon.
10. A display device, comprising: the display panel according to any one of claims 1 to 9.
CN202110476546.4A 2021-04-29 2021-04-29 Display panel and display device Active CN113193033B (en)

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Citations (2)

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Publication number Priority date Publication date Assignee Title
CN111785759A (en) * 2020-07-17 2020-10-16 武汉华星光电半导体显示技术有限公司 Display panel and display device
CN215771156U (en) * 2021-04-20 2022-02-08 合肥维信诺科技有限公司 Display panel and display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111785759A (en) * 2020-07-17 2020-10-16 武汉华星光电半导体显示技术有限公司 Display panel and display device
CN215771156U (en) * 2021-04-20 2022-02-08 合肥维信诺科技有限公司 Display panel and display device

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