CN111584459A - 采用使用延长通孔的金属线局部互连的中段制程mol制造的集成电路ic及相关方法 - Google Patents
采用使用延长通孔的金属线局部互连的中段制程mol制造的集成电路ic及相关方法 Download PDFInfo
- Publication number
- CN111584459A CN111584459A CN202010476256.5A CN202010476256A CN111584459A CN 111584459 A CN111584459 A CN 111584459A CN 202010476256 A CN202010476256 A CN 202010476256A CN 111584459 A CN111584459 A CN 111584459A
- Authority
- CN
- China
- Prior art keywords
- layer
- mol
- metal
- providing
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本公开涉及采用使用延长通孔的金属线局部互连的中段制程(MOL)制造的集成电路(IC)及相关方法。公开了采用使用延长通孔的金属线局部互连的中段制程(MOL)制造的集成电路(IC)。还公开了相关的方法。具体而言,金属层中的不同金属线可能需要在IC的MOL工艺期间被电互连。为了允许金属线被电互连而无需在金属线上方提供可能难以在例如印刷工艺中提供的此类互连,在一示例性方面中,延长或展开的通孔被提供在IC中的MOL层中。延长通孔被提供在MOL层中在该MOL层中的金属层下方并跨该MOL层的金属层中的两个或更多个毗邻金属层延伸。将互连移动到MOL层上方可简化IC的制造,特别是在低纳米(nm)节点尺寸下。
Description
本发明专利申请是国际申请号为PCT/US2015/046518,国际申请日为2015年8月24日,进入中国国家阶段的申请号为201580048484.X,名称为“采用使用延长通孔的金属线局部互连的中段制程(MOL)制造的集成电路(IC)及相关方法”的发明专利申请的分案申请。
优先权要求
本申请要求于2014年9月12日提交且题为“MIDDLE-OF-LINE(MOL)MANUFACTUREDINTEGRATED CIRCUITS(ICS)EMPLOYING LOCAL INTERCONNECTS OF METAL LINES USING ANELONGATED VIA,AND RELATED METHODS(采用使用延长通孔的金属线局部互连的中段制程(MOL)制造的集成电路(IC)及相关方法)”的美国专利申请序列号14/484,366的优先权,其内容被整体纳入于此。
技术领域
本公开的技术一般涉及集成电路(IC)的中段制程(middle-of-line,MOL)制造工艺,且尤其涉及促成金属层中的金属线之间的互连。本公开涉及采用使用延长通孔的金属线局部互连的中段制程(MOL)制造的集成电路(IC)及相关方法。
背景技术
计算设备在社会上已变得十分普遍。这些计算设备的日益增加的存在性部分地由于这些计算设备的日益增加的功能性和多用途性而加速。功能性和多用途性的这种增加已通过在小封装中提供越来越强大的处理能力来实现,如由摩尔定律宽松地认识到的。增加处理能力而同时减小集成电路(IC)的尺寸的压力已使传统制造工艺面临压力,尤其是随着节点尺寸已减小到低纳米(nm)维度(例如,<20nm)。
IC的当前半导体制造可包括前段制程(FEOL)、中段制程(MOL)和后段制程(BEOL)工艺。FEOL工艺可包括晶片制备、隔离、阱形成、栅极图案化、间隔物、扩展、源极/漏极注入、硅化物形成等等。MOL工艺可包括栅极接触部形成和IC的不同层之间的互连。BEOL工艺可包括用于将在FEOL和MOL工艺期间创建的半导体器件进行互连的一系列晶片处理步骤。现代半导体芯片产品的成功制造和鉴定涉及所采用的材料和工艺之间的相互作用。具体而言,在MOL工艺期间耦合MOL IC中的金属层中的金属线在当前的低纳米(nm)节点尺寸下越来越具有挑战性,特别是对于光刻印刷而言。随着MOL堆叠尺寸减小,金属线的间距被进一步减小,以使得由于紧间距,不可能在金属线上方的层中提供互连通孔以用于金属线互连。
发明内容
详细描述中公开的各方面包括采用使用延长通孔的金属线局部互连的中段制程(MOL)制造的集成电路(IC)。还公开了相关的方法。具体而言,金属层中的不同金属线可能需要在IC的MOL工艺期间被电互连。关于此,为了允许金属线被互连而不在金属线上方提供可能难以例如在印刷工艺中提供的此类互连,在一示例性方面中,在IC中的MOL层中提供延长或展开的通孔。延长的通孔在MOL层中的在该MOL层中的金属层下方提供并跨MOL层的金属层中的两个或更多个毗邻金属层延伸。因为这样的金属线通常单向且彼此平行地制造在金属层中,所以具有这样的电交互耦合允许在IC中的MOL层中对连接元件布线时有更大的设计灵活性。将互连移动到MOL层(例如,介电层上方)可简化集成电路(IC)的制造,特别是在低纳米(nm)节点尺寸下。
关于此,在一个方面,公开了一种IC。该IC包括基板。该IC还包括置于基板上方的MOL层。该IC进一步包括置于MOL层上方的金属互连层,该金属互连层包括第一金属导电元件和第二金属导电元件。该IC还包括置于金属互连层和MOL层之间的延长通孔,该延长通孔被置于与第一金属导电元件和第二金属导电元件接触以将第一金属导电元件与第二金属导电元件互连。
在另一方面,公开了一种IC。该IC包括基板。该IC还包括置于基板上方的MOL层。该IC进一步包括用于提供置于MOL层上方的金属互连的装置,该用于提供金属互连的装置包括金属互连层装置,该金属互连层装置包括第一金属导电装置和第二金属导电装置。该IC还包括用于将该金属互连层装置和该MOL层耦合的装置,该用于耦合的装置被定位在该MOL层上方且在该金属互连层装置下方。
在另一方面,公开了一种形成IC的方法。该方法包括:作为前段制程(FEOL)工艺的一部分,提供基板。该方法还包括:作为FEOL工艺的一部分,提供置于基板上方的MOL层。该方法进一步包括:作为MOL工艺的一部分,提供置于MOL层上方的金属互连层,该金属互连层包括第一金属导电元件和第二金属导电元件。该方法还包括:作为MOL工艺的一部分,提供置于金属互连层和MOL层之间的延长通孔,该延长通孔与第一金属导电元件和第二金属导电元件接触以将第一金属导电元件与第二金属导电元件互连。
附图说明
图1是在上层中具有金属层的传统三维(3D)集成电路(IC)(3DIC)的简化横截面视图;
图2是图1的3DIC的横截面视图的部分、更详细视图;
图3是从图1和2的3DIC移除的金属层的俯视平面图;
图4是根据本公开的一示例性方面的具有中段制程(MOL)层的3DIC的横截面视图,该MOL层采用使用延长通孔的、置于MOL层上方的金属线局部互连;
图5是从图4的3DIC移除的、图4的3DIC中的金属层中的金属线与延长通孔耦合的俯视平面图;
图6是图4中的3DIC的金属层中的被耦合的金属线的部分、更详细的横截面视图;
图7是用于制造图4的3DIC的示例性制造过程的流程图,该3DIC具有MOL层,该MOL层采用使用延长通孔的、置于MOL层上方的金属线局部互连;以及
图8是可包括图4的3DIC的示例性的基于处理器的系统的框图。
具体实施方式
现在参照附图,描述了本公开的若干示例性方面。措辞“示例性”在本文中用于表示“用作示例、实例或解说”。本文中描述为“示例性”的任何方面不必被解释为优于或胜过其他方面。
详细描述中所公开的各方面包括以中段制程(MOL)制造的采用使用延长通孔的金属线局部互连的集成电路(IC)。还公开了相关的方法。具体而言,金属层中的不同金属线可能需要在IC的MOL工艺期间被电互连。关于此,为了允许金属线被电互连而无需在金属线上方提供这样的互连(例如在印刷工艺中可能难以提供这种互连),在一示例性方面中,在IC中的MOL层中提供延长或展开的通孔。延长的通孔在MOL层中在该MOL层中的金属层下方提供并跨该MOL层的金属层中的两个或更多个毗邻金属层延伸。因为这些金属线通常单向且彼此平行地制造在金属层中,所以具有这种电交互耦合允许在对IC中的MOL层中的导电元件布线时有更大的设计灵活性。将互连移动到MOL层(例如,介电层上方)可简化集成电路(IC)的制造,尤其在低纳米(nm)节点尺寸下。
在讨论本公开的具有采用使用延长通孔的、置于MOL层上方的金属线局部互连的MOL层的IC的示例性方面之前,参考图1-3提供对用于向IC中的金属线提供互连的传统工艺的缺点的详细讨论。本公开的示例性方面的讨论在以下参考图4开始。
关于此,图1是具有有源组件的第一层12的传统三维(3D)IC(3DIC)10,在一示例性方面中,有源组件可以是具有栅极16、源极(S)18以及漏极(D)20的晶体管14。金属栅极连接22可覆盖每个栅极16或每个栅极16的至少一部分(例如,栅极区域)。介电层24位于金属栅极连接22上方。介电层24可由诸如氮化硅(SiN)之类的材料形成。与介电层24有区别且不同的层间电介质26可填充栅极16周围的空间并防止元件之间的短路。在一示例性方面中,层间电介质26是二氧化硅材料。替换地,层间电介质26可以是低K电介质或其它类似材料。
继续参考图1,3DIC 10可包括具有附加有源元件(未示出)的第二层28。第二层28可位于介电层24上方。第一层12和第二层28之间的互连可通过金属层和通孔的组合来实现。在一示例性方面中,第一金属层30位于介电层24下方且从源极18(或漏极20)向上延伸到介电层24。第二金属层32延伸穿过介电层24并且电耦合到第一金属层30。通孔34耦合至第二金属层32。同样,通孔36可延伸穿过介电层24到达金属栅极连接22以耦合至栅极16。通孔34和36可耦合至第二层28中的有源元件或可耦合至第二层28内的金属互连层40内的导电元件38。在实践中,金属互连层40内的导电元件38一般而言是平行的并且在单一方向上延伸,以使得导电元件38之间的互连不是自然存在的。随着IC(诸如3DIC 10)的节点尺寸减小,导电元件38之间的间距减小,并且在导电元件38之间布置互连变得更加困难。允许这样的互连会增加设计灵活性,这进而又增加IC的多功能性。
图1的导电元件38的相似但不同的视图在图2和3中提供。具体而言,通孔34和36在图2中的介电层24上面更容易看到,而导电元件38的平行、单向性质在图3中被最佳地图示。图2还示出高精度电阻器42,该高精度电阻器42可用作通孔44的虚设着陆焊盘。
为了允许设计者在元件之间进行连接时有更大的灵活性,本公开的示例性方面提供了可藉以在MOL工艺期间将金属互连层的导电元件进行互连的技术。在MOL工艺期间提供这样的互连允许在金属互连层的导电元件之间维持紧密的间距。更紧密的间距意味着设计将更紧凑并节省芯片面积。通过消除连接较低层的金属层上方的金属互连层的相邻线的需要,可实现进一步的成本节省。
关于此,图4示出了包括第一层52的3DIC 50,该第一层具有基板54,在该基板54上形成有源元件56。示例性有源元件56可以是晶体管,该晶体管可包括栅极58、源极60和漏极62。栅极58覆盖有金属栅极连接64,且金属栅极连接64覆盖有MOL层67中的介电层66(该介电层可以是SiN,且可以恢复为MOL层)。层间电介质68可填充入栅极58周围并为其提供绝缘。根据需要或期望,第一金属层70和第二金属层72可帮助提供至源极60和/或漏极62的电连接。进一步,通孔74可耦合至第二金属层72以提供至第二层76中的有源元件(未示出)的连接。作为非限制性示例,通孔74可以是钨工艺通孔。作为另一非限制性示例,通孔74也可以是穿硅通孔(TSV)。其它通孔78可提供从金属栅极连接64到第二层76中的有源元件的连接。除了第二层76内的任何有源元件之外,第二层76还可包括金属互连层80,在金属互连层80内具有导电元件82。应当领会,取代直接连接至有源元件,一个或多个通孔74、78可耦合至金属互连层80内的导电元件82。
在3DIC 50的MOL工艺期间,本公开的示例性方面展开或延长置于MOL层67中的通孔84。延长通孔84可耦合金属互连层80内的两个(或更多个)导电元件82(所述导电元件82在本示例中为金属线83)以建立电互连,而无需改变导电元件82的间距或以其它方式使得制造工艺变复杂。延长通孔84被提供在MOL层67和金属互连层80之间以提供导电元件82之间的互连。“延长”的意思是通孔84在MOL层67中被展开或延长,以使得该通孔跨越在IC中的两个导电元件82(诸如金属线)之间,以提供这些导电元件82之间的互连。例如,金属线可在IC中彼此相邻,如在图4中的3DIC 50中的金属线83所示。因为这些金属线通常单向且彼此平行地制造在金属层中,所以具有这种电交互耦合允许在对IC中的MOL层中的导电元件进行布线时有更大的设计灵活性。将互连移动到MOL层67(例如,介电层66上方)可简化IC的制造,尤其在低纳米(nm)节点尺寸下。尽管导电元件82被示为平行于栅极58,然而应当领会,在许多芯片制造工艺中,导电元件82垂直于栅极58。
作为非限制性示例,延长通孔84可以是钨工艺通孔。作为另一非限制性示例,延长通孔84也可以是穿硅通孔(TSV)。如果导电元件82垂直于栅极58,则延长通孔84可平行于栅极58延伸并可将虚设的第二金属层72或虚设焊盘(例如,比如高精度电阻器42,在图4中未示出)用作着陆焊盘。
如图5和6中更佳地图示的,展开的通孔84可跨越两个平行的导电元件82(诸如金属线83)以进行电连接。如图6中更好地解说的,可提供具有相对较高精度的虚设元件86(也被称为绝缘体)以帮助将展开的通孔84与栅极58或展开的通孔84下方的其它有源元件隔离。尽管特别构想了展开的通孔84可做出该连接,然而应当领会,其它金属结构也可做出该连接。而且,如本文所使用的,“用于耦合的装置”被定义成包括展开的通孔84和这样的其它金属结构。
图7示出根据本公开的各方面的用于创建图4的3DIC 50(或其它IC)的示例性过程90。过程90开始于提供基板54(框92)以及在基板54上提供栅极58(框94)。第一金属层70可通过最初图案化并蚀刻用于第一金属层70的空间(框96)以及图案化并蚀刻用于金属栅极连接64的空间(98)来创建。接着用金属来填充被蚀刻的图案以创建第一金属层70和金属栅极连接64,接着进行化学机械抛光(CMP)(框100)。
继续参考图7,过程90通过提供第二金属层72(框102)并且接着图案化并蚀刻以提供用于通孔74的空间(框104)以及图案化并蚀刻以提供通孔78(框106)来继续。随后用金属来填充被蚀刻的图案以创建通孔74、78,接着进行CMP(框108)。接下来可提供第二层76(框110)。
尽管被讨论成适用于IC且具体适用于3DIC,然而应当领会,本公开的各方面也可在其它半导体器件中使用。
根据本文公开的各方面的、根据用于金属层的MOL制造技术制造的图4的3DIC 50可在任何基于处理器的设备中提供或集成到任何基于处理器的设备中。非限定性的示例包括:机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、移动电话、蜂窝电话、计算机、便携式计算机、台式计算机、个人数字助理(PDA)、监视器、计算机监视器、电视机、调谐器、无线电、卫星无线电、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频碟(DVD)播放器,以及便携式数字视频播放器。
关于此,图8示出了可采用图4中示出的3DIC 50的基于处理器的系统120的示例。在该示例中,基于处理器的系统120包括一个或多个中央处理单元(CPU)122,其各自包括一个或多个处理器124。(诸)CPU 122可具有耦合到(诸)处理器124以用于对临时存储的数据快速访问的高速缓存存储器126。(诸)CPU 122被耦合至系统总线128,并且可将基于处理器的系统120中所包括的设备进行相互耦合。如众所周知的,(诸)CPU 122通过在系统总线128上交换地址、控制、以及数据信息来与这些其他设备通信。例如,(诸)CPU 122可将总线事务请求传达给存储器控制器130。尽管在图8中未解说,可以提供多个系统总线128。
其它设备可连接到系统总线128。如图8中解说的,作为示例,这些设备可包括存储器系统132、一个或多个输入设备134、一个或多个输出设备136、一个或多个网络接口设备138、以及一个或多个显示控制器140。(诸)输入设备134可包括任何类型的输入设备,包括但不限于输入键、开关、语音处理器等。(诸)输出设备136可包括任何类型的输出设备,包括但不限于音频、视频、其他视觉指示器等。(诸)网络接口设备138可以是被配置成允许去往和来自网络142的数据交换的任何设备。网络142可以是任何类型的网络,包括但不限于:有线或无线网络、私有或公共网络、局域网(LAN)、广域网(WLAN)、无线LAN(WLAN)和因特网。(诸)网络接口设备138可被配置成支持所期望的任何类型的通信协议。存储器系统132可包括一个或多个存储器单元144(0-N)。
(诸)CPU 122还可被配置成在系统总线128上访问(诸)显示控制器140以控制发送给一个或多个显示器146的信息。(诸)显示器控制器140经由一个或多个视频处理器148向(诸)显示器146发送要显示的信息,视频处理器148将要显示的信息处理成适于(诸)显示器146的格式。(诸)显示器146可包括任何类型的显示器,包括但不限于:阴极射线管(CRT)、液晶显示器(LCD)、发光二极管(LED)显示器、等离子显示器等。
本领域技术人员将进一步领会,结合本文所公开的诸方面描述的各种解说性逻辑块、模块、电路和算法可被实现为电子硬件、存储在存储器中或另一计算机可读介质中并由处理器或其它处理设备执行的指令、或这两者的组合。作为示例,本文中描述的设备可在任何电路、硬件组件、集成电路(IC)、或IC芯片中采用。本文所公开的存储器可以是任何类型和大小的存储器,且可配置成存储所期望的任何类型的信息。为清楚地解说这种可互换性,以上已经以其功能性的形式一般地描述了各种解说性组件、框、模块、电路和步骤。此类功能性如何被实现取决于具体应用、设计选择、和/或加诸于整体系统上的设计约束。技术人员可针对每种特定应用以不同方式来实现所描述的功能性,但此类实现决策不应被解读为致使脱离本公开的范围。
结合本文中公开的诸方面描述的各种解说性逻辑块、模块、以及电路可用设计成执行本文中描述的功能的处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或其他可编程逻辑器件、分立的门或晶体管逻辑、分立的硬件组件、或其任何组合来实现或执行。处理器可以是微处理器,但在替代方案中,处理器可以是任何常规处理器、控制器、微控制器或状态机。处理器还可被实现为计算设备的组合,例如DSP与微处理器的组合、多个微处理器、与DSP核心协同的一个或多个微处理器、或任何其它此类配置。
本文所公开的各方面可被体现为硬件和存储在硬件中的指令,并且可驻留在例如随机存取存储器(RAM)、闪存、只读存储器(ROM)、电可编程ROM(EPROM)、电可擦可编程ROM(EEPROM)、寄存器、硬盘、可移动盘、CD-ROM、或本领域中所知的任何其它形式的计算机可读介质中。示例性存储介质被耦合到处理器,以使得处理器能从/向该存储介质读取/写入信息。在替换方案中,存储介质可以被整合到处理器。处理器和存储介质可驻留在ASIC中。ASIC可驻留在远程站中。在替换方案中,处理器和存储介质可作为分立组件驻留在远程站、基站或服务器中。
还注意到,本文任何示例性方面中描述的操作步骤是为了提供示例和讨论而被描述的。所描述的操作可按除了所解说的顺序之外的众多不同顺序来执行。此外,在单个操作步骤中描述的操作实际上可在多个不同步骤中执行。另外,可组合示例性方面中讨论的一个或多个操作步骤。将理解,如对本领域技术人员显而易见地,在流程图中解说的操作步骤可进行众多不同的修改。本领域技术人员还将理解,可使用各种不同技术和技艺中的任何一种来表示信息和信号。例如,以上描述通篇引述的数据、指令、命令、信息、信号、位(比特)、码元、和码片可由电压、电流、电磁波、磁场或磁粒子、光场或光学粒子、或其任何组合来表示。
提供对本公开的先前描述是为使得本领域任何技术人员皆能够制作或使用本公开。对本公开的各种修改对本领域技术人员而言将容易是显而易见的,并且本文中所定义的普适原理可被应用到其他变型而不会脱离本公开的精神或范围。由此,本公开并非旨在被限定于本文中所描述的示例和设计,而是应被授予与本文中所公开的原理和新颖特征一致的最广义的范围。
Claims (20)
1.一种集成电路IC,包括:
包括有源元件的基板,其中所述有源元件中的至少一个包括栅极;
置于所述基板上方的中段制程MOL层;
置于所述MOL层上方的金属互连层,所述金属互连层包括导电元件,其中所述导电元件垂直于所述栅极;以及
置于所述MOL层内的延长通孔,其中所述延长通孔平行于所述栅极延伸。
2.如权利要求1所述的IC,其特征在于,进一步包括虚设金属层或虚设焊盘,作为所述延长通孔的着陆焊盘。
3.如权利要求1所述的IC,其特征在于,进一步包括位于所述基板和所述MOL层之间的层间电介质,所述层间电介质与所述MOL层不同且有区别。
4.如权利要求1所述的IC,其特征在于,所述MOL层包括介电层。
5.如权利要求1所述的IC,其特征在于,所述导电元件包括金属线。
6.如权利要求1所述的IC,其特征在于,所述导电元件彼此平行。
7.如权利要求1所述的IC,其特征在于,进一步包括置于金属结构下方的绝缘体,所述绝缘体将所述金属结构与关联于所述基板的所述有源元件隔离。
8.如权利要求1所述的IC,其特征在于,所述IC是三维3D IC。
9.如权利要求4所述的IC,其特征在于,所述介电层包括氮化硅SiN。
10.如权利要求1所述的IC,其特征在于,所述延长通孔包括钨工艺通孔。
11.如权利要求1所述的IC,其特征在于,所述延长通孔包括延长的穿硅通孔TSV。
12.如权利要求1所述的IC,其特征在于,所述IC被集成到半导体管芯中。
13.如权利要求1所述的IC,其特征在于,所述IC被集成到选自由以下各项组成的组的设备中:娱乐单元;导航设备;通信设备;固定位置数据单元;移动位置数据单元;计算机;个人数字助理PDA;监视器;电视机;调谐器;以及无线电。
14.一种集成电路IC,包括:
包括有源元件的基板,其中所述有源元件中的至少一个包括栅极;
置于所述基板上方的中段制程MOL层;
用于提供置于所述MOL层上方的金属互连的装置,所述用于提供所述金属互连的装置包括金属互连层装置,所述金属互连层装置包括导电装置,其中所述导电装置垂直于所述栅极;以及
用于将所述金属互连层装置和所述MOL层耦合的装置,所述用于耦合的装置被定位在所述MOL层中,其中所述延长通孔平行于所述栅极延伸。
15.一种形成集成电路IC的方法,包括:
作为前段制程FEOL工艺的一部分,提供包括有源元件的基板,其中所述有源元件中的至少一个包括栅极;
作为所述FEOL工艺的一部分,提供置于所述基板上方的中段制程MOL层;
作为MOL工艺的一部分,提供置于所述MOL层上方的金属互连层,所述金属互连层包括导电元件,其中所述导电元件垂直于所述栅极;以及
作为所述MOL工艺的一部分,提供置于所述MOL层内的延长通孔,其中所述延长通孔平行于所述栅极延伸。
16.如权利要求15所述的方法,其特征在于,进一步包括提供虚设金属层或虚设焊盘,作为所述延长通孔的着陆焊盘。
17.如权利要求15所述的方法,其特征在于,进一步包括提供与所述MOL层有区别且不同于所述MOL层的层间电介质,所述层间电介质位于所述MOL层下方。
18.如权利要求15所述的方法,其特征在于,所述有源元件包括晶体管。
19.如权利要求15所述的方法,其特征在于,提供所述MOL层包括提供介电层。
20.如权利要求15所述的方法,其特征在于,提供所述MOL层包括提供氮化硅SiN层。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/484,366 US9620454B2 (en) | 2014-09-12 | 2014-09-12 | Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods |
US14/484,366 | 2014-09-12 | ||
CN201580048484.XA CN106716631B (zh) | 2014-09-12 | 2015-08-24 | 采用使用延长通孔的金属线局部互连的中段制程(mol)制造的集成电路(ic)及相关方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201580048484.XA Division CN106716631B (zh) | 2014-09-12 | 2015-08-24 | 采用使用延长通孔的金属线局部互连的中段制程(mol)制造的集成电路(ic)及相关方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111584459A true CN111584459A (zh) | 2020-08-25 |
Family
ID=54105987
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201580048484.XA Active CN106716631B (zh) | 2014-09-12 | 2015-08-24 | 采用使用延长通孔的金属线局部互连的中段制程(mol)制造的集成电路(ic)及相关方法 |
CN202010476256.5A Pending CN111584459A (zh) | 2014-09-12 | 2015-08-24 | 采用使用延长通孔的金属线局部互连的中段制程mol制造的集成电路ic及相关方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201580048484.XA Active CN106716631B (zh) | 2014-09-12 | 2015-08-24 | 采用使用延长通孔的金属线局部互连的中段制程(mol)制造的集成电路(ic)及相关方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9620454B2 (zh) |
EP (1) | EP3192098B1 (zh) |
CN (2) | CN106716631B (zh) |
WO (1) | WO2016039968A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7947601B2 (en) | 2009-03-24 | 2011-05-24 | Micron Technology, Inc. | Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device |
US9691695B2 (en) * | 2015-08-31 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure |
US10510688B2 (en) | 2015-10-26 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via rail solution for high power electromigration |
CN109492273B (zh) * | 2018-10-22 | 2022-11-15 | 珠海一微半导体股份有限公司 | 一种基于通孔的自动打孔方法 |
US11710657B2 (en) | 2020-09-29 | 2023-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Middle-of-line interconnect structure having air gap and method of fabrication thereof |
US20230061693A1 (en) * | 2021-08-24 | 2023-03-02 | Qualcomm Incorporated | Three-dimensional (3d) interconnect structures employing via layer conductive structures in via layers and related fabrication methods |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4988643A (en) * | 1989-10-10 | 1991-01-29 | Vlsi Technology, Inc. | Self-aligning metal interconnect fabrication |
US20070296064A1 (en) * | 2006-06-22 | 2007-12-27 | Gates Stephen M | Electronic structures utilizing etch resistant boron and phosphorus materials and methods to form same |
US20090152724A1 (en) * | 2007-12-12 | 2009-06-18 | International Business Machines Corporation | Ic interconnect for high current |
US20100200992A1 (en) * | 2008-09-26 | 2010-08-12 | International Business Machines Corporation | Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced |
US20110248404A1 (en) * | 2010-04-08 | 2011-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy Pattern in Wafer Backside Routing |
EP2581935A2 (en) * | 2011-10-11 | 2013-04-17 | Broadcom Corporation | MOM capacitor having electrodes made from local interconnects and manufacturing method thereof |
CN103137610A (zh) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | 一种微加热装置及形成方法 |
US20130181330A1 (en) * | 2012-01-13 | 2013-07-18 | Qualcomm Incorporated | Integrating through substrate vias into middle-of-line layers of integrated circuits |
US20140124951A1 (en) * | 2012-11-06 | 2014-05-08 | Samsung Electronics Co., Ltd. | Integrated Circuit Devices Including Through-Silicon Via (TSV) Contact Pads Electronically Insulated from a Substrate |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006059939A (ja) | 2004-08-19 | 2006-03-02 | Fujitsu Ltd | Misキャパシタおよびmisキャパシタ作成方法 |
US7160772B2 (en) * | 2005-02-23 | 2007-01-09 | International Business Machines Corporation | Structure and method for integrating MIM capacitor in BEOL wiring levels |
US7863188B2 (en) * | 2005-07-29 | 2011-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20070218685A1 (en) | 2006-03-17 | 2007-09-20 | Swaminathan Sivakumar | Method of forming trench contacts for MOS transistors |
US7553760B2 (en) * | 2006-10-19 | 2009-06-30 | International Business Machines Corporation | Sub-lithographic nano interconnect structures, and method for forming same |
US8421128B2 (en) * | 2007-12-19 | 2013-04-16 | International Business Machines Corporation | Semiconductor device heat dissipation structure |
US7858468B2 (en) * | 2008-10-30 | 2010-12-28 | Micron Technology, Inc. | Memory devices and formation methods |
US8912076B2 (en) | 2008-11-05 | 2014-12-16 | Texas Instruments Incorporated | Crack deflector structure for improving semiconductor device robustness against saw-induced damage |
US8133774B2 (en) | 2009-03-26 | 2012-03-13 | International Business Machines Corporation | SOI radio frequency switch with enhanced electrical isolation |
US8383510B2 (en) | 2011-03-04 | 2013-02-26 | Globalfoundries Inc. | Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials |
US8421186B2 (en) | 2011-05-31 | 2013-04-16 | International Business Machines Corporation | Electrically programmable metal fuse |
US9059263B2 (en) | 2011-11-09 | 2015-06-16 | QUALCOMM Incorpated | Low-K dielectric protection spacer for patterning through substrate vias through a low-K wiring layer |
US8779592B2 (en) | 2012-05-01 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via-free interconnect structure with self-aligned metal line interconnections |
US20130307032A1 (en) | 2012-05-16 | 2013-11-21 | Globalfoundries Inc. | Methods of forming conductive contacts for a semiconductor device |
US8901627B2 (en) | 2012-11-16 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Jog design in integrated circuits |
US8766258B1 (en) * | 2012-12-12 | 2014-07-01 | International Business Machines Corporation | Authentication using graphene based devices as physical unclonable functions |
CN103915384B (zh) | 2013-01-08 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US9012293B2 (en) | 2013-01-10 | 2015-04-21 | Globalfoundries Singapore Pte. Ltd. | Sandwich damascene resistor |
US8933562B2 (en) * | 2013-01-24 | 2015-01-13 | International Business Machines Corporation | In-situ thermoelectric cooling |
US20150201495A1 (en) * | 2014-01-14 | 2015-07-16 | Qualcomm Incorporated | Stacked conductive interconnect inductor |
US9196583B1 (en) * | 2014-05-09 | 2015-11-24 | Qualcomm Incorporated | Via material selection and processing |
-
2014
- 2014-09-12 US US14/484,366 patent/US9620454B2/en active Active
-
2015
- 2015-08-24 CN CN201580048484.XA patent/CN106716631B/zh active Active
- 2015-08-24 EP EP15763137.5A patent/EP3192098B1/en active Active
- 2015-08-24 CN CN202010476256.5A patent/CN111584459A/zh active Pending
- 2015-08-24 WO PCT/US2015/046518 patent/WO2016039968A1/en active Application Filing
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4988643A (en) * | 1989-10-10 | 1991-01-29 | Vlsi Technology, Inc. | Self-aligning metal interconnect fabrication |
US20070296064A1 (en) * | 2006-06-22 | 2007-12-27 | Gates Stephen M | Electronic structures utilizing etch resistant boron and phosphorus materials and methods to form same |
US20090152724A1 (en) * | 2007-12-12 | 2009-06-18 | International Business Machines Corporation | Ic interconnect for high current |
US20100200992A1 (en) * | 2008-09-26 | 2010-08-12 | International Business Machines Corporation | Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced |
US20110248404A1 (en) * | 2010-04-08 | 2011-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy Pattern in Wafer Backside Routing |
EP2581935A2 (en) * | 2011-10-11 | 2013-04-17 | Broadcom Corporation | MOM capacitor having electrodes made from local interconnects and manufacturing method thereof |
CN103137610A (zh) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | 一种微加热装置及形成方法 |
US20130181330A1 (en) * | 2012-01-13 | 2013-07-18 | Qualcomm Incorporated | Integrating through substrate vias into middle-of-line layers of integrated circuits |
US20140124951A1 (en) * | 2012-11-06 | 2014-05-08 | Samsung Electronics Co., Ltd. | Integrated Circuit Devices Including Through-Silicon Via (TSV) Contact Pads Electronically Insulated from a Substrate |
Also Published As
Publication number | Publication date |
---|---|
CN106716631B (zh) | 2020-06-26 |
EP3192098B1 (en) | 2020-03-18 |
US20160079175A1 (en) | 2016-03-17 |
CN106716631A (zh) | 2017-05-24 |
EP3192098A1 (en) | 2017-07-19 |
WO2016039968A1 (en) | 2016-03-17 |
US9620454B2 (en) | 2017-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108886018B (zh) | 在用于集成电路(ic)的互连结构中形成自对准垂直互连通道(via) | |
CN106716631B (zh) | 采用使用延长通孔的金属线局部互连的中段制程(mol)制造的集成电路(ic)及相关方法 | |
TWI818016B (zh) | 裝置層互連 | |
US9343369B2 (en) | Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems | |
TWI747085B (zh) | 包含導電互連結構之微電子裝置、相關電子系統及相關方法 | |
US9607893B1 (en) | Method of forming self-aligned metal lines and vias | |
KR102242279B1 (ko) | 집적 회로 퓨즈 구조체 | |
JP2015079961A (ja) | Tsv構造を具備した集積回路素子及びその製造方法 | |
US8803284B2 (en) | Thick on-chip high-performance wiring structures | |
US11705395B2 (en) | Core fill to reduce dishing and metal pillar fill to increase metal density of interconnects | |
TW202230621A (zh) | 用於半導體晶粒的互連結構的金屬化層、用於製造所述金屬化層的方法、包含所述金屬化層的積體電路結構及包含所述積體電路結構的計算裝置 | |
US9728838B2 (en) | On chip antenna with opening | |
TW201606892A (zh) | 具有時脈閘控功率及路由於下方的信號之兩側上的金屬 | |
US20160079167A1 (en) | Tie-off structures for middle-of-line (mol) manufactured integrated circuits, and related methods | |
CN114944385A (zh) | 基于虚设穿硅过孔板的去耦电容器 | |
US11710636B2 (en) | Metal and spacer patterning for pitch division with multiple line widths and spaces | |
US20170317167A1 (en) | SEMICONDUCTOR INTEGRATED CIRCUITS (ICs) EMPLOYING LOCALIZED LOW DIELECTRIC CONSTANT (LOW-K) MATERIAL IN INTER-LAYER DIELECTRIC (ILD) MATERIAL FOR IMPROVED SPEED PERFORMANCE | |
US11610810B2 (en) | Maskless air gap enabled by a single damascene process | |
CN109844929B (zh) | 采用具有多个沟道结构的场效应晶体管(fet)并且不具有浅沟槽隔离(sti)空隙引起的电短路的半导体器件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |