CN111584435A - Substrate, chip packaging structure and preparation method thereof - Google Patents
Substrate, chip packaging structure and preparation method thereof Download PDFInfo
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- CN111584435A CN111584435A CN202010406913.9A CN202010406913A CN111584435A CN 111584435 A CN111584435 A CN 111584435A CN 202010406913 A CN202010406913 A CN 202010406913A CN 111584435 A CN111584435 A CN 111584435A
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- chip
- substrate
- substrate body
- back surface
- base plate
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- 239000000758 substrate Substances 0.000 title claims abstract description 96
- 238000004806 packaging method and process Methods 0.000 title abstract description 17
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000005452 bending Methods 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 4
- 238000007781 pre-processing Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 2
- 239000003973 paint Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007590 electrostatic spraying Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- MECHNRXZTMCUDQ-RKHKHRCZSA-N vitamin D2 Chemical compound C1(/[C@@H]2CC[C@@H]([C@]2(CCC1)C)[C@H](C)/C=C/[C@H](C)C(C)C)=C\C=C1\C[C@@H](O)CCC1=C MECHNRXZTMCUDQ-RKHKHRCZSA-N 0.000 description 1
- 235000001892 vitamin D2 Nutrition 0.000 description 1
- 239000011653 vitamin D2 Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The application discloses base plate, chip packaging structure and preparation method thereof, the provided base plate comprises a base plate body, the base plate body is provided with a chip setting area, the back of the base plate body corresponding to the chip setting area is covered with a solder-proof barrier layer or is not provided with the solder-proof barrier layer, the provided chip packaging structure comprises a chip and a base plate, and in the method for preparing the chip packaging structure, the chip is connected to the base plate. Because the back of the substrate body corresponding to the chip setting area is completely covered with the solder resist barrier layer or is not provided with the solder resist barrier layer, the back of the substrate can be ensured to be flat, the stress is uniform during plastic packaging, and the risk of chip breakage is greatly reduced.
Description
Technical Field
The present application relates generally to the field of semiconductor manufacturing technologies, and more particularly, to a substrate, a chip package structure and a method for manufacturing the same.
Background
In semiconductor manufacturing, with the increasing development of semiconductor technology, chips are also developing towards small and thin trends, and the risk of chip cracking is also increasing. The substrate plays an important role as a carrier of the chip, and the chip is easily cracked due to the unevenness of the back surface of the substrate.
As shown in fig. 1 to 3, different layers of adhesive films are adhered to the back of the unit with dummy sheets, and the adhesive films are positioned below the effective area of the chip 12 across the row adhering edges; plastic packaging is carried out on the same semiconductor packaging equipment under different die assembly 14 pressures; 10 decaps were randomly extracted from 30 samples, and the results are shown in fig. 4. It can be seen that the greater the number of layers of tape 15, the greater the clamping pressure of the clamp 14, and the greater the probability of false sheet breakage. It can be seen that when the substrate 11 has a foreign material warpage on the back surface, particularly under the chip 12, the chip 12 may be broken.
It can be seen that the general failure mechanism of chip cracking due to substrate design problems is as follows: when the whole die cavity is filled with the plastic packaging material, vertical pressure is applied to the whole cavity; under the action of high pressure, the substrate is flattened; due to the fact that the back face of the substrate is uneven, the substrate is folded at the position with the height difference, and the chip at the corresponding position is also stressed and folded at the moment, and accordingly the chip is broken.
As shown in fig. 5 and 6, the analysis was performed by taking an LGA frame and a BGA frame as examples. Two LGA frames are selected, the height difference between the green paint and the bonding pad 13 is measured, the fact that the boundary of the green paint covered on the periphery of the bonding pad 13 on the back of the substrate is found, the green paint is obviously protruded, and the measurement result reaches the height difference even exceeding 30 mu m. And more through holes are formed in two sides of a crack initiation point of the BGA framework, the surface of the substrate at the through holes is uneven, and the height difference reaches 17 mu m. Research on the back structure of the substrate shows that the back of the substrate corresponding to the chip arrangement area is uneven, so that uneven stress is caused during plastic packaging, and the chip is broken.
Disclosure of Invention
In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a substrate, a chip package structure and a method for manufacturing the same.
In a first aspect, the present invention provides a substrate, which is characterized by comprising a substrate body, wherein a chip arrangement region is arranged on a front surface of the substrate body, and a solder resist barrier layer is fully covered or not arranged on a back surface of the substrate body corresponding to the chip arrangement region.
In one embodiment, a stress compensation structure is arranged on the chip arrangement region, and the stress compensation structure can offset chip bending caused by stress generated by unevenness of the back surface of the substrate body.
In one embodiment, the stress compensation structure includes a groove, the groove is disposed on the chip disposing region, and the groove is filled with a flexible buffer material.
In one embodiment, the solder mask barrier layer comprises green oil, and the coverage height of the green oil enables the back surface of the substrate to be a flat surface.
In one embodiment, the flexible cushioning material comprises an underfill.
In one embodiment, the placement area of the underfill is larger than the size of the recess.
In a second aspect, the present invention provides a chip package structure, which is characterized in that the chip package structure comprises the substrate and a chip, wherein the chip is connected to the substrate.
In a third aspect, the present invention provides a method for manufacturing a chip package structure, which is characterized in that the method for manufacturing the chip package structure comprises:
preprocessing a substrate body;
attaching a chip to the substrate body;
wherein, carrying out the preliminary treatment to the base plate body includes:
and the back surface of the substrate body corresponding to the chip setting area is fully covered with the solder mask barrier layer.
In one embodiment, the step of attaching a die to the substrate body by soldering includes:
a groove is arranged on the substrate body;
filling flexible buffer materials in the grooves;
and adhering the chip to the flexible buffer material.
Compared with the prior art, the invention has the following advantages: the substrate provided by the invention comprises a substrate body, wherein the substrate body is provided with a chip arrangement area, the back surface of the substrate body corresponding to the chip arrangement area is fully covered with a solder resist barrier layer or is not provided with the solder resist barrier layer, the chip packaging structure comprises a chip and a substrate, and the chip is connected onto the substrate in the chip packaging structure preparation method. Because the back of the substrate body corresponding to the chip setting area is completely covered with the solder resist barrier layer or is not provided with the solder resist barrier layer, the back of the substrate can be ensured to be flat, the stress is uniform during plastic packaging, and the risk of chip breakage is greatly reduced.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a top view of an experimental chip package structure provided in the prior art;
FIG. 2 is a side view of an experimental chip package structure provided by the prior art;
FIG. 3 is a diagram illustrating a state of an experimental chip package structure according to the prior art;
FIG. 4 is a histogram of crack numbers for an experimental chip package structure provided by the prior art;
fig. 5 is a state diagram of a chip package structure provided in the prior art before packaging;
fig. 6 is a state diagram of a chip package structure provided in the prior art during packaging;
FIG. 7 is a front view of a substrate according to an embodiment of the present invention;
FIG. 8 is a backside structural view of a substrate according to an embodiment of the present invention;
fig. 9 is a top view of a chip package structure according to an embodiment of the invention;
fig. 10 is a side view of a chip package structure provided by an embodiment of the invention;
fig. 11 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the present invention.
In fig. 1 to 6: 11-substrate, 12-chip, 13-pad, 14-mold-close, 15-tape;
in fig. 7 to 10: 21-substrate, 211-substrate body, 212-chip placement area, 213-solder resist barrier, 22-chip, 23-pad, 24-flexible buffer material.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
As mentioned in the background, the LGA frame and BGA frame were analyzed for findings. Two LGA frames are selected, the height difference between the green paint and the bonding pad is measured, the fact that the boundary of the green paint is covered on the periphery of the bonding pad on the back of the substrate is found, the green paint is obviously protruded, and the measurement result reaches or even exceeds the height difference of 30 mu m. And more through holes are formed in two sides of a crack initiation point of the BGA framework, the surface of the substrate at the through holes is uneven, and the height difference reaches 17 mu m. Research on the back structure of the substrate shows that the back of the substrate corresponding to the chip arrangement area is uneven, so that uneven stress is caused during plastic packaging, and the chip is broken.
Therefore, how to provide a substrate with a flat back surface in the chip placement area will become an improvement of the present application. In view of the above, the present application provides a substrate, a chip package structure and a method for manufacturing the same. The basic idea of the invention is to flatten the back of the substrate chip setting area, so that the chip is stressed uniformly during plastic package, and the chip is prevented from cracking.
Referring to fig. 7-10, a substrate of the present invention is shown.
As shown in fig. 7 and 8, the substrate includes a substrate body 211, the front surface of the substrate body 211 has a chip disposing region 212, and the back surface of the substrate body 211 corresponding to the chip disposing region 212 is completely covered with a solder resist layer 213 or is not provided with the solder resist layer 213.
Because the back of the substrate body 211 corresponding to the chip setting area 212 is completely covered with the solder resist barrier layer 213 or is not provided with the solder resist barrier layer 213, the back of the substrate can be ensured to be flat, the stress is uniform during plastic packaging, and the risk of chip fracture is greatly reduced.
On the basis of the above embodiment, the chip disposing region 212 is provided with a stress compensation structure, and the stress compensation structure can offset the chip bending caused by the stress generated by the unevenness of the back surface of the substrate body 211. Under the condition that the back surface of the substrate body 211 corresponding to the chip setting area 212 is not smooth enough, the substrate body 211 is still stressed, and the stress compensation structure mainly plays a role in relieving the bending stress applied to the substrate body 211, blocking the propagation of the bending stress and preventing the chip from being stressed.
Specifically, the stress compensation structure includes a groove, the groove is disposed on the chip disposing region 212, and the groove is filled with the flexible buffer material 24. When the plastic package material is filled in the whole die cavity, under the action of high pressure, the back surface of the substrate body 211 is uneven, the substrate body 211 is bent at the position with height difference, the flexible buffer material 24 unloads the bending stress, the chip at the corresponding position cannot be stressed basically, and the risk of chip fracture is effectively reduced.
In this embodiment, the solder mask barrier 213 includes a green oil, and the coverage height of the green oil is such that the back surface of the substrate is a flat surface. The flexible buffer material 24 comprises an adhesive filling, the area of which is larger than the size of the recess, which has the advantage that hard contact of the chip with the edges of the recess is prevented. The flexible buffer material 24 fills and overflows the groove to partially wrap the side surface of the chip, so that the stress buffering effect is further improved.
Referring to fig. 7 to 10, there are shown chip package structures of the present invention.
As shown in fig. 9 and 10, the chip package structure includes the substrate 21 and the chip 22, and the chip 22 is connected to the substrate 21.
The flip-chip packaging structure is shown, wherein functional bumps are arranged on a chip 22, a bonding pad 23 is arranged on a substrate 21, a flexible buffer material 24 is arranged between the chip 22 and the substrate 21, and the flexible buffer material 24 fills and overflows a groove to partially cover the side surface of the chip 22 without influencing the electric conduction of the chip 22. The flexible buffer material 24 is filled with glue, and the chip 22 and the substrate 21 are bonded by the filled glue while the buffer is realized.
As shown in fig. 11, a method for manufacturing a chip package structure according to the present invention is shown for manufacturing the chip package structure described above.
In step 10, the substrate body 211 is pretreated;
in step 20, a chip 22 is connected to the substrate body 211;
wherein, the preprocessing the substrate body 211 includes:
the solder resist layer 213 is entirely covered on the back surface of the substrate body 211 corresponding to the chip 22 setting region 212.
The solder resist 213 may be the above-mentioned green oil, and the green oil may be bonded to the back surface of the substrate body 211 corresponding to the chip 22 disposition region 212 by electrostatic spraying.
In step 10, the step of connecting the chip 22 to the substrate body 211 by soldering includes:
a groove is arranged on the substrate body 211;
filling flexible buffer material 24 in the groove;
the chip 22 is bonded to the flexible cushioning material 24.
The flexible buffer material 24 may be filled with glue, and the glue should not adhere between the functional bumps of the chip 22 and the pads 23 of the substrate 21 during the filling process, and affect the soldering effect between the chip 22 and the substrate.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (9)
1. The substrate is characterized by comprising a substrate body, wherein a chip setting area is arranged on the front surface of the substrate body, and a welding-proof blocking layer is fully covered or not arranged on the back surface of the substrate body corresponding to the chip setting area.
2. The substrate according to claim 1, wherein a stress compensation structure is disposed on the chip disposing region, and the stress compensation structure can counteract chip bending caused by stress generated by unevenness of the back surface of the substrate body.
3. The substrate according to claim 2, wherein the stress compensation structure comprises a groove disposed on the chip-disposing region, and the groove is filled with a flexible buffer material.
4. The substrate of claim 1, wherein the solder mask barrier comprises a green oil having a coverage height such that the back surface of the substrate is a flat surface.
5. A substrate according to claim 3, wherein the flexible buffer material comprises an underfill.
6. A substrate according to claim 5, wherein the glue fill is provided over an area greater than the dimensions of the recess.
7. A chip package structure comprising the substrate of any one of claims 1 to 6 and a chip, wherein the chip is connected to the substrate.
8. A method for manufacturing the chip package structure according to claim 7, comprising:
preprocessing a substrate body;
attaching a chip to the substrate body;
wherein, carrying out the preliminary treatment to the base plate body includes:
and the back surface of the substrate body corresponding to the chip setting area is fully covered with the solder mask barrier layer.
9. The method for manufacturing a chip package structure according to claim 8, wherein the step of connecting a chip to the substrate body by soldering comprises:
a groove is arranged on the substrate body;
filling flexible buffer materials in the grooves;
and adhering the chip to the flexible buffer material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010406913.9A CN111584435B (en) | 2020-05-14 | 2020-05-14 | Substrate, chip packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010406913.9A CN111584435B (en) | 2020-05-14 | 2020-05-14 | Substrate, chip packaging structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111584435A true CN111584435A (en) | 2020-08-25 |
| CN111584435B CN111584435B (en) | 2023-11-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010406913.9A Active CN111584435B (en) | 2020-05-14 | 2020-05-14 | Substrate, chip packaging structure and preparation method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004134821A (en) * | 2004-02-06 | 2004-04-30 | Toshiba Corp | Semiconductor apparatus |
| JP2005175113A (en) * | 2003-12-10 | 2005-06-30 | Fdk Corp | Printed wiring board for mounting flip chip |
| US20070235884A1 (en) * | 2006-03-29 | 2007-10-11 | Shih-Ping Hsu | Surface structure of flip chip substrate |
| CN106298729A (en) * | 2015-05-12 | 2017-01-04 | 南茂科技股份有限公司 | Packaging structure and manufacturing method thereof |
-
2020
- 2020-05-14 CN CN202010406913.9A patent/CN111584435B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005175113A (en) * | 2003-12-10 | 2005-06-30 | Fdk Corp | Printed wiring board for mounting flip chip |
| JP2004134821A (en) * | 2004-02-06 | 2004-04-30 | Toshiba Corp | Semiconductor apparatus |
| US20070235884A1 (en) * | 2006-03-29 | 2007-10-11 | Shih-Ping Hsu | Surface structure of flip chip substrate |
| CN106298729A (en) * | 2015-05-12 | 2017-01-04 | 南茂科技股份有限公司 | Packaging structure and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN111584435B (en) | 2023-11-24 |
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