CN111565126A - Network situation perception acquisition device - Google Patents

Network situation perception acquisition device Download PDF

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Publication number
CN111565126A
CN111565126A CN201910981730.7A CN201910981730A CN111565126A CN 111565126 A CN111565126 A CN 111565126A CN 201910981730 A CN201910981730 A CN 201910981730A CN 111565126 A CN111565126 A CN 111565126A
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CN
China
Prior art keywords
network
control chip
communication circuit
cpu
ethernet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910981730.7A
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Chinese (zh)
Inventor
肖相生
高渊
李占才
刘杨
赵丰
张晓光
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Jiangsu Yunyong Electronic Technology Co ltd
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Jiangsu Yunyong Electronic Technology Co ltd
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Publication date
Application filed by Jiangsu Yunyong Electronic Technology Co ltd filed Critical Jiangsu Yunyong Electronic Technology Co ltd
Priority to CN201910981730.7A priority Critical patent/CN111565126A/en
Publication of CN111565126A publication Critical patent/CN111565126A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/04—Processing captured monitoring data, e.g. for logfile generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4406—Loading of operating system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/06—Generation of reports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a network situation perception acquisition device which comprises a main control board and a hard disk, wherein an operating system is preinstalled in the hard disk, a CPU (central processing unit) processor, a multi-path gigabit Ethernet communication circuit, a multi-path optical port communication circuit, a USB (universal serial bus) interface circuit, a PCIE (peripheral component interface express) interface, a DDR3 memory bank, a NOR Flash memory, a NAND Flash memory and a network port expansion board are carried on the main control board, and the network port expansion board is electrically connected with the CPU processor through the PCIE interface. By adopting the NXP QoriQ T4240 processor of the high-performance non-X86 and expanding a plurality of network interfaces through the expansion board, the high-performance CPU processor is matched with the plurality of network interfaces and can efficiently and cooperatively work, so that the CPU processor can not only quickly analyze and process data, but also completely meet the requirement of power consumption required by the simultaneous work of the plurality of network interfaces.

Description

Network situation perception acquisition device
Technical Field
The invention relates to the technical field of network equipment, in particular to a network situation perception acquisition device.
Background
The network situation perception acquisition device is generally deployed in each level of regulation and control center (monitoring and maintenance center) and each level of local area network of the power plant/transformer substation power monitoring system, and is a device system for acquiring, analyzing and processing network security data of a main station or the power plant power monitoring system and communicating with the main station system.
Because network data of a plurality of objects, such as data of a general-purpose host, data of industrial control equipment, data of network equipment, data of safety equipment, etc., needs to be acquired, the device needs to be configured with a plurality of data acquisition interfaces to complete data acquisition. Since the network data is collected, the data collection interface of the device generally adopts a network interface.
The device not only needs to collect a large amount of data, but also needs to analyze and process the data and communicate with the master station system, so that a high-performance CPU (central processing unit) processor is needed. However, many high-performance CPU processors (such as X86 processors) can analyze and process data quickly, but if many network interfaces are configured and the interfaces operate simultaneously, the power consumption load of the CPU processor will be greatly increased, and in a serious case, the CPU processor will be down directly. Therefore, it is necessary to develop a network situation awareness acquisition device with a high-performance CPU processor that is capable of working simultaneously in cooperation with multiple network interfaces.
Disclosure of Invention
The invention aims to overcome the technical problems and provides a network situation perception acquisition device.
In order to achieve the purpose, the invention adopts the following technical scheme:
a network situation perception acquisition device comprises a main control board and a hard disk, wherein an operating system is preinstalled in the hard disk, a CPU (central processing unit) processor, a multi-path gigabit Ethernet communication circuit, a multi-path optical port communication circuit, a USB (universal serial bus) interface circuit, a PCIE (peripheral component interface express) interface, a DDR (double data rate) 3 memory bank, a NOR Flash memory, a NAND Flash memory and a network port expansion board are carried on the main control board, and the network port expansion board is electrically connected with the CPU processor through the PCIE interface; the gigabit Ethernet communication circuit, the optical port communication circuit, the USB interface circuit, the DDR3 memory bank, the NOR Flash memory and the NAND Flash memory are all electrically connected with the CPU.
Furthermore, the network port expansion board is provided with a plurality of gigabit ethernet communication circuits and a plurality of optical port communication circuits, each gigabit ethernet communication circuit comprises a first ethernet control chip and a network port, the CPU processor is connected to the network port through the first ethernet control chip, each optical port communication circuit comprises a second ethernet control chip and an SFP optical module connector, and the CPU processor is connected to the SFP optical module connector through the second ethernet control chip.
Furthermore, each path of gigabit ethernet communication circuit comprises a third ethernet control chip and a network port, the CPU processor is connected to the network port sequentially through the third ethernet control chip, each path of optical port communication circuit comprises a fourth ethernet control chip and an SFP optical module connector, and the CPU processor is connected to the SFP optical module connector through the fourth ethernet control chip.
Further, the model of the CPU processor is NXP QorIQ T4240.
Further, the models of the first ethernet control chip and the second ethernet control chip are both intel i 350.
Furthermore, the network port is an RJ45 network port, the model is XHanRun HR872230H, and a network transformer is arranged in the RJ45 network port.
Further, the third ethernet control chip and the fourth ethernet control chip are both Alaska88E1548 in model.
Further, the operating system is an kylin operating system or a Linux operating system.
The invention has the beneficial effects that:
the invention adopts the NXP QoriQ T4240 processor of the high-performance non-X86 and expands a plurality of network interfaces through the expansion board, thereby realizing the matching of the high-performance CPU processor and the plurality of network interfaces and the high-efficiency cooperative work, so that the CPU processor can not only quickly analyze and process data, but also completely meet the requirement of power consumption required by the simultaneous work of the plurality of network interfaces.
Drawings
FIG. 1: the invention relates to an architecture block diagram of a network situation perception acquisition device.
FIG. 2: the invention discloses a partial schematic diagram of a CPU processor.
FIG. 3: the invention discloses a partial schematic diagram of an Ethernet control chip of a main control board.
FIG. 4: the invention discloses a partial schematic diagram of an optical port communication circuit of a main control board.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
As shown in fig. 1, a network situation awareness acquisition device includes a main control board and 2 hard disks, where the main control board carries a CPU processor, 8 gigabit ethernet communication circuits, 4 optical interface communication circuits, a USB interface circuit, a PCIE interface, DDR3 memory banks, a NOR Flash memory, a NAND Flash memory, and a network interface expansion board.
One hard disk is a 256G/SSD solid state disk, an kylin operating system is preinstalled in the hard disk, and the hard disk has an almost complete linux function; the other hard disk is a 1TB enterprise-level data hard disk and is used for storing the acquired data; the onboard NAND Flash stores a simplified Linux operating system therein, and is decompressed to a DDR3 memory bank for operation when the device is started, so that the situation that the device cannot be started normally due to damage of a file system caused by mistaken deletion or abnormal shutdown of a user on the file system can be effectively avoided.
As shown in fig. 2, the CPU processor adopts an NXP QorIQ T4240 processor, a master frequency 1.5G, 8 cores, and 16 threads, and is mainly used for analyzing and processing data.
The DDR3 memory has the capacity of 16G, is electrically connected with the CPU processor, and is mainly used for loading a system and an application program.
The USB interface circuit is electrically connected with the CPU processor and is mainly used for device maintenance and internal expansion.
The NOR Flash memory has a capacity of 128MB, is electrically connected with the CPU, and is mainly used for storing a boot program and boot configuration information.
The capacity of the NAND Flash memory is 2GB, the NAND Flash memory is electrically connected with the CPU processor and is mainly used for storing a reduced version Linux operating system.
As shown in fig. 3, the 1 st to 4 th gigabit ethernet communication circuits share the same ethernet control chip, and the CPU processor is connected to the corresponding RJ45 network port through the ethernet control chip, and is connected to a collected object, such as a general-purpose host, through the RJ45 network port, so as to transmit data of the general-purpose host to the CPU processor.
The 5 th-8 th gigabit Ethernet communication circuits share the same Ethernet control chip, the CPU is connected to the corresponding RJ45 network port through the Ethernet control chip, and is connected to a collected object, such as industrial control equipment, through the RJ45 network port, so as to transmit data of the industrial control equipment to the CPU.
As shown in fig. 4, the 4 paths of optical interface communication circuits share the same ethernet control chip, and the CPU is connected to the corresponding SFP optical module connector through the ethernet control chip. And connecting the SFP optical module connector to a collected object, such as industrial control equipment, so as to transmit the data of the industrial control equipment to the CPU processor.
The Ethernet control chip is characterized in that the type of the Ethernet control chip is Alaska88E1548, the type of the RJ45 net port is XHanRunHR872230H, a network transformer is arranged in the RJ45 net port, the appearance layout is double-row double-seat (2x2), the SFP optical module connector is a standard component, and the appearance layout is double-row double-seat (2x 2).
The network port expansion board is connected to the main control board in an inserting mode through the PCIE interface, and the network port expansion board expands 8 paths of gigabit Ethernet communication circuits and 4 paths of optical port communication circuits.
The 1 st to 4 th paths of gigabit Ethernet communication circuits on the network port expansion board share the same Ethernet control chip, and the CPU is connected to the corresponding RJ45 network port through the PCIE interface and the Ethernet control chip in sequence. The 5 th-8 th paths of gigabit Ethernet communication circuits on the network port expansion board share the same Ethernet control chip, and the CPU is connected to the corresponding RJ45 network port through the PCIE interface and the Ethernet control chip in sequence. The data of the safety device is transmitted to a CPU processor by connecting to a collected object, such as a safety device, through an RJ45 network port.
The 4 paths of optical port communication circuits on the network port expansion board share the same Ethernet control chip, and the CPU is connected to the corresponding SFP optical module connectors through the PCIE interface and the Ethernet control chip in sequence. The SFP optical module connector is connected to the collected object, such as the isolation device, so as to transmit the data of the isolation device to the CPU processor.
The Ethernet control chip on the network port expansion board is of an Intel I350 model, the RJ45 network port on the network port expansion board is of an XHanRun HR872230H model, the network transformer is arranged in the RJ45 network port, and the appearance layout is double-row double-seat (2x 2). The SFP optical module connector is a standard component, and the appearance layout is double-row double-seat (2x 2).
The following briefly introduces the working principle of the present invention:
after the device is powered on, a bootstrap program pre-stored in a NOR Flash memory is loaded after basic hardware detection, the device is further self-checked according to a preset bootstrap flow, an operating system required to be started by a user is loaded, and meanwhile, the control right is given to the operating system. After the system is loaded and started, an application program pre-installed in the system is automatically operated, data of connected equipment is collected through each path of gigabit Ethernet communication circuit and optical interface communication circuit, monitoring sampling analysis is carried out, and finally analysis results and abnormity are reported to the master station equipment.
Finally, it should be noted that: the above embodiments are only used to illustrate the present invention and do not limit the technical solutions described in the present invention; thus, while the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted; all such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and protected by the following claims.

Claims (8)

1. The utility model provides a network situation perception collection system, includes main control board and hard disk, operating system, its characterized in that have been pre-installed in the hard disk: the main control board is provided with a CPU processor, a multi-path gigabit Ethernet communication circuit, a multi-path optical port communication circuit, a USB interface circuit, a PCIE interface, a DDR3 memory bank, a NOR Flash memory, a NAND Flash memory and a network port expansion board on board, and the network port expansion board is electrically connected with the CPU processor through the PCIE interface; the gigabit Ethernet communication circuit, the optical port communication circuit, the USB interface circuit, the DDR3 memory bank, the NOR Flash memory and the NAND Flash memory are all electrically connected with the CPU.
2. The network situational awareness acquisition device of claim 1, wherein: the network port expansion board is provided with a plurality of paths of gigabit Ethernet communication circuits and a plurality of paths of optical port communication circuits, each path of gigabit Ethernet communication circuit comprises a first Ethernet control chip and a network port, the CPU is connected with the network port through the first Ethernet control chip, each path of optical port communication circuit comprises a second Ethernet control chip and an SFP optical module connector, and the CPU is connected with the SFP optical module connector through the second Ethernet control chip.
3. The network situational awareness acquisition device of claim 1, wherein: each path of gigabit Ethernet communication circuit comprises a third Ethernet control chip and a network port, the CPU processor is connected with the network port sequentially through the third Ethernet control chip, each path of optical port communication circuit comprises a fourth Ethernet control chip and an SFP optical module connector, and the CPU processor is connected with the SFP optical module connector through the fourth Ethernet control chip.
4. The network situational awareness acquisition device of claim 1, wherein: the model of the CPU processor is NXP QoriQ T4240.
5. The network situational awareness collection system of claim 2, wherein: the first Ethernet control chip and the second Ethernet control chip are both of Intel I350 type.
6. The network situational awareness collection system of claim 2 or 3, wherein: the network port is an RJ45 network port, the model is XHanRun HR872230H, and a network transformer is arranged in the RJ45 network port.
7. The network situational awareness collection system of claim 3, wherein: the third Ethernet control chip and the fourth Ethernet control chip are both Alaska88E1548 in model.
8. The network situational awareness acquisition device of claim 1, wherein: the operating system is an kylin operating system or a Linux operating system.
CN201910981730.7A 2019-10-16 2019-10-16 Network situation perception acquisition device Pending CN111565126A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115442351A (en) * 2022-08-06 2022-12-06 中国船舶重工集团公司第七一五研究所 High-speed RS-422 serial port communication module based on FPGA and CPU

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101188057A (en) * 2007-12-14 2008-05-28 哈尔滨工程大学 ARM-based flat wheel detection and control system
US20120209986A1 (en) * 2011-02-15 2012-08-16 Shesha Shah Social Net Advocacy Process and Architecture
CN203590247U (en) * 2013-11-18 2014-05-07 成都比善科技开发有限公司 Smart grid network message acquisition device
CN106547708A (en) * 2016-11-01 2017-03-29 济南浪潮高新科技投资发展有限公司 A kind of distributed storage module based on ARM

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101188057A (en) * 2007-12-14 2008-05-28 哈尔滨工程大学 ARM-based flat wheel detection and control system
US20120209986A1 (en) * 2011-02-15 2012-08-16 Shesha Shah Social Net Advocacy Process and Architecture
CN203590247U (en) * 2013-11-18 2014-05-07 成都比善科技开发有限公司 Smart grid network message acquisition device
CN106547708A (en) * 2016-11-01 2017-03-29 济南浪潮高新科技投资发展有限公司 A kind of distributed storage module based on ARM

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115442351A (en) * 2022-08-06 2022-12-06 中国船舶重工集团公司第七一五研究所 High-speed RS-422 serial port communication module based on FPGA and CPU

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Application publication date: 20200821