CN101727329B - Mainboard system, storage device for starting same and connector - Google Patents
Mainboard system, storage device for starting same and connector Download PDFInfo
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- CN101727329B CN101727329B CN 200810170041 CN200810170041A CN101727329B CN 101727329 B CN101727329 B CN 101727329B CN 200810170041 CN200810170041 CN 200810170041 CN 200810170041 A CN200810170041 A CN 200810170041A CN 101727329 B CN101727329 B CN 101727329B
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Abstract
The invention provides a mainboard system, a storage device for starting the same and a connector. The mainboard system comprises a central processing unit, a control chipset and an interface connector, wherein the control chipset is electrically connected to the central processing unit; the interface connector is electrically connected to the control chipset and provided with a power-on supervisory program interface unit and a peripheral storage device interface unit; the power-on supervisory program interface unit is electrically connected to the control chipset and used for connecting a system firmware read-only storage; and when the mainboard system starts the power, the central processing unit transmits a read-only storage retrieval cycle to the control chipset and acquires a power-on program from the system firmware read-only storage through the power-on supervisory program interface unit. Thus, the system firmware read-only storage can be conveniently updated and maintained.
Description
Technical field
The present invention relates to a kind of mainboard system, particularly relate to a kind of mainboard system that can start by removable system firmware ROM (read-only memory), have the flash memory of this system firmware ROM (read-only memory) and connect the connector of this mainboard system and flash memory.
Background technology
At personal computer (Personal Computer, PC) in the process that starts, start (booting) program (for example, basic input/output system (Basic Input/Output System, BIOS)) can be responsible for the responsibility of initiating hardware, detection hardware function and guiding operating system.In general, boot program can be stored in the storer that content can not be lost after an outage, and this storer with boot program is commonly referred to as system firmware (System Firmware) ROM (read-only memory) (Read Only Memory, ROM).When the personal computer system crosses electricity or be reset (reset), CPU (central processing unit) (CentralProcessing Unit, CPU) need the address of article one instruction of execution can be positioned in the system firmware storer, allow thus the start program begin to carry out.
Specifically, when the electric power starting of personal computer, the part instruction of CPU in can the executive system firmware ROM, and with chipset and primary memory (for example, dynamic RAM (Dynamic Random Access Memory, DRAM)) initialization.Afterwards, CPU can be decompressed to remaining start-up command the primary memory of personal computer from the system firmware ROM (read-only memory), and the boot program after carrying out from primary memory.
The system firmware ROM (read-only memory) is to be configured in regularly on the mainboard system of personal computer at present, and be connected in the South Bridge chip of chipset by low pin position (Low Pin Count) bus or serial peripheral interface (Seria lPeripheral Interface, SPI) bus.Traditionally, the system firmware ROM (read-only memory) is to implement with ROM (read-only memory), is therefore generally to be modified.Yet, because boot program (for example, BIOS) size and complexity constantly increase in time, and the renewal speed of hardware is accelerated, make boot program also must constantly update to support new hardware, so erasable (smearing) is removed and programmable read only memory (Erasable Programmable Read OnlyMemory, EPROM) is widely used in implementation system firmware ROM (read-only memory) to allow the user can upgrade easily boot program.Although, can allow the user upgrade boot program along with the renewal of hardware with erasable and programmable read only memory implementation system firmware ROM (read-only memory), yet erasable and programmable read only memory is still and is configured in regularly on mainboard system in the prior art, therefore when its capacity can't store the boot program that upgrades, just can't continue to upgrade new boot program.Therefore, have and need the mainboard system framework that development one cover can more convenient replacing system firmware ROM (read-only memory).
Summary of the invention
The invention provides a kind of mainboard system, it can come access removable system firmware ROM (read-only memory) to upgrade and maintenance system firmware ROM and boot program thereof easily by the industry-standard interface card.
The invention provides a kind of flash memory, it can provide above-mentioned mainboard system start required system firmware ROM (read-only memory) removably, upgrades and maintenance system firmware ROM and boot program thereof easily thus.
The invention provides a kind of mainboard system, it comprises CPU (central processing unit), control chip group and interface connector.The control chip group is to be electrically connected to CPU (central processing unit).Interface connector is to be electrically connected so far control chip group and tool power-on management routine interface unit and peripheral storage device interface unit, and wherein power-on management routine interface unit is electrically connected to the control chip group and in order to the connected system firmware ROM.When mainboard system started power supply, CPU (central processing unit) can send ROM (read-only memory) acquisition cycle to this control chip group, and obtained boot program by power-on management routine interface unit from the system firmware ROM (read-only memory).
In one embodiment of this invention, above-mentioned power-on management routine interface unit comprises a serial peripheral interface (serial Peripheral Interface), an Industry Standard Architecture (Industry StandardArchitecture, ISA) or one low pin position (Low Pin Count, LPC).
In one embodiment of this invention, above-mentioned interface connector is that PCI Express type connector and above-mentioned peripheral storage device interface unit are PCI Express interface bus.
In one embodiment of this invention, above-mentioned control chip group comprises the north bridge chips that is electrically connected to CPU (central processing unit) and the South Bridge chip that is electrically connected to north bridge chips.
In one embodiment of this invention, above-mentioned interface connector is that PCI Express connector and above-mentioned interface bus are PCI Express interface bus.
In one embodiment of this invention, above-mentioned PCI Express interface bus is electrically connected to north bridge chips.
In one embodiment of this invention, above-mentioned PCI Express interface bus is electrically connected to South Bridge chip.
In one embodiment of this invention, above-mentioned PCI Express type connector comprises PCI Express interface card electromechanical equipment (Card ElectroMechanical, CEM) connector, PCI Express Mini Interface Card electromechanical equipment (Mini-CEM) connector or high-speed interface card (Express Card) connector.
In one embodiment of this invention, above-mentioned boot program comprises Basic Input or Output System (BIOS) (Basic Input/Output System) or extensible firmware interface (Extensible FirmwareInterface).
In one embodiment of this invention, above-mentioned mainboard system also comprises flash memory, and wherein this flash memory is to be electrically connected to removedly PCI Express type connector and the system firmware ROM (read-only memory) is to be configured on flash memory.
in one embodiment of this invention, above-mentioned flash memory comprises PCI Express type card connector, flash controller and flash chip, PCI Express type card connector is to be electrically connected to removedly above-mentioned PCI Express type connector, flash controller is to be electrically connected to PCI Express type card connector and to be electrically connected to above-mentioned control chip group via above-mentioned PCI Express interface bus, flash chip is to be electrically connected to flash controller, wherein the system firmware ROM (read-only memory) is electrically connected to PCI Express type card connector and is electrically connected to above-mentioned control chip group via the serial peripheral interface bus.
The invention provides a kind of flash memory, comprise card connector, flash controller, flash chip and system firmware ROM (read-only memory).Card connector is in order to connect mainboard system, and wherein PCI Express type card connector has power-on management routine interface unit and peripheral storage device interface unit.Flash controller is electrically connected to the peripheral storage device interface unit of card connector.Flash chip is electrically connected to flash controller.The system firmware ROM (read-only memory) is electrically connected to the power-on management routine interface unit of card connector, and wherein the system firmware ROM (read-only memory) has to start the boot program of above-mentioned mainboard system.
In one embodiment of this invention, above-mentioned power-on management routine interface unit comprises serial peripheral interface (serial Peripheral Interface), Industry Standard Architecture (Industry StandardArchitecture, ISA) or low pin position (Low Pin Count, LPC).
In one embodiment of this invention, above-mentioned boot program comprises Basic Input or Output System (BIOS) (Basic Input/Output System) or extensible firmware interface (Extensible FirmwareInterface).
The invention provides a kind of connector, it comprises peripheral storage device interface unit and power-on management routine interface unit, wherein peripheral storage device interface unit in order to be electrically connected control chip and storage device electrically and power-on management routine interface unit in order to being connected control chip group and system firmware ROM (read-only memory), and this system firmware ROM (read-only memory) is to be configured on storage device.
In one embodiment of this invention, above-mentioned peripheral storage device interface unit is a PCIExpress interface bus, the attached extension technology of a parallel high-order (Parallel Advanced TechnologyAttachment, PATA) interface bus or the attached extension technology of a tandem high-order (Serial AdvancedTechnology Attachment, SATA) interface bus.
The present invention is connected to mainboard system because adopting removable system firmware ROM (read-only memory) and linking by industry-standard interface, therefore can effectively upgrade with the maintenance system firmware ROM in boot program.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 illustrates the summary calcspar of mainboard system according to the embodiment of the present invention.
Fig. 2 illustrates the pin schematic diagram of the PCI ExpressMiniCEM golden finger signal of PCI Express type connector according to the embodiment of the present invention.
Fig. 3 illustrates the summary calcspar of the example external device of tool PCI Express type card connector according to one embodiment of the invention
The reference numeral explanation
100: mainboard system
110: CPU (central processing unit)
120: the control chip group
122: north bridge chips
124: South Bridge chip
130:PCI Express type connector
130a: power-on management routine interface unit
130b: peripheral storage device interface unit
150: the system firmware ROM (read-only memory)
300: flash memory
302:PCI Express type card connector
304: flash controller
306: flash chip
Embodiment
Fig. 1 is the summary calcspar of the mainboard system that illustrates according to the embodiment of the present invention.
Please refer to Fig. 1, motherboard (Mother Board) system 100 is configured in computing machine (not illustrating) in order to engage the associated component of this computing machine.Motherboard (Mother Board) system 100 comprises CPU (central processing unit) (Central Processing Unit, CPU) 110, control chip group 120 and interface connector 130.
CPU (central processing unit) 110 is in order to explain that instruction performed on mainboard system 100 is with the running of control linkage to the assembly of mainboard system 100.
South Bridge chip 124 is electrically connected to north bridge chips 122, and in order to processing low speed signal, and contact by north bridge chips 122 and CPU (central processing unit) 110.For example, these low speed signals comprise the communication between peripheral equipment interface, multimedia controller and communication interface.For example, South Bridge chip 124 has peripheral assembly interconnect (Peripheral Component Interconnect, PCI) controller, attached (the Advanced Technology Attachment of advanced technology, ATA) functions such as controller, USB (universal serial bus) (Universal Serial Bus, USB) controller, network controller, sound effect control device.
In the present embodiment, PCI Express type connector 130 comprises a power-on management routine interface (Boot Loader Interface) unit 130a and a peripheral storage device interface unit 130b.
Power-on management routine interface unit 130a is electrically connected to South Bridge chip 124 and in order to allow the bus of CPU (central processing unit) 110 recognition system firmware ROMs 150.that is to say, when the computer starting power supply, CPU (central processing unit) 110 can be sent ROM (read-only memory) acquisition cycle (ROM FetchCycle) and obtain first start-up command of boot program in system firmware ROM (read-only memory) 150 via South Bridge chip 124, and power-on management routine interface unit 130a is exactly the mechanism that mainboard system 100 can recognition system firmware ROM 150 in the design of current chip group, therefore the ROM (read-only memory) acquisition cycle can successfully be sent to the system firmware ROM (read-only memory) that is connected with South Bridge chip 124 by power-on management routine interface unit 130a to capture boot program.In the present embodiment, power-on management routine interface unit 130a is serial peripheral interface (Serial Peripheral Interface, SPI) bus, yet it must be appreciated and the invention is not restricted to this, power-on management routine interface 130a can also be the pin position that only has serial peripheral interface bus necessity in another embodiment of the present invention, also or Industry Standard Architecture (Industry Standard Architecture, ISA), low pin position (Low PinCount, LPC) or other suitable interfaces in order to the transmission system firmware.
In the system firmware ROM (read-only memory), boot program is Basic Input or Output System (BIOS) (Basic Input/Output System) in the present embodiment.In addition, in another embodiment of the present invention, the boot program of system firmware ROM (read-only memory) can also be extensible firmware interface (Extensible FirmwareInterface).
Periphery storage device interface unit 130b is electrically connected to South Bridge chip 124.In the present embodiment peripheral storage device interface unit 130b be PCI Express interface bus so that interface connector 130 (namely, PCI Express type connector 130) can connect the peripheral equipment that is compatible to PCI Express interface, storage device for example, in another embodiment, peripheral storage device interface unit 130b is the pin position that only has PCI Express interface bus necessity.The relevant specification of PCI Express interface those skilled in the art in the invention for this reason can be understood easily, does not describe in detail at this.
Particularly, for keeping the not pin of any function of tool, therefore being compatible in the present embodiment in the PCI Express type connector 130 of MiniCEM pin 45,47,49 and 51, can to arrange (lay out) be power-on management routine interface unit 130a due to pin (pin) 45,47,49 in the specification of Mini CEM and 51.
Fig. 2 illustrates the pin schematic diagram of the PCI ExpressMniCEM golden finger signal of PCI Express type connector 130 according to the embodiment of the present invention.
Please refer to Fig. 2, reservation pin 45,47,49 and 51 in PCI Express MiniCEM golden finger signal is SPISI pin, SPISO pin, SPICLK pin and the SPICS# pin that is arranged to respectively serial peripheral interface in the present embodiment, and other PCI Express MiniCEM golden finger signals are PCI Express interface pins.The base this, be the apparent size that belongs to MiniCEM in embodiments of the present invention on PCI Express type connector 130 entities, can connect the peripheral device with Mini CEM thus, PCI Express type connector 130 can receive and transmit the signal that is compatible to PCI Express interface standard and the signal that is compatible to the serial peripheral interface standard on signal transmits simultaneously.
In addition, though be not illustrated in Fig. 1, but mainboard system 100 also can comprise other expansion slots (for example, PCI, I SA, USB, SATA connector etc.) and be connected to South Bridge chip 124 or north bridge chips 122 to connect display card, infrared module, bluetooth module or networking card etc.
Based on above-mentioned, system firmware ROM (read-only memory) 150 is to be connected to mainboard system 100 by the power-on management routine interface unit 130a in PCI Express type connector 130 in the present embodiment, therefore on the configurable external device using PCI Express interface of system firmware ROM (read-only memory) 150, be connected to removedly mainboard system 100 through peripheral device thus.That is to say, system firmware ROM (read-only memory) 150 is configurable has PCI Express type card connector (namely, the male joint of PCI Express interface) pass through PCI Express type connector 130 (namely on external device, the female joint of PCIExpress interface) be connected to South Bridge chip 124, identify system firmware ROM (read-only memory) 150 with the acquisition boot program (for example, BIOS) and make the ROM (read-only memory) acquisition cycle can waltz through South Bridge chip 124 with power-on management routine interface unit 130a.Describe the example of this external device in detail below with reference to Fig. 3.
Fig. 3 illustrates the summary calcspar of the example external device with PCI Express type card connector according to one embodiment of the invention, wherein this external device is a flash memory.
Please refer to Fig. 3, flash memory 300 comprises card connector 302, flash controller 304 and flash chip 306, and the system firmware ROM (read-only memory) 150 in Fig. 1 is configured on this flash memory 300.
particularly, PCI Express type card connector 302 also has power-on management routine interface unit 302a and peripheral storage device interface unit 302b, wherein power-on management routine interface unit 302a is electrically connected in order to the peripheral storage device interface unit 130b with PCI Express type connector 130 in order to power-on management routine interface unit 130a electric connection and peripheral storage device interface unit 302b with PCI Express type connector 130, therefore power-on management routine interface unit 302a corresponds to the serial peripheral interface bus in embodiments of the present invention, and peripheral storage device interface unit 302b corresponds to PCI Express interface bus.The arrangement of the pin of PCI Express type card connector 302 is to be same as shown in Figure 2ly, is not described in detail at this.
System firmware ROM (read-only memory) 150 is electrically connected to the power-on management routine interface unit 302a of PCI Express type card connector 302.As mentioned above, the system firmware ROM (read-only memory) has to start the boot program of mainboard system 100.
Under as Fig. 1 and framework shown in Figure 3, when the power supply that is connected to the computing machine of mainboard system 100 and configure host plate system 100 by PCI Express type card connector 302 and PCI Express type connector 130 when flash memory 300 is activated, CPU (central processing unit) 110 can send the ROM (read-only memory) acquisition cycle (readonly memory fetch cycle) to chipset (that is, north bridge chips 122 and South Bridge chip 124).This ROM (read-only memory) acquisition cycle can be sent to north bridge chips 122 by the bus between CPU (central processing unit) 110 and north bridge chips 122.Then, north bridge chips 122 can be sent to South Bridge chip 124 by the bus between north bridge chips 122 and South Bridge chip 124.Then, South Bridge chip 124 can recognition start-up hypervisor interfaces unit 130a and power-on management routine interface unit 302a and obtain first start-up command of boot program and send CPU (central processing unit) 110 to from system firmware ROM (read-only memory) 150.Then, CPU (central processing unit) 110 can repeat to send the ROM (read-only memory) acquisition cycle according to above-mentioned path and obtain all boot programs, and the boot program that execution afterwards captures is to complete opening computer.
In general, mainboard system 00 can comprise also that a primary memory (not illustrating) is connected to north bridge chips 122, because primary memory is that speed is faster than the dynamic RAM of ROM (read-only memory), therefore in this example, after CPU (central processing unit) 110 can capture from the system firmware ROM (read-only memory) and come initialize main memory with the boot program of carrying out some, the follow-up boot program of obtaining is stored in primary memory and from then on carries out in primary memory, promote thus the speed of carrying out boot program.
It is worth mentioning that, be to be electrically connected to South Bridge chip 124 according to the PCI Express type connector 130 of the mainboard system 100 of the present embodiment, so flash controller 304 is all to receive steering order from South Bridge chip 124 with system firmware ROM (read-only memory) 150.Yet, because north bridge chips 122 also can be identified PCI Express interface, therefore also the power-on management routine interface unit 130a of PCI Express type connector 130 can be electrically connected to South Bridge chip 124 and the circuit layout mode that peripheral storage device interface unit 130b is electrically connected to north bridge chips 122 is come implementation in another embodiment of the present invention.In this example, above-mentioned flash controller 304 is to receive steering order from north bridge chips 122, and system firmware ROM (read-only memory) 150 is to receive steering order from South Bridge chip 124.
In addition, though the embodiment of the present invention describe with PCI Express interface standard, yet the invention is not restricted to this, any suitable industry standard connector, as PATA, SATA, SCSI etc.., all can be applicable to the present invention.
In sum, system firmware ROM (read-only memory) of the present invention is to be configured on the external device that is connected to removedly mainboard system, therefore the user can change system firmware ROM (read-only memory) or maintenance system firmware ROM by disassembling this external device easily, can make thus the renewal elasticity more of the system firmware of computer system.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; those skilled in the art can do a little change and retouching under the future that does not break away from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (11)
1. mainboard system comprises:
One CPU (central processing unit);
One control chip group is electrically connected to this CPU (central processing unit); And
One PCI Express type connector, be electrically connected to this chipset and have a power-on management routine interface unit and a peripheral storage device interface unit, wherein this power-on management routine interface unit is electrically connected to this control chip group and in order to connect a system firmware ROM (read-only memory)
Should periphery storage device interface unit be wherein a PCI Express interface bus,
Wherein this CPU (central processing unit) sends ROM (read-only memory) acquisition cycle to this control chip group, and obtains a boot program by this power-on management routine interface unit from this system firmware ROM (read-only memory), and wherein this PCI Express type connector comprises:
One first pin is in order to receive an input signal of a corresponding serial peripheral interface standard;
One second pin is in order to receive a output signal that should the serial peripheral interface standard;
One the 3rd pin is in order to receive a frenquency signal that should the serial peripheral interface standard; And
One the 4th pin, in order to receiving a chip selection signal that should the serial peripheral interface standard,
Wherein this power-on management routine interface unit is comprised of this first pin, this second pin, the 3rd pin and the 4th pin.
2. mainboard system as claimed in claim 1, wherein this control chip group comprises:
One north bridge chips is electrically connected to this CPU (central processing unit); And
One South Bridge chip is electrically connected to this north bridge chips.
3. mainboard system as claimed in claim 2, wherein this PCI Express interface bus is electrically connected to this north bridge chips.
4. mainboard system as claimed in claim 2, wherein this PCI Express interface bus is electrically connected to this South Bridge chip.
5. mainboard system as claimed in claim 1, wherein this PCI Express type connector comprises a PCI Express interface card electromechanical equipment connector, a PCI Express Mini Interface Card electromechanical equipment connector or a high-speed interface card connector.
6. mainboard system as claimed in claim 1, wherein this boot program comprises a Basic Input or Output System (BIOS) or an extensible firmware interface.
7. mainboard system as claimed in claim 1, also comprise a flash memory, and wherein this flash memory is to be electrically connected to removedly this PCI Express type connector and this system firmware ROM (read-only memory) is configured on this flash memory.
8. mainboard system as claimed in claim 7, wherein this flash memory comprises:
One PCI Express type card connector is electrically connected to this PCI Express type connector removedly;
One flash controller is electrically connected to this PCI Express type card connector and is electrically connected to this control chip group via this PCIExpress interface bus; And
One flash chip is electrically connected to this flash controller,
Wherein this system firmware ROM (read-only memory) is electrically connected to this PCI Express type card connector and is electrically connected to this control chip group via this power-on management routine interface unit.
9. flash memory comprises:
One PCI Express type card connector, in order to connect a mainboard system, wherein this PCIExpress type card connector has a power-on management routine interface unit and a peripheral storage device interface unit, should periphery storage device interface unit be wherein a PCI Express interface bus;
One flash controller is electrically connected to this periphery storage device interface unit of this card connector;
One flash chip is electrically connected to this flash controller; And
One system firmware ROM (read-only memory) is electrically connected to this power-on management routine interface unit of this card connector, and wherein this system firmware ROM (read-only memory) has to start a boot program of this mainboard system, and wherein this PCI Express type connector comprises:
One first pin is in order to receive an input signal of a corresponding serial peripheral interface standard;
One second pin is in order to receive a output signal that should the serial peripheral interface standard;
One the 3rd pin is in order to receive a frenquency signal that should the serial peripheral interface standard; And
One the 4th pin, in order to receiving a chip selection signal that should the serial peripheral interface standard,
Wherein this power-on management routine interface unit is comprised of this first pin, this second pin, the 3rd pin and the 4th pin.
10. flash memory as claimed in claim 9, wherein this PCI Express type card connector comprises a PCI Express interface card electromechanical equipment connector, a PCI Express Mini Interface Card electromechanical equipment connector or a high-speed interface card connector.
11. flash memory as claimed in claim 9, wherein this boot program comprises a Basic Input or Output System (BIOS) or an extensible firmware interface.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810170041 CN101727329B (en) | 2008-10-15 | 2008-10-15 | Mainboard system, storage device for starting same and connector |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810170041 CN101727329B (en) | 2008-10-15 | 2008-10-15 | Mainboard system, storage device for starting same and connector |
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| CN101727329A CN101727329A (en) | 2010-06-09 |
| CN101727329B true CN101727329B (en) | 2013-06-12 |
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| CN103631608A (en) * | 2012-08-21 | 2014-03-12 | 瑞昱半导体股份有限公司 | Starting-up guide device and starting-up guide method thereof |
| CN106293672A (en) * | 2015-06-05 | 2017-01-04 | 昆达电脑科技(昆山)有限公司 | Starting-up method |
| CN111766797A (en) * | 2019-04-02 | 2020-10-13 | 海盗船存储器公司 | Microcontroller, memory module and method for updating firmware of microcontroller |
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