CN111556807A - 用于3d ic应用的可激光释放粘结材料 - Google Patents

用于3d ic应用的可激光释放粘结材料 Download PDF

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CN111556807A
CN111556807A CN201880082753.8A CN201880082753A CN111556807A CN 111556807 A CN111556807 A CN 111556807A CN 201880082753 A CN201880082753 A CN 201880082753A CN 111556807 A CN111556807 A CN 111556807A
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diglycidyl ether
layer
substrate
ether
group
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CN111556807B (zh
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R·普利吉达
吴起
刘晓
白东顺
B·黄
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Brewer Science Inc
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Brewer Science Inc
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Abstract

提供了新型的基于热塑性聚羟基醚的组合物，其用作用于暂时性粘结和激光脱粘工艺的可激光释放的组合物。本发明组合物可以使用各种UV激光脱粘，几乎不留残渣。由这些组合物形成的层具有良好的热稳定性，并且可溶于通常使用的有机溶剂(例如环戊酮)中。该组合物还可以用作RDL形成的堆积层。

Description

用于3D IC应用的可激光释放粘结材料
发明背景
相关申请
本申请要求于2017年12月22日提交的、题为“用于3D IC应用的可激光释放粘结材料”(LASER-RELASEABLE BONDING MATERIALS FOR 3-D IC APPLICATIONS)的美国临时专利申请系列号62/609,426的优先权，该文的全部内容通过引用纳入本文。
发明领域
本发明涉及可激光释放组合物，其用于用作暂时性晶片粘结工艺中的粘结组合物，或者用作在再分布层形成期间用作堆积层。
相关技术说明
临时性晶片粘结(TWB)通常涉及通过聚合粘结材料将器件晶片或微电子基材附着至载体晶片或基材的方法。在粘结后，器件晶片通常变薄至小于50μm，然后径向加工以在其背侧产生硅穿孔(through-silicon vias，TSV)、再分布层、粘结垫和其它电路特征件在背面加工过程中载体晶片支撑脆弱的器件晶片，由晶片操作和转移步骤产生的机械冲击和强机械作用力，如在用于将器件晶片变薄的晶片背面研磨过程中施加的力，所述背面加工可能需要在环境温度和高温(>250℃) 之间的重复循环。当所有的加工完成时，器件晶片通常附连在薄膜框上，然后从所述载体晶片上分离或脱粘，并在进一步操作之前进行清洁。
大部分TWB工艺在器件晶片和载体晶片之间使用一个或多个层。对于两层体系的示例，所述第一层是聚合物粘结材料。其本质可以是热塑性、热固性或光固化的。聚合粘结材料层通常厚10μm至120μm，更常见为厚50μm至100μm。第二层相对薄，通常小于2μm，并且存在以使得在加工之后能够容易地分离粘结的晶片对。薄层响应来自激光光源或其他光源的辐照，这使得所述层本身分解或相邻的聚合物粘结材料分解，导致结构中粘结完整性损失，使其无需施加机械作用力而分离。
现在，市场上的大部分暂时性粘结/脱粘平台聚焦多层结构，例如包括暂时性粘结层和释放层的双层系统。各层的涂覆和烘烤的多个步骤导致经营成本增加以及整个工艺的产量下降。不同的是，通过使用同时用作暂时性结合层和激光释放层的单一材料，可以实现成本的显著降低和产量的提高。
激光诱导的释放正成为一种流行的脱粘模式，并且材料可用于在紫外(例如248nm、308nm和355nm)到近红外(例如1064nm)范围的激光波长下工作。激光释放技术即使在大型板上，在释放过程中仍提供了高产量和低应力，高效的薄基材处理，并且易于施加。激光释放技术可在封装领域的不同应用中使用，例如临时粘结、扇出型晶圆级封装、层压、使用硅穿孔(TSV)的2.5D/3D集成、系统级封装(system-in-packaging，SiP)、封装体层叠(package-on-package，PoP) 和其它异构集成基础设施。
发明概述
本发明广泛涉及暂时性粘结方法、再分布层形成方法以及通过这些方法形成的结构。在一个实施方式中，暂时性粘结方法包括：提供堆叠体，所述堆叠体包括第一基材、粘结层和第二基材。第一基材具有背表面和前表面。粘结层与前表面相邻，并且包括聚羟基醚。第二基材具有与粘结层相邻的第一表面。粘结层暴露于激光能量，以促进第一基材和第二基材的分离。
在其它实施方式中，本发明提供一种微电子结构，其包括具有背表面和前表面的第一基材。粘结层与前表面相邻，并且粘结层包括聚羟基醚。具有第一表面的第二基材与粘结层相邻，并且前表面和第一表面中的至少一个是器件表面。
在另一实施方式中，本发明方法包括在基材表面上形成堆积层。堆积层包括聚羟基醚，并且具有远离基材表面的上表面。第一再分配层形成于上表面上，并且，一个或多个附加的再分布层任选地形成于第一再分布层上。
在另一实施方式中，微电子结构包括具有表面的基材。堆积层在基材表面上，并且堆积层包括聚羟基醚，并且具有远离基材表面的上表面。在上表面上具有第一再分布层。
附图简要说明
附图(图)1是显示本发明优选暂时性粘结方法的截面示意图；
图2是显示图1实施方式变形的截面示意图；
图3是显示本发明再分布层形成的示意图；
图4是是描述实施例2中测试的聚合物1的TGA(空气中)的图；
图5是是描述实施例2中测试的聚合物1的TGA(氮气中)的图；
图6是实施例4中测试的由配方1产生的粘结线的SUSS Chrocdail图；和
图7是如实施例6中所述在308nm脱粘的空白器件。
发明详述
本发明涉及用作暂时性粘结的新型组合物或堆积组合物，以及使用这些组合物的方法。
暂时性粘结或堆积聚合物以及组合物
1.聚羟基醚
在本发明中使用的组合物包括聚羟基醚。优选的聚羟基醚可以是聚合的或低聚的，并且优选的循环单元包括：含二羟基染料和二缩水甘油醚。
优选的含二羟基染料包括存在于染料上的一个或多个带有两个羟基(-OH) 的芳族部分。染料或生色团应吸收约300nm至约400nm波长的光，从而将光吸收度性质赋予聚羟基醚。优选的该染料包括选自下组的那些：4,4'-二羟基二苯甲酮、二羟基查尔酮染料、4-[(2-苯基亚肼基)甲基]间苯二酚、二羟基偶氮苯、二羟基蒽醌、2,2'-亚甲基双[6-(苯并三唑-2-基)-4-叔辛基苯酚]、姜黄素、姜黄素衍生物及它们的组合。
优选的二缩水甘油醚包含具有两个环氧化物环的环族(优选为C3至C8)、芳族(优选为C6至C12)或脂族(优选为C2至C10)部分，通常这些环氧化物连接至与环族或芳族部分键合的氧原子。优选的二缩水甘油醚包括选自下组的那些：双酚A二缩水甘油醚、双酚F二缩水甘油醚、1,4-环己烷二甲醇二缩水甘油醚、间苯二酚二缩水甘油醚、双酚A丙氧基化二缩水甘油醚、乙二醇二缩水甘油醚、1,4- 环己二甲醇二缩水甘油醚、甘油二缩水甘油醚、1,4-丁二醇二缩水甘油醚、新戊二醇二缩水甘油醚、1,3-丁二醇二缩水甘油醚、1,3-双(3-环氧丙氧基丙基)四甲基二硅氧烷及它们的组合。
通过使含二羟基染料和二缩水甘油醚在溶剂体系中并在催化剂的存在下在升高的温度下反应来合成聚羟基醚。优选以一定水平提供单体以使得含二羟基染料与二缩水甘油醚的摩尔比为约10:90至90:10，更优选为约30:70至约70:30，甚至更优选为40:60至约60:40。
在聚合期间使用的合适的催化剂包括选自下组的那些：溴化乙基三苯基鏻和氢氧化四甲铵。基于被视为100重量％的单体固体总重量，通常存在的催化剂的量为约1重量％至约5重量％的催化剂，优选约2重量％至约3重量％的催化剂。
在聚合体系中使用的合适溶剂包括选自下组的那些：环戊酮、环己酮、γ-丁内酯(GBL)、四氢糠醇、苯甲醇、二甲亚砜(DMSO)、N-甲基-2-吡咯烷酮(NMP)、以及它们的混合物。基于被视为100重量％的组合物总重量，聚合期间通常存在的溶剂水平为约40重量％至约90重量％的溶剂，并且优选约50重量％至约80重量％的溶剂，并且余量为固体。
聚合反应在约70℃至约150℃、更优选约130℃至约150℃的温度下进行约3 小时至约24小时、更优选约6小时至约15小时、更优选约12小时的时间。粗产物在醇中进行沉淀并且在真空下进行干燥。所得的聚羟基醚的重均分子量优选为约 1,000道尔顿至约100,000道尔顿，优选约约10,000道尔顿至约50,000道尔顿，更优选约20,000道尔顿至40,000道尔顿。
2.聚羟基醚组合物
在本发明中使用的粘结或堆积组合物通过将聚羟基醚简单溶解在溶剂体系中形成。合适溶剂包括选自下组的那些：环戊酮、环己酮、γ-丁内酯(GBL)、四氢糠醇、苯甲醇、二甲亚砜(DMSO),、N-甲基-2-吡咯烷酮(NMP)、以及它们的混合物。优选地，溶解允许在搅拌的同时，在约24小时的过程中进行，获得均匀溶液。溶液优选在使用前进行过滤。
基于被视为100重量％的组合物的总重量，最终的激光可释放粘结或堆积组合物优选含有约5重量％至约50重量％的固体、更优选约10重量％至约40重量％的固体，更优选约20重量％至约30重量％的固体。基于被视为100重量％的组合物中固体的总重量，这些固体通常为100重量％的聚羟基醚，然而，在一些示例中，其可以是约95重量％至约100重量％的聚羟基醚，更优选约98重量％至约100重量％的聚羟基醚。
在一个实施方式中，所述组合物基本不含交联剂。也就是说，基于被视为100 重量％的组合物的总重量，组合物包含小于3重量％、优选小于1重量％、更优选约0重量％的交联剂。
在一个实施方式中，组合物可包含表面活性剂。在另一实施方式中，不包含其它成分。亦即，组合物基本由溶剂体系中的聚羟基醚组成、或者甚至由溶剂体系中的聚羟基醚组成。在另一实施方式中，组合物基本由溶剂体系中的聚羟基醚和表面活性剂组成、或者甚至由溶剂体系中的聚羟基醚和表面活性剂组成。
不管确切的配方如何，可激光释放组合物都可以在暂时性粘结工艺中用作粘合组合物，以使用以下所述的方法将器件基材粘结至载体基材。另外，可激光释放组合物可以用作再分布层形成工艺中的堆积组合物，同样如下文所述。
使用暂时性粘结或堆积聚合物的方法
1.暂时性粘结实施方式
参见图1(a)(未按比例绘制)，在示意图和截面图中显示了前体结构10。结构10包括第一基材12。基材12具有前表面或器件表面14、背表面16和最外部边缘18。虽然基材12可以是任何形状，其通常是圆形。优选的第一基材12包括器件晶片，例如器件表面包括选自下组的器件阵列(未显示)的那些器件晶片：集成电路、 MEMS、微传感器、功率半导体、发光二极管、光子电路、插入器(interposer)、包埋的无源器件以及其它在硅和其它半导体材料(例如硅-锗、砷化镓、氮化镓、砷化铝镓、磷化铝铟镓和磷化铟镓)上制造的微器件或由硅和其它半导体材料(例如硅-锗、砷化镓、氮化镓、砷化铝镓、磷化铝铟镓和磷化铟镓)制造的微器件。这些器件的表面通常包括由一种或多种以下材料形成的结构(也未显示)：硅、多晶硅、二氧化硅、(氧)氮化硅、金属(例如铜、铝、金、钨、钽)，低k电介质、聚合物电介质和各种金属氮化物和硅化物。器件表面14也可包括至少一种选自下组的结构：焊接凸起；金属杆形件；金属柱；以及由选自硅、多晶硅、二氧化硅、(氧)氮化硅、金属、低k电介质、聚合物电介质、金属氮化物和金属硅化物的材料形成的结构。
如图1(a)所示，将根据本发明的可激光释放粘结组合物施加在第一基材12上以在器件表面14上形成可激光释放粘结层20。粘结层20具有远离第一基材12的上表面21，并且优选地，粘结层20直接形成于器件表面14上(即，在粘结层20和基材12之间没有任何中间层)。可以通过任意已知的施加方法来施加粘结组合物。一个优选的方法包括：以约500rpm至约3,000rpm(优选为约1,000rpm至约2,000rpm)的速度在约10秒至约120秒(优选为约30至约90秒)的时间内旋涂所述组合物。
在施加所述组合物后，优选将其加热至约120℃至约250℃，更优选为约150 ℃至约200℃的温度并持续约60秒至约10分钟(优选为约120秒至约5分钟)的时间。重要的是，在该加热期间几乎没有或没有发生交联。换而言之，所得到的粘结层20优选是热塑性的。
在一些实施方式中，取决于所使用的组合物，优选使粘结层20经受多阶段烘烤处理。同样，在一些示例中，上述施加和烘烤处理可在所述组合物的另一个等分试样上重复，从而以多步骤在第一基材12上“建立”第一粘结层20。
在另一实施方式中，本发明的可激光释放粘结组合物可以形成为预成型的干燥薄膜，而不是施加成为可流动组合物。在该示例中，该组合物形成为即使无支撑也不会塌陷或改变性质(没有施加力或能量)的无支撑自我维持薄膜随后将该薄膜粘附至第一基材12，以形成可激光释放粘结组合物20，如图1(a)所示。
无论粘结层20如何形成，其平均厚度(在五个位置测量)应为约1μm至约 200μm，更优选约5μm至约50μm，甚至更优选约1μm至约30μm。可以使用任何薄膜厚度测量工具来测量本文所使用的厚度，并且一种优选工具是红外干涉仪，例如SUSS Microtec或Foothill出售的那些。
粘结层20还应当具有低的总厚度变化(“TTV”)，这意味着层20的最厚点和最薄点彼此没有显著差异。TVV优选通过在薄膜上多个点或位置处测量厚度来计算，优选在至少约50个点或在约50个点处测量厚度，更优选在至少约100个点或在100个点处测量厚度，甚至优选在至少约1,000个点或在约1,000个点处测量厚度。在这些点处获得的最高厚度测量值和最低厚度测量值之间的差值被称为该特定层的TTV测量值。在一些TTV测量示例中，可以从计算中删除边缘剔除或异常值。在这些情况下，包含的测量次数以百分比表示，亦即，如果以97％的包含率给出TTV，则3％的最高和最低测量值将被剔除，并且3％在最高和最低测量值之间均分(即，各1.5％)。优选地，使用约95％至约100％的测量值、更优选约97 ％至约100％的测量值，甚至更优选约100％的测量值来实现上述TTV范围。
除了绝对数(例如5μm)方面的TTV低之外，相对于粘结层20的平均薄膜厚度的TTV也应该是低的。因此，粘结层20在空白基材上的TTV应小于粘结层20平均厚度的约25％，优选小于粘结层20平均厚度的约10％，并且更优选地小于粘结层20平均厚度的约5％。例如，如果粘结层20具有50μm的平均厚度，则最大可接受的TTV将为约12.5μm或更小(小于50μm的约25％)，优选地为约5μm或更小(小于50μm的约10％)，更优选约2.5μm或更小(小于50μm的约5％)。
另外，可激光释放的粘结层20将与所需的基材形成牢固的粘结。如通过 ASTMD4541/D7234测定的，粘结强度大于约50psig、优选为约80-250psig、更优选为约100-150psig的任何物质都适合用作粘结层20。
粘结层20的k值将为至少约0.008，优选至少约0.05，更优选至少约0.1，甚至更优选约0.1至约0.4。
图1(a)中的截面示意图也描绘了第二前体结构22。第二前体结构22包括第二基材24。在此实施方式中，第二基材24是载体晶片。也就是说，第二基材24具有前表面或载体表面26、背表面28和最外部边缘30。虽然第二基材24可以是任何形状，但通常其为圆形，并且尺寸与第一基材12相似。优选的第二基材24包括透明玻璃晶片或能允许激光能量通过载体基材的任何其他(对激光能量)透明的基材。一个特别优选的玻璃载体晶片是康宁
Figure GDA0002575030240000071
EAGLE
Figure GDA0002575030240000072
玻璃晶片。
随后将结构10和22以面对面的关系按压在一起，从而使粘结层20的上表面21 与第二基材24的前表面或载体表面26接触(图1(b))。在按压时，施加足够的压力和热并持续足够的时间，从而使两个结构10和22粘结在一起以形成粘结的堆叠体34。取决于形成粘结层20的组合物，粘结参数会变化，但在此步骤中的通常温度为约150℃至约250℃，优选为约180℃至约220℃，通常压力为约1000N至约 25,000N，优选约3,000N至约20,000N，持续时间为约30秒至约20分钟，优选为约 3分钟至10分钟。
粘结堆叠体34的TTV应小于总平均厚度的约10％，优选小于总平均厚度的约 5％(在整个堆叠体43的五个位置测量)，并且更优选地小于粘结堆叠体34的总平均厚度的约3％。亦即，如果粘结堆叠体34的平均厚度为100μm，则小于约10％的TTV为约10μm或更低。
现在可安全地处理第一基材12并对其进行进一步加工，如果未将第一基材12 粘结至第二基材24的情况下，这种加工可能损害第一基材12。因此，所述结构可安全地进行背侧加工，例如背研磨、化学-机械抛光("CMP")、蚀刻、金属沉积(即金属化)、电介质沉积、图案化(例如光刻、通孔蚀刻)、钝化、退火、再分布层形成、以及它们的组合，而不会发生基材12和24的分离，且不会渗透在这些后续处理步骤中遇到的任何化学物质。粘结层20不仅可以承受这些加工，而且还可以承受高达约300℃、优选约150℃至约280℃，并且更优选约180℃至约250℃的加工温度。
一旦加工完成，就可以通过使用激光分解或烧蚀全部或部分可激光释放的粘合层20来分离基材12和24。合适的激光包括UV激光，优选波长为约200nm至约 400nm，最优选波长为约300nm至约360nm。为了使可释放激光的粘结层脱粘，以蛇形图案在整个载体晶片的表面上进行扫描激光，以使整个晶片暴露。示例性的激光脱粘工具包括SUSS MicroTecLambda STEEL 2000激光脱粘器、EVG850 DB 自动化脱粘系统和Kingyoup LD-自动200/300激光脱粘器。晶片优选用场尺寸为约 40×40μm至约12.5×4mm的激光斑进行扫描。使基材脱粘的合适能量密度(fluence) 为约100mJ/cm2至约400mJ/cm2，优选约150mJ/cm2至约350mJ/cm2。使基材脱粘结的合适功率为约2W至6W，优选为约3W至约4W。
在激光暴露后，基材12和24将容易分离。在分离后，可以用等离子体蚀刻或能溶解粘结层20的溶剂来去除任意剩余的粘结层20。
在上述实施方式中，可激光释放粘结层20显示于器件晶片的第一基材12上。应理解，这些基材/层方案可颠倒。亦即，粘结层20可以形成于第二基材24(即，载体晶片)上。与上述实施方式相同的组成和加工条件应用于该实施方式。
在特别优选的实施方式中，粘结层20是基材12和24之间的唯一层。然而，应理解在替代性实施方式中，粘结层20可以与其他粘结材料、结构支撑层、层叠辅助层、联接层(用于粘附至初始基材)、污染控制层和清洁层一起使用。优选的结构和施加技术将由应用和工艺流程决定。
图2显示了该替代的多层实施方式的示例，其中，与图1相同的标号表示相同的部分。在图2的实施方式中，将本发明的粘结组合物施加至第二基材24以在载体表面26上形成粘结层20，形成结构22’，如图2(a)所示。或者，结构22’可以已成形的形式提供。将不同于用于形成可激光释放粘结层20的第二组合物施加至第一基材12的器件表面14上以形成层32。层32具有远离第一基材12的上表面34以及与第一基材12相邻的下表面36。在一个实施方式中，层32是第二粘结层，用于需要多层粘结方案的示例中。在该示例中，优选第二粘结层32的粘结强度大于可激光释放粘结层20的粘结强度(比其更牢固)。特别是，第二粘结层32的粘结强度是可激光释放粘结层20的粘结强度的至少约1.2倍，优选至少约1.5倍，更优选约1.7 至约4倍。第一和第二基材12、24的分离可以如前文所述进行。
或者，在多层方案中，该基材/层方案可以颠倒。亦即，层32可以形成于第二基材24(载体晶片)上，同时本发明的可激光释放粘结层20形成于在第一基材12(器件晶片)上。在该示例中，对层32(不管其是否是粘结层)进行选择，以使激光能量在通过第二基材24之后从层32通过，从而允许激光能量接触可激光是否粘结层20，并导致分解，如前文所述。
2.堆积层实施方式
在另一实施方式中，本发明的可激光释放组合物可以用作堆积层，用于再生层(“RDL”)形成，尤其是在晶圆级或面板级工艺的RDL优先/芯片后封装中，这有利于最大程度地减少或者甚至避免在封装过程中已知的合格裸晶损失 (known-good die loss)。该工艺的一个方案如图3所示。
如图3(a)所示，将如前文所述的可激光释放粘结或堆积组合物施加至载体基材40的上表面38以在载体表面38上形成可激光释放粘结层42。堆积层42按关于上述暂时性粘结实施方式所述的任意方法形成，包括加工条件和产生的性质。堆积层42具有远离载体基材40的上表面44，并且优选地，堆积层42直接形成于载体基材40的上表面38上(即，在堆积层42和基材40之间没有任何中间层)。
接着，晶种层46按常规方法放置于上表面44上。晶种层46随后可以同样按照已知方法用光刻胶涂覆、图案化并电镀，形成图3(c)所示结构。参见图3(d)，剥去光刻胶，并且蚀刻金属，随后进行介电层的涂覆、图案化和固化。这导致形成第一RDL48，如图3(e)所示。图3(b)至图3(e)的步骤可以按需重复多次，以产生多个RDL(45(a)-(d)，即，图3(f)所示实施方式中的四个RDL)。
参见图3(g)，在形成所需数量的RDL后，同样按常规方法将焊球50附着至最上面(最后形成的)RDL。将晶片(die)52粘结至焊球50，随后施加并研磨常规环氧树脂模塑层54，形成扇出型晶圆级封装结构56。最后，按如上所述激光分离条件，将激光能量施加至载体基材40，以分解或烧蚀全部或部分可激光释放堆积层42。在激光施加后，载体基材40将释放，并且与扇出型晶圆级封装结构56分离(图3(h))，并且通过溶剂去除任意剩余堆积层42。
应注意，用于形成扇出型晶圆级封装结构的上述工艺仅是可以使用本发明组合物作为堆积层进行的该类型工艺的一个示例，并且该工艺可以根据使用者需要进行变化。例如，RDL层的数量以及芯片和焊球的数量和位置可以按需变化。本领域技术人员将理解和定制这些设置。
通过阅读本文所述的发明和下面的工作实施例，本发明的各种实施方式的其它优势对于本领域普通技术人员而言是显而易见的。除非另以其它方式说明，应理解本文所述的各种实施方式相互间不必是相互排斥的。例如，在一个实施方式中所示或所述的特征也可以包括在其它实施方式中，但是不是必须包括在其它实施方式中。因此，本发明行本文所述具体实施方式的组合和/或集成的变体。
如本文所用，在两个或更多项项目的列表中使用时词语“和/或”意味着所列出项目中的任何一个都可以单独使用，或者可以使用两个或更多个所列出项目的任意组合。例如，如果组合物描述为含有或排除组分A、B和/C，则组合物含有或排除单独的组分A；单独的组分B；单独的组分C；A和B的组合；A和C的组合； B和C的组合；或A、B和C的组合。
本发明还使用数值范围来量化与本发明多个实施方式有关的某些参数。应该理解，当提供数值范围时，这些范围将被解释为为仅描述该范围下限值的权利要求限制以及仅描述该范围上限值的权利要求提供文字支持。例如，所公开的约10 至约100的数值范围为描述“大于约10”(无上限)的权利要求和描述“小于约100” (无下限)的权利要求提供了文字支持。
实施例
以下实施例描述了根据本发明的方法。然而应理解，这些实施例通过举例的方式提供，其所含的任何内容都不应视作对本发明整体范围的限制。
实施例1
用于激光脱粘的聚合物1
在该过程中，在三颈圆底烧瓶中，将13.07克的4.4'-二羟基二苯甲酮(TCI美国公司(TCI Americ)，波特兰，俄勒冈州)、20.76克的双酚A二缩水甘油醚 (D.E.R.TM 332，西格玛-奥德里奇公司(Sigma-Aldrich)，圣路易斯，密苏里州) 和0.84克的溴化乙基三苯基鏻(西格玛-奥德里奇公司，圣路易斯，密苏里州) 溶解于在65.33克的环戊酮(西格玛-奥德里奇公司，圣路易斯，密苏里州)。该混合物在140℃反应12小时。所得聚合物1在1000克的乙醇(西格玛-奥德里奇公司，圣路易斯，密苏里州)中沉淀，随后在80℃真空干燥过夜。
接着，将30克的纯化的聚合物1溶解于70克的环戊酮中并搅拌一天，获得均匀溶液。所得的制剂1通过0.2μm的Messiner滤器过滤。
在该实施例中发生的反应如下。
Figure GDA0002575030240000111
实施例2
聚合物1的性质
在空气和氮气中以10℃/分钟的斜率进行热重分析(TGA)。结果显示于图4 和5。该聚合物在初始分解温度相对较高，空气中为约350℃，在氮气中为约360 ℃。
聚合物1进行完全表征，并且表征数据显示于表1。重均分子量(Mw)和多分散性(“PDI”)通过使用凝胶渗透色谱法(GPC)，使用THF作为洗脱溶剂来测量。玻璃化转变温度(Tg)用差示扫描量热法(DSC)在25℃至250℃的氮气环境下检测。使用TA仪器公司(TAInstruments)的流变仪测试该材料的流变性(包括熔体粘度)。样品在250℃加载，并记录了250℃至50℃的流变性质。
Figure GDA0002575030240000112
表1：聚合物1的表征
流变数据表明，由于在该温度下聚合物熔体粘度低，聚合物1材料可以用于热压粘结工艺，从而在约200℃获得良好的粘结线。
实施例3
聚合物1的光学测试
使用可变角度光谱椭圆仪(VASE)确定聚合物1的光学常数(n&k)。表2 显示了两个不同波长下样品的光学常数n和k。聚合物1在308nm处具有非常好的吸光度，k值为0.2，但是在355nm处具有不那么好的吸光度，其k值为0.008。308nm 处的高k值进一步表明，聚合物1在该波长下可能具有良好的激光脱粘性能。
Figure GDA0002575030240000113
Figure GDA0002575030240000121
表2：聚合物1的光学常数
实施例4
使用制剂1粘结
在此实施例中，在作为载体晶片的八英寸玻璃晶片上涂覆16μm的实施例1的制剂1。该涂层以3,000rpm/s的加速度，以1000rpm旋涂旋涂30秒。随后将载体晶片在50℃下烘烤3分钟，在120℃下烘烤3分钟，并且在200℃下烘烤3分钟。随后通过在230℃下，在真空中(<5毫巴)，2000N下使用
Figure GDA0002575030240000123
510粘结机(EV集团 (EV Group))粘结3分钟，将经涂覆的载体晶片粘结至8英寸Si晶片。用Chrocdail 红外干涉仪(SUSS MicroTec SE公司)扫描粘结的对，该干涉仪使用Precitec传感器并测量旋转的基材，并且能够测量晶片表面上数百个甚至数千个点。未检测到空隙(参见图6)，该材料显示出良好的粘结线(厚度为16.7μm)，并且最小总厚度变化(“TTV”)为1.72μm，使用97％的测量值。
实施例5
使用制剂1的晶片薄化
使用研磨机/抛光机(DGP8761，Disco公司)以目标厚度60μm对如实施例4 所述制备的六对粘结晶片对进行研磨薄化测试。将晶片粗磨至90μm，去除速率为1μm/s～5μm/s，然后进一步研磨至62μm，去除速率为0.2μm/s～0.4μm/s。然后将晶片抛光，以1μm/分钟的去除速率使其再薄2μm，以达到60μm的最终目标厚度。表3显示六对晶片对的详细数据。粘结线的厚度和TTV与研磨前的数值一致，表明粘结材料在研磨过程中的机械稳定性。薄化的硅晶片也以良好的TTV实现了目标厚度。此外，通过在250℃的氮气烘箱中烘烤30分钟，对薄化晶片对进行热模拟。未观察到任意晶片的严重缺陷。
Figure GDA0002575030240000122
Figure GDA0002575030240000131
表3：研磨前后的粘结晶片对
实施例6
使用制剂1的激光脱粘和清洁
通过使用市场上的三种主要紫外激光波长，SUSS ELD12激光脱粘机、EVG 半自动脱粘系统和Kingyoup LD-半自动200/300使粘结晶片对成功脱粘。表4列出了这三种脱粘机各自的激光脱粘参数。脱粘器件晶片的图像如图7所示。使用环戊酮可以很好地清洁残留在器件晶片上的残留物。清洁后，所述晶片在绿光下视觉上是洁净的，没有残留物。
Figure GDA0002575030240000132
表4：激光脱粘参数
实施例7
用于激光脱粘的聚合物2
在该实施例中，在三颈圆底烧瓶中，将17.71克的4.4'-二羟基二苯甲酮、30.94 克的双酚A二缩水甘油醚(D.E.R.TM 332)和1.35克的溴化乙基三苯基鏻溶解于在 50克的环戊酮。该混合物在150℃反应24小时。
接着，将57.34克的聚合物溶解于42.66克的γ丁内酯中并搅拌一天，获得均匀溶液。所得的制剂2通过0.2μm的Messiner滤器过滤。
实施例8
使用制剂2粘结
在该过程中，通过以3,000rpm/s的加速度，以1000rpm旋涂旋涂30秒，在作为载体晶片的八英寸玻璃晶片上涂覆21μm的实施例7的制剂2。随后将载体晶片在50℃下烘烤4分钟，在110℃下烘烤4分钟，并且在200℃下烘烤4分钟，最后在 220℃下烘烤4分钟。经涂覆的载体晶片粘结至八英尺Si晶片。将晶片对在真空中 (<5毫巴)，210℃，2,000N下在
Figure GDA0002575030240000141
粘结机中粘结。通过目视检查确认了良好的结合线形成。
实施例9
由制剂2产生干燥薄膜
使用刮棒涂布机(K303 Multicoater，英国RK PrintCoat仪器有限公司)在以下条件下将对激光敏感的热塑性制剂2流延到50μm的聚对苯二甲酸乙二醇酯载体薄膜(H950A，中国台湾省南亚塑料公司)上：间隙80μm，速度40米/分钟。将溶剂浇铸薄膜在热板中于50℃干燥5分钟，然后在140℃干燥5分钟，以获得尺寸为厚度20μm、宽度200mm和长度300mm的自立式干燥粘结薄膜。
实施例10
干燥薄膜的层叠
在以下条件下使用Tamerica,TCC-2700热辊层压机将实施例9中产生的粘结薄膜层叠至100mm的玻璃晶片上：辊温度140℃，速度0.2米/分钟。用刀修整多余的薄膜，并在层压后将聚对苯二甲酸乙二醇酯基膜剥去。
实施例11
层叠玻璃晶片的粘结
在以下条件下，使用
Figure GDA0002575030240000142
ApogeeTM粘结机(成本高效设备公司(Cost EffectiveEquipment,LLC)，罗拉，密苏里州)，将实施例10中制备的层叠玻璃晶片与另一100毫米玻璃晶片粘结在一起：压板温度230℃，力1800N，3分钟。在晶片间粘结后未观察到空隙或分层。
实施例12
粘结晶片对的激光释放和清洁
在加工后，在以下条件下，使用355-nm激光脱粘机(LD-半自动300，勤友企业有限公司(Kingyoup Enterprises Co.,Ltd.))使得粘结的玻璃晶片对分离：功率6W，扫描速度2m/s，线间距40μm。在脱粘后，两个玻璃晶片用GBL-环己酮共溶剂体系旋转清洁，用于重新使用和进一步加工。

Claims (49)

1.一种暂时性粘结方法，其包括:
提供堆叠体，该堆叠体包括：
具有背表面和前表面的第一基材；
与所述前表面相邻且包含聚羟基醚的粘结层；以及
第二基材，其具有与所述粘结层相邻的第一表面；以及
使粘结层暴露于激光能量，以促进第一基材和第二基材的分离。
2.如权利要求1所述的方法，其中，所述聚羟基醚包括二缩水甘油醚和二羟基染料的共聚物。
3.如权利要求2所述的方法，其中，所述二缩水甘油醚选自下组：双酚A二缩水甘油醚、双酚F二缩水甘油醚、1,4-环己烷二甲醇二缩水甘油醚、间苯二酚二缩水甘油醚、双酚A丙氧基化二缩水甘油醚、乙二醇二缩水甘油醚、1,4-环己二甲醇二缩水甘油醚、甘油二缩水甘油醚、1,4-丁二醇二缩水甘油醚、新戊二醇二缩水甘油醚、1,3-丁二醇二缩水甘油醚、1,3-双(3-环氧丙氧基丙基)四甲基二硅氧烷及它们的组合。
4.如权利要求2所述的方法，其中，所述二羟基染料选自下组：4,4'-二羟基二苯甲酮、二羟基查尔酮染料、4-[(2-苯基亚肼基)甲基]间苯二酚、二羟基偶氮苯、二羟基蒽醌、2,2'-亚甲基双[6-(苯并三唑-2-基)-4-叔辛基苯酚]、姜黄素、姜黄素衍生物及它们的组合。
5.如权利要求1所述的方法，其中，所述粘结层是热塑性层。
6.如权利要求1所述的方法，其中，所述暴露以约200mJ/cm2至约400mJ/cm2的剂量进行。
7.如权利要求1所述的方法，其中，所述提供堆叠体包括在所述前表面上形成所述粘结层。
8.如权利要求7所述的方法，其中，在所述前表面上形成所述粘结层包括将可流动粘结组合物施加至所述前表面，所述可流动组合物含有分散或溶解在溶剂体系中的聚羟基醚。
9.如权利要求8所述的方法，所述方法还包括：在约120℃至250℃的温度下加热所述组合物约60秒至约10分钟的时间，以形成所述粘结层。
10.如权利要求7所述的方法，其中，在所述前表面上形成所述粘结层包括将含有聚羟基醚的自立式薄膜施加至所述前表面以形成所述粘结层。
11.如权利要求10所述的方法，其中，将含有聚羟基醚的自立式薄膜施加至所述前表面以形成所述粘结层包括使所述自立式薄膜粘附至所述前表面。
12.如权利要求1所述的方法，其中，所述前表面和所述第一表面中的一个选自下组：
(1)包括选自下组的器件阵列的器件表面：集成电路；MEMS；微传感器；功率半导体；发光二极管；光子电路；插入器；包埋的无源器件以及在硅、硅-锗、砷化镓和氮化镓上制造的微器件或由硅、硅-锗、砷化镓和氮化镓制造的微器件。
(2)包括至少一种选自下组的结构的器件表面：焊接凸起；金属杆形件；金属柱；以及由选自硅、多晶硅、二氧化硅、(氧)氮化硅、金属、低k电介质、聚合物电介质、金属氮化物和金属硅化物的材料形成的结构。
13.如权利要求1所述的方法，其中，所述第一和第二基材中的一个包含玻璃或其它透明材料。
14.如权利要求1所述的方法，所述方法还包括：在分离所述第一和第二基材之前，对所述堆叠体施加选自下组的加工：背研磨、化学-机械抛光、蚀刻、金属化、电介质沉积、图案化、钝化、退火、再分布层形成以及它们的组合。
15.如权利要求1所述的方法，其中，所述粘结层是所述第一基材和第二基材之间仅有的层。
16.如权利要求1所述的方法，所述粘结层具有第一粘结强度，并且所述堆叠体还包含所述第一基材和第二基材之间的第二粘结层，所述第二粘结层的粘结强度大于所述第一粘结强度。
17.一种微电子结构，其包括：
具有背表面和前表面的第一基材；
与所述前表面相邻的粘结层，所述粘结层包含聚羟基醚；以及
具有与所述粘结层相邻的第一表面的第二基材，所述前表面和所述第一表面中的至少一个是器件表面。
18.如权利要求17所述的微电子结构，其中，所述聚羟基醚包括二缩水甘油醚和二羟基染料的共聚物。
19.如权利要求18所述的微电子结构，其中，所述二缩水甘油醚选自下组：双酚A二缩水甘油醚、双酚F二缩水甘油醚、1,4-环己烷二甲醇二缩水甘油醚、间苯二酚二缩水甘油醚、双酚A丙氧基化二缩水甘油醚、乙二醇二缩水甘油醚、1,4-环己二甲醇二缩水甘油醚、甘油二缩水甘油醚、1,4-丁二醇二缩水甘油醚、新戊二醇二缩水甘油醚、1,3-丁二醇二缩水甘油醚、1,3-双(3-环氧丙氧基丙基)四甲基二硅氧烷及它们的组合。
20.如权利要求18所述的微电子结构，其中，所述二羟基染料选自下组：4,4'-二羟基二苯甲酮、二羟基查尔酮染料、4-[(2-苯基亚肼基)甲基]间苯二酚、二羟基偶氮苯、二羟基蒽醌、2,2'-亚甲基双[6-(苯并三唑-2-基)-4-叔辛基苯酚]、姜黄素、姜黄素衍生物及它们的组合。
21.如权利要求17所述的微电子结构，其中，所述粘结层是热塑性层。
22.如权利要求17所述的微电子结构，其中，所述粘结层的平均厚度为约1μm至约100μm。
23.如权利要求17所述的微电子结构，其中，所述前表面和所述第一表面中的一个选自下组：
(1)包括选自下组的器件阵列的器件表面：集成电路；MEMS；微传感器；功率半导体；发光二极管；光子电路；插入器；包埋的无源器件以及在硅、硅-锗、砷化镓和氮化镓上制造的微器件或由硅、硅-锗、砷化镓和氮化镓制造的微器件。
(2)包括至少一种选自下组的结构的器件表面：焊接凸起；金属杆形件；金属柱；以及由选自硅、多晶硅、二氧化硅、(氧)氮化硅、金属、低k电介质、聚合物电介质、金属氮化物和金属硅化物的材料形成的结构。
24.如权利要求17所述的微电子结构，其中，所述第一和第二基材中的一个包含玻璃或其它透明材料。
25.如权利要求17所述的微电子结构，其中，所述粘结层是所述第一基材和第二基材之间仅有的层。
26.如权利要求17所述的微电子结构，所述粘结层具有第一粘结强度，并且还包含所述第一基材和第二基材之间的第二粘结层，所述第二粘结层的粘结强度大于所述第一粘结强度。
27.一种形成微电子结构的方法，所述方法包括：
(I)在基材表面上形成堆积层，所述堆积层包括聚羟基醚，并且具有远离所述基材表面的上表面；
(II)在所述上表面上形成第一再分布层；以及
(III)在所述第一再分布层上任选地形成一个或多个另外的再分布层。
28.如权利要求27所述的方法，所述方法还包括：
(IV)使得焊球附着至形成步骤(II)和任选的形成步骤(III)的最后的再分布层；
(V)使芯片附着至所述焊球；以及
(VI)任选地重复附着步骤(IV)和附着步骤(V)一次或多次。
29.如权利要求28所述的方法，所述方法还包括在所述芯片和焊球上形成环氧树脂层以在所述基材上形成扇出型晶圆级封装结构。
30.如权利要求29所述的方法，所述方法还包括：分离所述基材和所述扇出型晶圆级封装结构。
31.如权利要求30所述的方法，其中，所述分离包括：使所述堆积层暴露于激光能量以促进所述基材和所述扇出型晶圆级封装结构分离。
32.如权利要求31所述的方法，其中，所述暴露以约200mJ/cm2至约400mJ/cm2的剂量进行。
33.如权利要求27所述的方法，其中，所述聚羟基醚包括二缩水甘油醚和二羟基染料的共聚物。
34.如权利要求33所述的方法，其中，所述二缩水甘油醚选自下组：双酚A二缩水甘油醚、双酚F二缩水甘油醚、1,4-环己烷二甲醇二缩水甘油醚、间苯二酚二缩水甘油醚、双酚A丙氧基化二缩水甘油醚、乙二醇二缩水甘油醚、1,4-环己二甲醇二缩水甘油醚、甘油二缩水甘油醚、1,4-丁二醇二缩水甘油醚、新戊二醇二缩水甘油醚、1,3-丁二醇二缩水甘油醚、1,3-双(3-环氧丙氧基丙基)四甲基二硅氧烷及它们的组合。
35.如权利要求33所述的方法，其中，所述二羟基染料选自下组：4,4'-二羟基二苯甲酮、二羟基查尔酮染料、4-[(2-苯基亚肼基)甲基]间苯二酚、二羟基偶氮苯、二羟基蒽醌、2,2'-亚甲基双[6-(苯并三唑-2-基)-4-叔辛基苯酚]、姜黄素、姜黄素衍生物及它们的组合。
36.如权利要求27所述的方法，其中，形成步骤(I)包括将可流动组合物施加至所述基材的表面，所述可流动组合物含有分散或溶解在溶剂体系中的所述聚羟基醚。
37.如权利要求36所述的方法，所述方法还包括：在约120℃至250℃的温度下加热所述组合物约60秒至约10分钟的时间，以形成所述堆积层。
38.如权利要求27所述的方法，其中，形成步骤(I)包括将含有所述聚羟基醚的自立式薄膜施加至所述基材的表面以形成所述堆积层。
39.如权利要求38所述的方法，其中，将含有所述聚羟基醚的自立式薄膜施加至所述基材的表面以形成所述堆积层包括使所述自立式薄膜黏附至所述基材的表面。
40.如权利要求27所述的方法，其特征在于，所述基材包含玻璃或其它透明材料。
41.如权利要求27所述的方法，所述方法还包括：
使得多个焊球附着至形成步骤(II)和任选的形成步骤(III)的最后的再分布层；以及
使芯片附着至所述多个焊球中的至少两个。
42.一种微电子结构，其包括：
具有表面的基材；
在基材表面上的堆积层，所述堆积层包括聚羟基醚，并且具有远离基材表面的上表面；以及
在所述上表面上的第一再分布层。
43.如权利要求42所述的结构，所述结构还包括在所述第一再分布层上的一个或多个另外的再分布层。
44.如权利要求42所述的结构，所述结构还包括在所述第一再分布层上的至少一个焊球和附着至所述至少一个焊球的芯片。
45.如权利要求44所述的结构，所述结构还包括在所述焊球和芯片上的环氧树脂涂层。
46.如权利要求42所述的结构，其中，所述聚羟基醚包括二缩水甘油醚和二羟基染料的共聚物。
47.如权利要求46所述的结构，其中，所述二缩水甘油醚选自下组：双酚A二缩水甘油醚、双酚F二缩水甘油醚、1,4-环己烷二甲醇二缩水甘油醚、间苯二酚二缩水甘油醚、双酚A丙氧基化二缩水甘油醚、乙二醇二缩水甘油醚、1,4-环己二甲醇二缩水甘油醚、甘油二缩水甘油醚、1,4-丁二醇二缩水甘油醚、新戊二醇二缩水甘油醚、1,3-丁二醇二缩水甘油醚、1,3-双(3-环氧丙氧基丙基)四甲基二硅氧烷及它们的组合。
48.如权利要求46所述的结构，其中，所述二羟基染料选自下组：4,4'-二羟基二苯甲酮、二羟基查尔酮染料、4-[(2-苯基亚肼基)甲基]间苯二酚、二羟基偶氮苯、二羟基蒽醌、2,2'-亚甲基双[6-(苯并三唑-2-基)-4-叔辛基苯酚]、姜黄素、姜黄素衍生物及它们的组合。
49.如权利要求42所述的结构，其中，所述第一和第二基材中的一个包含玻璃或其它透明材料。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10490525B1 (en) * 2018-05-10 2019-11-26 International Business Machines Corporation High speed handling of ultra-small chips by selective laser bonding and debonding
US11073572B2 (en) * 2019-01-17 2021-07-27 Infineon Technologies Ag Current sensor device with a routable molded lead frame
WO2020154225A1 (en) * 2019-01-22 2020-07-30 Brewer Science, Inc. Laser-releasable bonding materials for 3-d ic applications
CN110396404B (zh) * 2019-07-12 2022-06-17 新乡医学院 基于腙类衍生物的荧光分子探针及其制备方法和在阳离子识别方面的应用
JP2022543238A (ja) * 2019-08-02 2022-10-11 ブルーワー サイエンス アイ エヌ シー． 持続的接合及びパターニングの材料
KR20210087337A (ko) 2020-01-02 2021-07-12 삼성전자주식회사 반도체 패키지와 이를 구비하는 전자 장치 및 반도체 패키지의 제조방법
WO2022036307A1 (en) * 2020-08-14 2022-02-17 Brewer Science, Inc. Permanent bonding and patterning material

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101393400A (zh) * 2008-10-29 2009-03-25 清溢精密光电（深圳）有限公司 除粘用光催化剂溶液及液体感光性树脂凸版表面除粘方法
US20130288058A1 (en) * 2012-04-30 2013-10-31 Brewer Science Inc. Development of high-viscosity bonding layer through in-situ polymer chain extension
CN104293224A (zh) * 2013-07-19 2015-01-21 日东电工株式会社 热剥离型粘合带及电子部件的切断方法
US20160133499A1 (en) * 2014-11-07 2016-05-12 International Business Machines Corporation Adhesive resins for wafer bonding
WO2016151485A1 (en) * 2015-03-25 2016-09-29 International Business Machines Corporation Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer-debonding

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5989700A (en) * 1996-01-05 1999-11-23 Tekscan Incorporated Pressure sensitive ink means, and methods of use
US7052597B2 (en) * 2001-03-27 2006-05-30 Exxonmobil Research And Engineering Company Tuning fuel composition for driving cycle conditions in spark ignition engines
DE502006000292D1 (de) * 2005-03-22 2008-03-06 Ems Chemie Ag Aus einem Polyhydroxyether enthaltenden Rohstoff gesponnenes thermoplastisches Fasermaterial, Verfahren zu seiner Herstellung und Verwendungen dafür
KR101096142B1 (ko) * 2008-01-24 2011-12-19 브레우어 사이언스 인코포레이션 캐리어 기판에 디바이스 웨이퍼를 가역적으로 장착하는 방법
US8859672B2 (en) * 2011-06-27 2014-10-14 Sabic Global Technologies B.V. Poly(arylene ether)-poly(hydroxy ether) block copolymer and method of making
WO2013006865A2 (en) 2011-07-07 2013-01-10 Brewer Science Inc. Methods of transferring device wafers or layers between carrier substrates and other surfaces
WO2013102146A1 (en) 2011-12-30 2013-07-04 Deca Technologies, Inc. Die up fully molded fan-out wafer level packaging
EP3092658A4 (en) * 2014-01-07 2017-07-05 Brewer Science, Inc. Cyclic olefin polymer compositions and polysiloxane release layers for use in temporary wafer bonding processes
US9865490B2 (en) * 2014-01-07 2018-01-09 Brewer Science Inc. Cyclic olefin polymer compositions and polysiloxane release layers for use in temporary wafer bonding processes
TWI663058B (zh) 2014-07-22 2019-06-21 美商布魯爾科技公司 作爲三維積體電路應用的雷射釋放材料的聚醯亞胺
US9324601B1 (en) 2014-11-07 2016-04-26 International Business Machines Corporation Low temperature adhesive resins for wafer bonding
EP3485506A4 (en) 2016-07-15 2020-03-11 Brewer Science, Inc. LASER ABLATIVE DIELECTRIC MATERIAL
US10617010B2 (en) 2016-08-29 2020-04-07 Brewer Science, Inc. Polymer film stencil process for fan-out wafer-level packaging of semiconductor devices
US10217637B1 (en) * 2017-09-20 2019-02-26 International Business Machines Corporation Chip handling and electronic component integration
BR112020008922A2 (pt) * 2017-11-08 2020-10-20 Cytec Industries Inc. estrutura de compósito polimérico reforçada com fibra, e, método para produzir uma estrutura de compósito polimérico reforçada com fibra.

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101393400A (zh) * 2008-10-29 2009-03-25 清溢精密光电（深圳）有限公司 除粘用光催化剂溶液及液体感光性树脂凸版表面除粘方法
US20130288058A1 (en) * 2012-04-30 2013-10-31 Brewer Science Inc. Development of high-viscosity bonding layer through in-situ polymer chain extension
CN104293224A (zh) * 2013-07-19 2015-01-21 日东电工株式会社 热剥离型粘合带及电子部件的切断方法
US20160133499A1 (en) * 2014-11-07 2016-05-12 International Business Machines Corporation Adhesive resins for wafer bonding
WO2016151485A1 (en) * 2015-03-25 2016-09-29 International Business Machines Corporation Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer-debonding

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