CN111554652A - 用于智能卡的导电迹线设计 - Google Patents

用于智能卡的导电迹线设计 Download PDF

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Publication number
CN111554652A
CN111554652A CN202010085485.4A CN202010085485A CN111554652A CN 111554652 A CN111554652 A CN 111554652A CN 202010085485 A CN202010085485 A CN 202010085485A CN 111554652 A CN111554652 A CN 111554652A
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Prior art keywords
conductive
vias
substrate
conductive vias
major surface
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CN202010085485.4A
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English (en)
Inventor
阿蒙帖·赛亚吉塔拉
威瓦·坦翁旺
南他博卜·拉帕尼特卜泊
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NXP BV
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NXP BV
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Abstract

一种用于组装智能卡的引线框架由具有相对的第一主表面和第二主表面的基板形成。管芯收容区域在所述基板的所述第一主表面中形成并且被导电通孔包围。导电涂层在所述基板的所述第二主表面上形成并且被图案化以在所述导电通孔上形成电接触焊盘。导电迹线在所述基板的所述第一主表面上形成。所述导电迹线在至少两个相邻通孔之间延伸并且部分地包围所述至少两个相邻导电通孔，从而在所述迹线的包围所述通孔的部分中形成间隙。集成电路芯片与所述导电通孔之间的电连接在所述间隙上延伸。所述间隙防止所述电连接与所述导电迹线发生意外接触。

Description

用于智能卡的导电迹线设计
技术领域
本发明总体上涉及智能卡，并且更具体地说，涉及用于智能卡的导电迹线设计。
背景技术
参考图1A，示出了智能卡10，所述智能卡10具有信用卡大小的主体12，所述主体12具有第一主表面14，所述第一主表面14包括用于收容IC模块18的集成电路(IC)模块收容区域16和天线20。图1B是IC模块18从载体22分离之前的俯视平面图。IC模块18包括IC 24，所述IC 24可以是安装在基板或引线框架26上的具有一定存储的微控制器，所述基板或引线框架26是载体22的一部分。基板26包括多个通孔28，所述多个通孔28使IC 24的有源表面上的导电焊盘通过键合导线30电连接到基板26的相对侧上的接触焊盘。通过包括天线20和接触焊盘两者，智能卡使得能够进行接触式连接和非接触式连接。
通孔28通常包括电镀贯穿孔。一条或多条导电迹线32和33在基板26的表面上形成并且形成了IC 24与天线20之间的连接。如图1B所示，导电迹线32和33从一个通孔行进到相邻的通孔等等。导电迹线32和33还如图1C所示包围通孔28，图1C是通孔28、将IC 24连接到通孔28的键合导线30和导电迹线32的显著放大平面图。
还如图1C所示，智能卡封装体的问题在于，键合导线30中的一条有时会下垂并与导电迹线32发生意外接触，从而引起可能导致智能卡不正确运行的短路状况。因此，将会希望能够组装出不会由于键合导线与导电迹线32发生意外接触而导致意外短路的智能卡。
发明内容
一种用于组装智能卡的引线框架，其包括：
基板，所述基板具有相对的第一主表面和第二主表面；
管芯收容区域，所述管芯收容区域在所述基板的所述第一主表面中形成；
多个导电通孔，所述多个导电通孔总体上包围所述管芯收容区域；
导电涂层，所述导电涂层在所述基板的所述第二主表面上形成，其中所述导电涂层被图案化以在所述多个导电通孔上形成多个电接触焊盘；以及
至少一条导电迹线，所述至少一条导电迹线在所述基板的所述第一主表面上形成，其中所述导电迹线在至少两个相邻通孔之间延伸，并且其中所述导电迹线不完全包围所述至少两个相邻导电通孔。
可选地，所述导电通孔是圆形、椭圆形、矩形和三角形中的一种。
可选地，所述至少一条导电迹线围绕所述至少两个相邻导电通孔延伸约一半距离。
可选地，所述至少一条导电迹线围绕所述至少两个相邻导电通孔延伸超过一半距离。
可选地，所述导电迹线的部分地包围所述至少两个相邻导电通孔的部分被配置成使得从集成电路芯片延伸到所述至少两个相邻导电通孔的键合导线在所述导电通孔的未被所述导电迹线包围的部分上延伸。
可选地：
所述多个导电通孔包括两组导电通孔，所述两组导电通孔安置在所述管芯收容区域的相对侧上；并且所述至少一条导电迹线包括第一导电迹线和第二导电迹线，所述第一导电迹线在所述第一组中的所述导电通孔中的每个导电通孔之间延伸并且部分地包围所述第一组中的所述导电通孔中的每个导电通孔，所述第二导电迹线在所述第二组中的所述导电通孔中的每个导电通孔之间延伸并且部分地包围所述第二组中的所述导电通孔中的每个导电通孔。
可选地，所述管芯收容区域包括深度小于所述基板的厚度的约一半的腔。
可选地，在所述基板的所述第二主表面上形成的所述导电涂层在所述腔上延伸，使得安置在所述腔内的集成电路芯片的主表面搁置在所述导电涂层上。
可选地，所述导电涂层还在所述导电通孔上延伸并且包括位于在所述导电通孔上延伸的部分与在所述腔上方的部分之间的间隙。
可选地，所述导电涂层包括用粘合剂附接到所述基板的所述第二主表面的铜箔。
可选地，所述导电涂层包括用于防止所述铜氧化的防腐蚀涂层。
一种智能卡，其包括：
基板，所述基板具有相对的第一主表面和第二主表面；
管芯收容区域，所述管芯收容区域在所述基板的所述第一主表面中形成；
多个导电通孔，所述多个导电通孔总体上包围所述管芯收容区域，其中所述导电通孔从所述第一主表面延伸到所述第二主表面；
导电涂层，所述导电涂层在所述基板的所述第二主表面上形成，其中所述导电涂层被图案化以在所述多个导电通孔上形成多个电接触焊盘；
至少一条导电迹线，所述至少一条导电迹线在所述基板的所述第一主表面上形成，其中所述导电迹线在至少两个相邻通孔之间延伸，并且其中所述导电迹线不完全包围所述至少两个相邻导电通孔；
集成电路芯片，所述集成电路芯片安置在所述管芯收容区域内；以及
多个电连接，所述多个电连接将所述集成电路芯片电连接到所述导电通孔中的相应导电通孔。
可选地，所述至少一条导电迹线围绕所述至少两个相邻导电通孔延伸约一半距离。
可选地，所述至少一条导电迹线围绕所述至少两个相邻导电通孔延伸超过一半距离。
可选地，所述导电通孔是圆形、椭圆形、矩形和三角形中的一种。
可选地，所述至少一条导电迹线的部分地包围所述至少两个相邻导电通孔的部分被配置成使得从所述集成电路芯片延伸到所述至少两个相邻导电通孔的所述电连接在所述至少两个相邻导电通孔的未被所述导电迹线包围的部分上延伸。
可选地：
所述多个导电通孔包括两组导电通孔，所述两组导电通孔安置在所述管芯收容区域的相对侧上；并且
所述至少一条导电迹线包括第一导电迹线和第二导电迹线，所述第一导电迹线在所述第一组中的所述导电通孔中的每个导电通孔之间延伸并且仅部分地包围所述第一组中的所述导电通孔中的每个导电通孔，所述第二导电迹线在所述第二组中的所述导电通孔中的每个导电通孔之间延伸并且仅部分地包围所述第二组中的所述导电通孔中的每个导电通孔。
可选地，所述管芯收容区域包括深度小于所述基板的厚度的约一半的腔。
可选地，在所述基板的所述第二主表面上形成的所述导电涂层在所述腔上延伸，使得安置在所述腔内的所述集成电路芯片的底表面搁置在所述导电涂层上。
可选地，另外包括在所述基板的所述第一主表面上形成的包封剂，所述包封剂覆盖所述集成电路芯片、所述多个导电通孔、所述至少一条导电迹线和在所述集成电路芯片与所述多个导电通孔之间的所述电连接。
附图说明
为了可以详细理解本发明的特征，下文参考实施例提供了对本发明的详细描述，附图中展示了所述实施例中的一些实施例。附图仅展示了本发明的典型实施例并且因此不应被视为对本发明的范围的限制，因为本发明可以承认其它等同效果的实施例。此外，附图是为了便于理解本发明并且因此不一定按比例绘制，并且为了突出本发明的其它特征，可以省略一些特征，从而使得可以更清楚地理解本发明。当结合附图阅读本说明时，所要求保护的主题的优点对于本领域技术人员而言将变得显而易见，在附图中，类似的参考标记用于指代类似的元件，并且在附图中：
图1A是展示了常规智能卡组合件和其IC模块的透视图，图1B是图1A的IC模块的一侧的放大平面图，并且图1C是图1B的IC模块的一部分的显著放大视图，所述部分的键合导线与其导电迹线接触；
图2A是根据本发明的实施例的引线框架载体的横截面侧视图，图2B是图2A的引线框架载体的一部分的仰视平面图，并且图2C是图2B的载体的所述部分的俯视平面图；
图3A示出了图2B的载体和引线框架的在将IC附接到其并利用键合导线将IC电连接到其通孔之后的顶侧，并且图3B是图3A的组合件的通孔、导电迹线和键合导线的显著放大视图；
图4A、4B、4C和4D展示了根据本发明的各个实施例的通孔和导电迹线；并且
图5是展示了根据本发明的实施例的智能卡组装过程中的各个步骤的流程图。
具体实施方式
在一个实施例中，本发明提供了一种用于组装智能卡的引线框架。所述引线框架由具有相对的第一主表面和第二主表面的基板形成。管芯收容区域在所述基板的所述第一主表面中形成并且被导电通孔包围。导电涂层在所述基板的所述第二主表面上形成并且被图案化以在所述导电通孔上形成电接触焊盘。导电迹线在所述基板的所述第一主表面上形成。所述导电迹线在至少两个相邻通孔之间延伸并且部分地包围所述至少两个相邻导电通孔，从而在所述迹线的包围所述通孔的部分中形成间隙。集成电路芯片与所述导电通孔之间的电连接在所述间隙上延伸。所述间隙防止所述电连接与所述导电迹线发生意外接触。
在另一个实施例中，本发明提供了一种智能卡，所述智能卡包括具有相对的第一主表面和第二主表面的基板和在第一主表面中形成的管芯收容区域。提供了多个导电通孔，所述多个导电通孔总体上包围管芯收容区域并且从第一主表面延伸到第二主表面。在基板的第二主表面上形成导电涂层并将其图案化以在所述多个导电通孔上形成多个电接触焊盘。在基板的第一主表面上形成至少一条导电迹线，并且所述至少一条导电迹线在至少两个相邻的通孔之间延伸。导电迹线仅部分地包围所述至少两个相邻的导电通孔。在管芯收容区域内安置集成电路芯片，并且利用在芯片的有源表面上的键合焊盘与通孔之间延伸的多个电连接将所述集成电路芯片电连接到通孔。导电迹线的部分地包围相邻导电通孔的部分被配置成使得从芯片延伸到两条相邻导电通孔的电连接在导电通孔的未被导电迹线包围的部分上延伸。
因此，本发明提供了具有用于避免和防止键合导线与导电迹线之间发生电短路的改进的导电迹线设计的智能卡。本发明提供了即使在导线下垂的情况下也能够防止键合导线接触导电迹线的优点。本发明还使得更容易控制导线环路形状。
现在参考图2A、2B和2C，图2A是根据本发明的实施例的引线框架载体100的横截面侧视图，图2B是引线框架载体100的所述部分的仰视平面图，并且图2C是引线框架载体100的所述部分的俯视平面图。引线框架载体100的所述部分包括引线框架102和轨道104，所述轨道104包括用于利用链轮(未示出)移动载体100的多个对准的孔106。载体100可以包括引线框架带或具有多于一行引线框架的带和在载体的相对侧上具有孔的另一条轨道。引线框架带100是本领域公知的类型，因此，将不详细描述引线框架带100的与对本发明的理解不特别相关的那些元件，以免模糊本发明。图2C中示出了引线框架102的轮廓108。引线框架102可以用于智能卡组装过程，如将在下文详细讨论的。引线框架102可以通过冲压或切割与载体100分离，如本领域中同样已知的。
引线框架102包括基板110，所述基板110具有第一主表面112(图2B)和相对的第二主表面114(图2C)。如本文所用的，基板是指其上施加有其它材料(例如，导电油墨、导电金属、模制化合物等)的下方物质或层或者主要材料或下方材料。基板110由如玻璃增强环氧树脂层压材料(即FR4)等非导电材料制成。
如图2B所示，在基板110的第一主表面112中形成管芯收容区域116，如总体上包围管芯收容区域116的多个导电通孔118那样。管芯收容区域116包括在引线框架102的大体上中心的位置处形成的腔。管芯收容区域116的深度可以小于基板110厚度的约一半。可替代地，腔的深度可以大于基板110的厚度的一半，并且在优选实施例中，腔完全延伸穿过基板110。导电通孔118也完全延伸穿过基板110。如本领域已知的，通孔118可以是电镀贯穿孔或者是填充有如焊料等导电材料的贯穿孔。
在当前优选的实施例中并且如图2B所示，导电通孔118包括安置在管芯收容区域116的相对侧上的两组导电通孔。例如，图2B示出了两组通孔118，其中每组包括四(4)个通孔118。如下文所讨论的，所述组由与导电迹线相关联的通孔限定。如本领域技术人员将理解的，每组通孔118的数量以及作为整体的通孔118的数量均将取决于用于组装需要访问的智能卡的集成电路的键合焊盘的数量。
在基板110的第二主表面114形成导电涂层120。将导电涂层120图案化以在导电通孔118中的相应导电通孔上形成多个电接触焊盘122(1)到122(8)。导电涂层120还覆盖管芯收容区域116的腔以形成管芯焊盘或管芯标志124，使得安置在腔内的集成电路芯片的主表面搁置在导电涂层120上。通常将管芯焊盘或标志124的大小和形状设置成收容IC芯片，即，基于芯片的大小和形状收容芯片。然而，管芯焊盘124的尺寸和形状以及IC芯片的尺寸和类型并不是本发明的一部分，因此将不在本文中进一步详细描述。
如本领域技术人员将理解的，导电涂层120的在导电通孔118上延伸的部分与在腔116上延伸的部分之间存在间隙，使得接触焊盘122彼此电绝缘并且与管芯焊盘124电绝缘。
在一个实施例中，导电涂层120包括用粘合剂(未示出)附接到基板110的第二主表面114的铜箔。导电涂层或铜箔120可以包括用于防止铜氧化的防腐蚀涂层，如Ni、Pd和/或Au。
在基板110的第一主表面112上形成至少一条导电迹线126，并且在优选实施例中，存在第一导电迹线126和第二导电迹线128(参见图2B)。导电迹线126、128中的每一条导电迹线在至少两个相邻的通孔118之间延伸并且部分地包围通孔118，但导电迹线126、128并不完全包围通孔118。
如先前所讨论的，可以将通孔118分为两组，并且将这些组限定为与所述两个导电迹线126和128中的一条导电迹线或另一条导电迹线相关联的那些通孔。因此，第一导电迹线126在第一组中的导电通孔118中的每个导电通孔之间延伸并且部分地包围第一组中的导电通孔118中的每个导电通孔，并且第二导电迹线128在第二组中的导电通孔118中的每个导电通孔之间延伸并且部分地包围第二组中的导电通孔118中的每个导电通孔。如对于本领域技术人员而言将显而易见的是，第一组通孔与接触焊盘122(1)到122(4)相关联，并且第二组通孔与接触焊盘122(5)到122(8)相关联。
简要地参考图3A和3B，图3A示出了具有集成电路(IC)芯片130的基板110的第一表面112，所述IC芯片130安置在管芯收容区域116的腔内并且用管芯附接粘合剂或管芯附接带附接到管芯标志124的内表面。IC芯片130(所述IC芯片130可以包括任何类型的集成电路，如具有较小存储的简单微处理器)在其有源表面上具有键合焊盘(未示出)，所述键合焊盘经由通孔118利用电连接装置132电连接到接触焊盘122。在优选实施例中，电连接装置包括键合导线，但在替代性实施例中，可以使用其它电连接装置，如导电油墨。
在基板110的第一主表面112上可以形成塑料模制化合物或包封剂134，其中所述包封剂覆盖IC芯片130、导电通孔118、第一电迹线126和第二导电迹线128以及在IC芯片130与导电通孔118之间的电连接132。
图3B是图3A所示组合件的通孔118、第一导电迹线126的一部分和键合导线132的显著放大视图。如所示，导电迹线126从一个通孔118延伸到另一个通孔118并且还部分地包围通孔118中的每个通孔。在一个实施例中，导电迹线围绕通孔118延伸约一半距离，并且在另一个实施例中，导电迹线围绕通孔延伸超过一半距离。然而，在每个实施例中，通孔的外周长有导电迹线不围绕延伸的间隙或部分。导电迹线126和128的部分地包围导电通孔118的部分被配置成使得从IC芯片130延伸到通孔118的键合导线132不在导电迹线上延伸。也就是说，键合导线132在导电通孔118的未被导电迹线126或128包围的部分上延伸。因此，如果键合导线132碰巧下垂或环路高度特别低，则键合导线132仍不与导电迹线发生意外接触。
图4A、4B、4C和4D展示了根据本发明的各个实施例的通孔和导电迹线。图4A示出了圆形通孔142和导电迹线144，所述导电迹线144沿通孔142的直径的一半以上延伸但仍具有用于容纳键合导线132的间隙。图4B示出了三角形通孔146和沿三角形通孔146的两侧延伸的导电迹线148，但是迹线148不沿三角形通孔146的第三侧延伸，使得键合导线132不会与键合导线132发生意外接触。图4C示出了矩形或方形通孔150和导电迹线152，所述导电迹线152完全沿矩形的一侧并且部分地沿矩形的两侧延伸并且沿两侧和朝向其的中间侧的各部分提供间隙以用于容纳键合导线132。图4D示出了圆形或环形通孔154和导电迹线156，所述导电迹线156沿通孔154的直径的仅约一半延伸并且留出用于容纳键合导线132的间隙。因此，如对于本领域技术人员而言将显而易见的是，本发明不受通孔形状的限制。
图5是展示了根据本发明的实施例的智能卡组装过程160中的各个步骤的流程图。从图5的左上侧开始，在第一步骤162中，提供了用于组装智能卡的引线框架。引线框架类似于常规的智能卡引线框架(图1B)并且在子步骤163形成。然而，在子步骤164，将根据本发明的实施例的导电迹线添加到引线框架，其中一条或多条迹线在通孔之间延伸并且部分地且不完全包围通孔，从而在键合导线将从集成电路穿到通孔的位置处留出间隙。
在步骤166，在引线框架的包封侧的管芯收容区域中放置粘合剂或管芯附接薄膜(DAF)，并且在步骤168，使用粘合剂或DAF将管芯附接在管芯收容区域中。使粘合剂固化，从而使得管芯牢固地附接到引线框架。在步骤170，将管芯电连接到引线框架中的通孔。在当前优选的实施例中，使用标准导线键合工艺将键合导线附接到管芯键合焊盘和相应的引线框架通孔。在步骤172，在管芯、键合导线和通孔上形成包封剂(参见图3A)。例如，可以执行球顶包封工艺，由此将液体包封剂分配到管芯、键合导线和通孔上。在步骤174，可以去除模制化合物/包封剂，所述步骤174是任选的。最后，在步骤176，检查成品装置。
本发明的导电迹线可以使用多种已知的方法形成，例如通过印刷和蚀刻。导电迹线仅部分地包围键合导线附接到的通孔，从而防止键合导线到导电迹线发生意外短路。
用模制化合物覆盖集成电路芯片和电连接(键合导线)，从而形成组装的装置。模制化合物为集成电路芯片、引线框架和在芯片与通孔之间的电连接提供电气和机械保护。在一个实施例中，模制化合物包括环氧树脂组合物，例如C级塑料材料(丙阶酚醛树脂)。随后使模制化合物固化成物理上硬质的，从而使得模制化合物覆盖的芯片、通孔、导电迹线和键合导线免于受潜在环境(如湿气和灰尘)影响以及机械损坏。模制化合物可以使用已知的方法(如传递模制或球顶工艺)形成在芯片上。
本发明可以应用于任何智能卡封装体或MEMS封装体并且将适于任何管芯尺寸和形状、管芯数量以及堆叠的管芯。
在描述主题的上下文中(尤其在以下权利要求书的上下文中)使用术语“一个/一种(a/an)”和“所述(the)”和类似指示物应被解释为覆盖单数和复数两者，除非本文中另有指示或者与上下文明显矛盾。除非本文中另有指示，否则本文中对值的范围的列举仅旨在用作单独参考落入所述范围内的每个单独值的速记方法，并且每个单独值被并入说明书中，就如同每个单独值在本文中被单独列举一样。
此外，前述描述仅出于说明目的并且不用于限制，因为所寻求的保护范围是由如下文阐述的权利要求书与其有权获得的任何等同物一起限定的。除非另有声明，否则任何和全部例子或本文所提供的示例性语言(例如，“如”)的使用仅旨在更好地说明主题并且不构成对主题的范围的限制。在权利要求书和书面描述两者中使用指示产生结果的条件的术语“基于”和其它类似短语并不旨在排除产生所述结果的任何其它条件。说明书中的任何语言均不应被解释为将任何未要求保护的要素指示为是实践如所要求保护的本发明所必须的。
本文中描述了优选实施例，包括发明人已知的用于执行所要求保护的主题的最佳模式。当然，对于本领域普通技术人员而言，在阅读前述描述后，这些优选实施例的变化将变得显而易见。发明人期望技术人员根据需要采用这些变化，并且发明人希望以与本文具体描述不同的方式实践所要求保护的主题。因此，在适用法律允许的情况下，该要求保护的主题包括所附权利要求中列举的主题的所有修改和等同物。此外，除非本文中另有指示或者与上下文明显矛盾，否则包括上述要素在其所有可能的变化的情况下的任何组合。

Claims (10)

1.一种用于组装智能卡的引线框架，其特征在于，所述引线框架包括：
基板，所述基板具有相对的第一主表面和第二主表面；
管芯收容区域，所述管芯收容区域在所述基板的所述第一主表面中形成；
多个导电通孔，所述多个导电通孔总体上包围所述管芯收容区域；
导电涂层，所述导电涂层在所述基板的所述第二主表面上形成，其中所述导电涂层被图案化以在所述多个导电通孔上形成多个电接触焊盘；以及
至少一条导电迹线，所述至少一条导电迹线在所述基板的所述第一主表面上形成，其中所述导电迹线在至少两个相邻通孔之间延伸，并且其中所述导电迹线不完全包围所述至少两个相邻导电通孔。
2.根据权利要求1所述的引线框架，其特征在于，所述至少一条导电迹线围绕所述至少两个相邻导电通孔延伸约一半距离。
3.根据权利要求1所述的引线框架，其特征在于，所述导电迹线的部分地包围所述至少两个相邻导电通孔的部分被配置成使得从集成电路芯片延伸到所述至少两个相邻导电通孔的键合导线在所述导电通孔的未被所述导电迹线包围的部分上延伸。
4.根据权利要求1所述的引线框架，其特征在于：
所述多个导电通孔包括两组导电通孔，所述两组导电通孔安置在所述管芯收容区域的相对侧上；并且所述至少一条导电迹线包括第一导电迹线和第二导电迹线，所述第一导电迹线在所述第一组中的所述导电通孔中的每个导电通孔之间延伸并且部分地包围所述第一组中的所述导电通孔中的每个导电通孔，所述第二导电迹线在所述第二组中的所述导电通孔中的每个导电通孔之间延伸并且部分地包围所述第二组中的所述导电通孔中的每个导电通孔。
5.根据权利要求1所述的引线框架，其特征在于，所述管芯收容区域包括深度小于所述基板的厚度的约一半的腔。
6.根据权利要求1所述的引线框架，其特征在于，在所述基板的所述第二主表面上形成的所述导电涂层在所述腔上延伸，使得安置在所述腔内的集成电路芯片的主表面搁置在所述导电涂层上。
7.一种智能卡，其特征在于，包括：
基板，所述基板具有相对的第一主表面和第二主表面；
管芯收容区域，所述管芯收容区域在所述基板的所述第一主表面中形成；
多个导电通孔，所述多个导电通孔总体上包围所述管芯收容区域，其中所述导电通孔从所述第一主表面延伸到所述第二主表面；
导电涂层，所述导电涂层在所述基板的所述第二主表面上形成，其中所述导电涂层被图案化以在所述多个导电通孔上形成多个电接触焊盘；
至少一条导电迹线，所述至少一条导电迹线在所述基板的所述第一主表面上形成，其中所述导电迹线在至少两个相邻通孔之间延伸，并且其中所述导电迹线不完全包围所述至少两个相邻导电通孔；
集成电路芯片，所述集成电路芯片安置在所述管芯收容区域内；以及
多个电连接，所述多个电连接将所述集成电路芯片电连接到所述导电通孔中的相应导电通孔。
8.根据权利要求7所述的智能卡，其特征在于，所述至少一条导电迹线的部分地包围所述至少两个相邻导电通孔的部分被配置成使得从所述集成电路芯片延伸到所述至少两个相邻导电通孔的所述电连接在所述至少两个相邻导电通孔的未被所述导电迹线包围的部分上延伸。
9.根据权利要求7所述的智能卡，其特征在于：
所述多个导电通孔包括两组导电通孔，所述两组导电通孔安置在所述管芯收容区域的相对侧上；并且
所述至少一条导电迹线包括第一导电迹线和第二导电迹线，所述第一导电迹线在所述第一组中的所述导电通孔中的每个导电通孔之间延伸并且仅部分地包围所述第一组中的所述导电通孔中的每个导电通孔，所述第二导电迹线在所述第二组中的所述导电通孔中的每个导电通孔之间延伸并且仅部分地包围所述第二组中的所述导电通孔中的每个导电通孔。
10.根据权利要求7所述的智能卡，其特征在于，另外包括在所述基板的所述第一主表面上形成的包封剂，所述包封剂覆盖所述集成电路芯片、所述多个导电通孔、所述至少一条导电迹线和在所述集成电路芯片与所述多个导电通孔之间的所述电连接。
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