CN111554643A - 用于倒装芯片球栅阵列的散热器设计 - Google Patents

用于倒装芯片球栅阵列的散热器设计 Download PDF

Info

Publication number
CN111554643A
CN111554643A CN202010085306.7A CN202010085306A CN111554643A CN 111554643 A CN111554643 A CN 111554643A CN 202010085306 A CN202010085306 A CN 202010085306A CN 111554643 A CN111554643 A CN 111554643A
Authority
CN
China
Prior art keywords
section
cavity
silicon chip
substrate
fcbga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010085306.7A
Other languages
English (en)
Inventor
高华宏
C·柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marvell Asia Pte Ltd
Original Assignee
Marvell Asia Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell Asia Pte Ltd filed Critical Marvell Asia Pte Ltd
Publication of CN111554643A publication Critical patent/CN111554643A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3672Foil-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/32Holders for supporting the complete device in operation, i.e. detachable fixtures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736Metallic materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本公开的各实施例涉及用于倒装芯片球栅阵列的散热器设计。倒装芯片球栅阵列(FCBGA)包括基板、腔形成环形加强件、外部散热器和热界面材料。腔形成环形加强件设置在基板上。腔形成环形加强件具有与基板形成空腔并暴露硅芯片的顶部的部分。外部散热器设置在硅芯片上和腔形成环形加强件的区段上。热界面材料将腔形成环形加强件的区段和硅芯片的顶部与外部散热器分离,并将热量从硅芯片传导至外部散热器。

Description

用于倒装芯片球栅阵列的散热器设计
相关申请的交叉引用
本公开要求于2019年2月8日提交的名称为“EXPOSED-DIE HEAT-SINK DESIGN”的美国临时申请序列号62/803,204的优先权的权益,其全部内容通过引用合并于此。
技术领域
本公开涉及一种用于倒装芯片球栅阵列(FCBGA)的散热器设计,即,设置在腔形成环形加强件上的外部散热器,该腔形成环形加强件与FCBGA的基板形成腔。腔形成环形加强件支撑外部散热器,暴露FCBGA上的硅芯片的顶部,并增加FCBGA的机械刚度。
背景技术
本文所提供的背景描述是为了总体上呈现本公开内容的目的。在此背景技术部分中所描述的工作的范围内,以及在申请时在其他情况下可能不能视为现有技术的描述内容,均未明确或暗含承认为针对本公开的现有技术。
倒装芯片球栅阵列(FCBGA)是一种半导体封装,其具有设置在基板一侧的硅芯片和设置在基板另一侧的球形栅阵列。球栅阵列可将FCBGA安装在印刷电路板上。硅芯片在操作期间发生成热量。需要将热量从硅芯片耗散到诸如空气的流体介质,以便硅芯片在最佳温度下工作。
发明内容
本公开涉及用于倒装芯片球栅阵列(FCBGA)的散热器设计,即,外部散热器,其布置在腔形成环形加强件上,该腔形成环形加强件与FCBGA的基板形成腔。腔形成环形加强件支撑外部散热器,暴露FCBGA基板上的硅芯片顶部,并为FCBGA基板增加机械刚度。热量从硅芯片传递到外部散热器,以通过一层热界面材料耗散到诸如空气的流体介质中,该热界面材料将硅芯片和腔体环形加强件与外部散热器分离。
本公开的方面提供了一种倒装芯片球栅阵列(FCBGA),其包括:基板,具有硅芯片;腔形成环形加强件,设置在基板上,该腔形成环形加强件具有与基板形成腔并暴露硅芯片的顶部的部分;热界面材料,设置在腔形成环形加强件的区段上和硅芯片上;以及外部散热器,设置在热界面材料上。
在一个示例中,区段暴露硅芯片的顶部的部分。在另一个示例中,腔形成环形加强件的区段的高度低于或高于硅芯片的高度。在又一示例中,该区段是第一区段,腔形成环形加强件包括沿着基板的外围布置的第二区段,第二区段通过阶梯过渡而过渡到第一区段。在另一个示例中,腔形成环形加强件从基板的外围到基板的中心具有均匀的高度。在又一示例中,该区段是第一区段,腔形成环形加强件包括附接到第一区段的第二区段。在另一个示例中,第二段沿着基板的外围设置。在又一个示例中,热界面材料是热油脂或导热焊盘。在另一示例中,腔形成环形加强件的区段的高度与硅芯片的高度相同。在又一个示例中,区段具有暴露基板上具有集成电路或探针焊盘的区域的长度。在另一示例中,外部散热器包括垂直于腔形成环形加强件的区段的一个或多个散热片。在又一示例中,外部散热器包括在外部散热器的底部上的凹槽或凸起,该凹槽或凸起在硅芯片上方。
本公开的各方面提供了一种方法,该方法包括:在倒装芯片球栅阵列(FCBGA)的基板上设置腔形成环形加劲件,该腔形成环形加强件具有与基板形成腔并暴露基板上的硅芯片的顶部的区段;将热界面材料设置在腔形成环形加强件的区段上和硅芯片的顶部上;以及在热界面材料上设置外部散热器。
在一个示例中,区段暴露硅芯片的顶部的部分。在另一示例中,将腔形成环形加强件设置在基板上的方法包括:将腔形成环形加强件的区设置在比硅芯片更低或更高的高度处。在又一个示例中,热界面材料的厚度是均匀的。在另一个示例中,外部散热器包括在外部散热器的底部上的凹槽或凸起,该凹槽或凸起在硅芯片上方。在又一个示例中,该区段是第一区段,该方法还包括将第一区段固定到沿着所述基板的外围设置的第二区段。在另一个示例中,该区段是第一区段,腔形成环形加强件包括沿着基底的外围布置的第二区段,第二区段通过阶梯过渡而过渡到第一区段。在又一个示例中,该方法还包括将FCBGA安装在印刷电路板上。
附图说明
图1A-1C示出了具有示例散热片设计的示例倒装芯片球栅阵列(FCBGA)的各种示例视图。
图2A和图2B示出了示例FCBGA的示例俯视图和示例侧视图,该示例FCBGA具有未覆盖示例性FCBGA的基板上的区域的示例腔形成环形加强件。
图3A-图B示出了具有不同高度的示例腔形成环形加强件的示例侧视图。
图4示出了示例外部散热器的示例侧视图,该示例外部散热器设置在示例腔形成环形加强件上,示例腔形成环形加强件高于硅芯片。
图5A和5B示出了具有均匀高度的示例腔形成环形加强件的各种示例性视图。
图6示出了具有均匀高度的另一示例腔形成环形加强件的示例侧视图。
图7是与示例腔形成环形加强件和在FCGBA的基板上的示例外部散热器的组装相关联的示例功能的流程图。
附图是出于图示示例实施例的目的,但是应当理解,实施例不限于附图中所示的布置和手段。
具体实施方式
以下描述包括体现本公开的各方面的示例系统、方法、技术和程序流程。然而,应理解,可以在没有这些具体细节的情况下实践本公开。例如,本公开涉及用于倒装芯片球栅阵列(FCBGA)的示例散热器设计,即,外部散热器和腔形成环形加强件,该腔形成环形加强件与FCBGA的基板形成腔。本公开的各方面可以应用于除FBGA之外的半导体封装,并且在其他情况下,未详细示出公知的情况、结构和技术,以便不使描述模糊。
概述
设置有热量散布器和外部散热器的FCBGA将热量从FCBGA上的硅芯片耗散到诸如空气的流体介质,从而使硅芯片在最佳温度下工作。热量散布器被布置在FCBGA的硅芯片上方以完全覆盖硅芯片的顶部,其中热量散布器的支撑端耦合到FCBGA的基板。此外,诸如硅脂的第一层热界面材料设置在硅芯片和热量散布器之间,以将热量从硅芯片传递到热量散布器。为了将热量耗散到空气中,外部散热器通过第二层热界面材料(例如,导热焊盘)接触热量散布器,以将热量从热量散布器传递到外部散热器。外部散热器包括一个或多个垂直于散热器定向的板,诸如散热片,以允许热量流入散热片以用于耗散到空气中。
经由第一层热界面材料层从硅芯片流到热量散布器的热量是将热量从硅芯片传递到外部散热器的瓶颈。为了减少该瓶颈,公开了用于FCBGA的散热器设计。散热器设计具有外部散热器和腔形成环形加强件,该腔形成环形加强件与FCBGA的基板形成腔。外部散热器可以设置在FCBGA的腔形成环形加强件和硅芯片上,其中一层热界面材料将腔形成环形加强件和硅芯片与外部散热器分开。热量经由热界面材料层从硅芯片传递到外部散热器,从而耗散到诸如空气的流体介质中。
所公开的散热器结构消除了在散热器和硅芯片之间管理FCBGA上的热量所需的热界面材料层,并减小了与壳体连接(例如,硅芯片至外部散热器)的热阻。来自硅芯片的热量不会通过第一层热界面材料从硅芯片传递到热量散布器,然后再通过第二层热界面材料从热量散布器传递到外部散热器。相反,热量通过单层热界面材料从硅芯片传递到外部散热器。所公开的用于FCBGA的外部散热器也提供了其他优点。
示例图示
图1A-图1C示出了具有示例散热器设计的示例倒装芯片球栅阵列(FCBGA)的各种示例视图。图1A和图1B分别示出了FCBGA的腔形成环形加强件128的侧视图100和俯视图150。此外,图1C示出了FCBGA的外部散热器130,其布置在腔形成环形加强件128上。与图1A和图1C相关联的视图可以与x或y维度相关联,x或y维度在假设FCBGA对称的情况下可能是相同的,但在其他示例中视图可能因尺寸而异。视图中相似的组件标有相似的附图标记。
FCBGA具有设置在基板120的一侧上的硅芯片110和设置在基板120的另一侧上的球栅格阵列122。硅芯片110可以是使用受控塌陷芯片连接设置在基板120上的集成电路。受控塌陷芯片连接或其缩写C4是一种用于通过沉积在芯片焊盘上的焊料凸点将诸如硅芯片110的半导体器件与诸如基板120的电路互连的方法。设置在基板120的另一侧上的球栅阵列122是用于集成电路的一种表面安装封装。球栅阵列122允许将FCBGA表面安装至印刷电路板(未示出)。
硅芯片110可在操作期间生成热量。为了使硅芯片在最佳温度下工作,可以将外部散热器130放置在腔形成环形加强件128和硅芯片110上。外部散热器130可以将硅芯片110在操作期间生成的热量传递到诸如空气的流体介质,以用于从硅芯片110中耗散。
腔形成环形加强件128可以是由诸如具有镍镀层或铝的铜的金属制成的刚性单件结构。腔形成环形加强件128可以由第一区段102、阶梯过渡104或下阶梯和第二区段106限定,其中的每个由虚线分开,并且,为了便于说明,针对腔形成环形加强件128的一侧示出了第一区段102、阶梯过渡104或下阶梯以及第二区段106,但腔形成环形加强件128的两侧可以类似地构成。在示例中,第一区段102、阶梯过渡104或下阶梯以及第二区段106可以各自具有0.3mm至4mm的厚度。至少第二区段106和基板120可以形成腔112,并且在示例中,第一区段102可以低于第二区段106。第一区段102可以沿着基板120的外围设置以支撑腔形成环形加强件,并且第二区段106可以基本上平行于基板120以高度H定向。阶梯过渡104可以促进从处于不同高度的第一区段102到第二区段106的过渡。如顶视图150所示,具有长度L的第二区段106可以暴露硅芯片110的顶部134。暴露可以是区段106覆盖顶部134的一部分或者根本不覆盖顶部134。在示例中,第二区段106的长度L可以在顶视图150中在硅芯片110和第二区段106之间限定槽108。
腔形成环形加强件128进一步支撑外部散热器130并增加机械刚度以防止基板120翘曲。与不形成腔112的环形结构相比,刚性增加。如图1C所示的外部散热器130连同形成腔环形加强件128也可以由各种金属制成,诸如具有镀镍的铜或铝。外部散热器130可以设置在腔形成环形加强件128的第二区段106上和硅芯片110的顶部134上,并由热界面材料层132隔开。在示例中,热界面材料层132可以具有均匀的厚度。热界面材料132可以是具有促进热传导的热阻的材料,例如具有硅基填充物的导热油脂或诸如石墨焊盘的导热焊盘,其厚度在几十微米的范围内。热油脂(也称为导热膏、散热复合物、散热膏、热复合物、热胶、热界面材料或热膏)是导热的(但通常是电绝缘的)复合物。导热油脂的作用可能是消除界面区域的气隙或空隙(起到隔热作用),以最大程度地提高热传递和散热。热界面材料132可以传导来自硅芯片110的热量,该硅芯片110是通过腔形成环形加强件128而暴露于外部散热器130。为了将热量散发到空气中,外部散热器130可包括在外部散热器130的顶部上的一个或多个板124,诸如散热片。在一些示例中,散热片可以被定向为垂直于形成环形加强件128的腔的第二区段106。热量从硅芯片110流过热界面材料132,并从外部散热器130的板124流动以用于散发到空气中。
腔形成环形加强件128的第二区段106可以具有长度L,该长度L以不同的量暴露硅芯片110的顶部134。在一些示例中,腔形成环形加强件128的第二区段106的长度L可以被确定尺寸,使得第二区段106不覆盖硅芯片110的顶部134并且不覆盖基板120上的邻近区域。只要没有将外部散热器130和热界面材料132设置在腔形成环形加强件128的上,就不会覆盖硅芯片110。该区域未被覆盖,从而允许从上方进入该区域。
图2A和图2B示出了示例FCBGA的示例侧视图200和示例俯视图250,示例FCBGA具有示例腔形成环形加强件128,该腔形成环形加强件128具有第二区段106,该第二区段106不覆盖示例FCBGA的基板120上的区域202。在示例中,区域202可以具有耦合到硅芯片110的探针焊盘,以探测硅芯片110和/或集成电路。腔形成环形加强件128的第二区段106可以具有长度L,以便不在区域202上方延伸以覆盖区域202。此外,第二区段106可以不覆盖硅芯片110的顶部。硅芯片110和第二区段106之间的槽108可以采用不同的形状。顶视图250中示出的形状是圆形,其指示长度L可以沿着硅芯片110周围的x或y维度变化,但是该形状可以采取包括矩形或椭圆形的其他形式。当外部散热器130(未示出)未布置在腔形成环形加强件128上时,槽108可允许从上方进入区域202。
在以上示例中,腔形成环形加强件128的高度和硅芯片110的顶部的高度可以相同,例如,第二区段106和硅芯片110的顶部在同一平面中。在其他示例中,腔形成环形加强件128的第二区段106可以在硅芯片110的顶部下方或上方。
图3A和图3B示出了具有不同高度的示例腔形成环形加强件128的示例侧视图。在图3A中,腔形成环形加强件128的第二区段106可以高于硅芯片110的高度。在图3B中,腔形成环形加强件128的第二区段106可以低于硅芯片110的高度。可以修改外部散热器130以考虑硅芯片110的顶部和腔形成环形加强件128的第二区段106的高度之间的高度差。
图4示出了示例外部散热器130的示例侧视图,该示例外部散热器130设置在示例腔形成环形加强件128上,示例腔形成环形加强件128的第二区段106高于硅芯片110的高度。外部散热器130的底部308可以在硅芯片110上形成有突出302。突出302可以由与外部散热器130相同的材料或不同的材料制成。热界面材料306可以设置在外部散热器130和硅芯片110之间以及在外部散热器130和第二区段106之间。与不具有突出部302的外部散热器130相比,突出302可以减小硅芯片110和外部散热器130之间所需的热界面材料306的厚度。例如,当外部散热器设置在第二区段106上和硅芯片110上时,硅芯片110之间的热界面材料306的厚度和支撑件106与外部散热器130之间的热材料的厚度可以基本相同或均匀。第二区段106高于硅芯片的顶部110在处理FCBGA期间还可允许保护硅芯片110。对FCBGA的任何冲击将由示例腔形成环形加强件128而不是硅芯片110吸收。如果示例腔形成环形加强件128的第二区段106低于硅芯片110的高度,则外部散热器130的底部308的一部分可以是在硅芯片110(未示出)上形成有凹槽。热界面材料306可以设置在外部散热器130与硅芯片110之间以及在外部散热器130与第二区段106之间。外部散热器130的底部上的凹槽可以提供用于增加厚度的空间。与没有凹槽的外部散热器130相比,硅芯片110和外部散热器130之间的热界面材料的热导率降低。例如,当外部散热器设置在第二区段106上和硅芯片110上时,硅芯片110之间的热界面材料306的厚度和支撑件106与外部散热器130之间的热材料的厚度可以基本相同或均匀。其他变化也是可能的。
图5A和图5B示出了示例腔形成环形加强件128的示例侧视图500和示例顶视图550,该示例腔体形成加强件128具有均匀的高度,其被设置在FCBGA的基板120上。视图可以与x或y维度相关联,假设FCBGA的对称性该x或y维度可以相同,但是在其他示例中,视图可以根据维度而有所不同。示例腔形成环形加强件128可以是由第一区段502和第二区段504限定的脊状整体结构。第一区段502可以沿着基板120的外围506定位。第二区段504被示出为与硅芯片110的顶部的高度相同,但是在其他示例中可以低于或高于硅芯片110的顶部。第二区段504可以在长度方向L的纵向上基本上平行于基板120定向,以形成腔112。另外,第二区段504可以在基板120上方从基板506的外围506的均匀高度处。基板120朝向基板120的中心508,在硅芯片110和第二区段504之间具有槽510。在示例中,外部散热器130(未示出)可以设置在腔形成环形加强件128的第二区段504上,其中热界面材料将腔形成环形加强件128的第二区段504和硅芯片110的顶部与外部散热器130分开。支撑外部散热器130的第二区段504的区域可以因为在腔形成环形加强件128的该示例中不存在阶梯过渡104,所以大于第二区段106的面积。此外,。在一些示例中,第一区段502的可以具有比第二区段504更大的厚度,以增加腔形成环形加强件128在支撑外部散热器130中的稳定性。
在一些示例中,腔形成环形加强件128可以由联接在一起的多个区段制成,而不是由一件式结构制成。
图6示出了具有均匀高度的腔形成环形加强件128的另一示例的示例侧视图。示例腔形成环形加强件128可以是由固定在界面606处的第一区段602和第二区段604限定的脊状两件式结构。该两个区段602、604可以例如,在界面606处通过粘合剂连接或机械连接来固定。区段602可以是沿着基板120的外围608的常规环形加强件,在其顶部上布置有区段604以形成形成腔的环形加强件128。区段604可以被定向为在长度L视图的纵向上基本上平行于基板120。此外,区段604可以在从基板120的外围608朝向基板120的中心610在基板120上方均匀的高度处。例如,外部散热器130(未示出)可以设置在腔形成环形加强件128的区段604上,其中热界面材料将硅芯片110和区段604分开。区段604可以是用于外部散热器130的支撑。
在以上示例中,示例腔形成环形加强件128被描述为暴露硅芯片110的顶部134。在其他示例中,示例腔形成环形加强件128可进一步接触硅芯片110,例如,示例腔形成环形加强件128的区段106、504或604接触硅芯片110。与硅芯片110的接触可以导致示例腔形成环形加强件128将热量从硅芯片110传导到FCBGA的基板120并通过热界面材料132从硅芯片110传递到外部散热器130。
示例功能
图7是与示例腔形成环形加强件128和示例外部散热器130在FCGBA上的组装相关联的示例功能的流程图700。
在702处,将示例腔形成环形加强件128设置在FCBGA的基板120上。示例腔形成环形加强件128可以暴露FCBGA的硅芯片110的顶部。示例腔形成环形加强件128还可以相对于基板120限定腔。示例腔形成环形加强件128可以由诸如镀有镍或铝的铜的金属制成。
在704处,将热界面材料设置在(i)示例腔形成环形加强件128的区段上,其用于支撑外部散热器130,并且(ii)在FCBGA的硅芯片110的顶部上。上面示出并描述了示例腔形成环形加强件的该区段的示例。热界面材料132可以是具有硅填充物以改善导热性的热油脂,或者可以是诸如导热垫的其他材料,在一些示例中,导热垫可以是十微米厚的倍数。
在706处,外部散热器130设置在热界面材料132上,以将热量从硅芯片110经由热界面材料132传递到外部散热器130。外部散热器130还可以具有例如散热片的板124,以将热量从硅芯片110传导到空气中。
在708处,将FCBGA表面安装在印刷电路板上。在示例中,基板120的球栅阵列122可以有助于将FCBGA安装到印刷电路板上。
除非明确说明,否则在列表之前使用短语“至少”与连词“和”不应视为排他性列表,也不应将其解释为具有每个类别中一项的类别列表。除此以外。引用“A、B和C中的至少一个”的子句只能侵犯所列项目中的一项、所列项目中的多项、以及列表中一项或多项以及未列出的另一项。
虽然已经结合作为示例提出的本公开的特定实施例描述了本公开的各方面,但是可以对示例进行替代、修改和变化。因此,本文阐述的实施例旨在说明而不是限制。在不脱离下面阐述的权利要求的范围的情况下可以进行改变。

Claims (20)

1.一种倒装芯片球栅阵列FCBGA,包括:
基板,具有硅芯片;
腔形成环形加强件,被设置在所述基板上,所述腔形成环形加强件具有与所述基板形成所述腔并暴露所述硅芯片的顶部的区段;
热界面材料,被设置在所述腔形成环形加强件的所述区段和所述硅芯片上;以及
外部散热器,被设置在所述热界面材料上。
2.根据权利要求1所述的FCBGA,其中区段暴露所述硅芯片的所述顶部的一部分。
3.根据权利要求1所述的FCBGA,其中所述腔形成环形加强件的所述区段的高度低于或高于所述硅芯片的高度。
4.根据权利要求1所述的FCBGA,其中所述区段是第一区段,所述腔形成环形加强件包括沿着所述基板的外围布置的第二区段,所述第二区段通过阶梯过渡而过渡到所述第一区段。
5.根据权利要求1所述的FCBGA,其中所述腔形成环形加强件从所述基板的外围到所述基板的中心具有均匀的高度。
6.根据权利要求5所述的FCBGA,其中所述区段是第一区段,所述腔形成环形加强件包括附接到所述第一区段的第二区段。
7.根据权利要求6所述的FCBGA,其中所述第二区段沿着所述基板的外围而被设置。
8.根据权利要求1所述的FCBGA,其中所述热界面材料是热油脂或导热焊盘。
9.根据权利要求1所述的FCBGA,其中所述腔形成环形加强件的所述区段的高度与所述硅芯片的高度相同。
10.根据权利要求1所述的FCBGA,其中所述区段具有暴露在所述基板上具有集成电路或探针焊盘的区域的长度。
11.根据权利要求1所述的FCBGA,其中所述外部散热器包括垂直于所述腔形成环形加强件的所述区段的一个或多个散热片。
12.根据权利要求1所述的FCBGA,其中所述外部散热器包括在所述外部散热器的底部上的凹槽或凸起,所述凹槽或所述凸起在所述硅芯片上方。
13.一种方法,包括:
在倒装芯片球栅阵列FCBGA的基板上设置腔形成环形加强件,所述腔形成环形加强件具有与所述基板形成型腔并暴露所述基板上的硅芯片的顶部的区段;
将热界面材料设置在所述腔形成环形加强件的所述区段和硅芯片的所述顶部上;和
在所述热界面材料上放置外部散热器。
14.根据权利要求13所述的方法,其中区段暴露所述硅芯片的所述顶部的一部分。
15.根据权利要求13所述的方法,其中将所述腔形成环形加强件设置在所述基板上包括:将所述腔形成环形加强件的所述区段设置在比所述硅芯片更低或更高的高度处。
16.根据权利要求13所述的方法,其中所述热界面材料的厚度是均匀的。
17.根据权利要求13所述的方法,其中所述外部散热器包括在所述外部散热器的底部上的凹槽或突起,所述凹槽或突起在所述硅芯片上方。
18.根据权利要求13所述的方法,其中所述区段是第一区段,所述方法还包括将所述第一区段固定到沿着所述基板的外围设置的第二区段。
19.根据权利要求13所述的方法,其中所述区段是第一区段,所述腔形成环形加强件包括沿着所述基板的外围设置的第二区段,所述第二区段通过阶梯过渡而过渡到所述第一区段。
20.根据权利要求13所述的方法,还包括将所述FCBGA安装在印刷电路板上。
CN202010085306.7A 2019-02-08 2020-02-10 用于倒装芯片球栅阵列的散热器设计 Pending CN111554643A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962803204P 2019-02-08 2019-02-08
US62/803,204 2019-02-08
US16/784,869 US11282762B2 (en) 2019-02-08 2020-02-07 Heat sink design for flip chip ball grid array
US16/784,869 2020-02-07

Publications (1)

Publication Number Publication Date
CN111554643A true CN111554643A (zh) 2020-08-18

Family

ID=69570514

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010085306.7A Pending CN111554643A (zh) 2019-02-08 2020-02-10 用于倒装芯片球栅阵列的散热器设计

Country Status (4)

Country Link
US (1) US11282762B2 (zh)
EP (1) EP3693991B1 (zh)
KR (1) KR20200097659A (zh)
CN (1) CN111554643A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11830785B2 (en) * 2021-10-06 2023-11-28 STATS ChipPAC Pte. Ltd. Package with windowed heat spreader

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724080B1 (en) 2002-12-20 2004-04-20 Altera Corporation Heat sink with elevated heat spreader lid
TWI249232B (en) * 2004-10-20 2006-02-11 Siliconware Precision Industries Co Ltd Heat dissipating package structure and method for fabricating the same
TWI246759B (en) * 2004-11-16 2006-01-01 Siliconware Precision Industries Co Ltd Heat dissipating package structure and fabrication method thereof
TW200802629A (en) * 2006-06-12 2008-01-01 Siliconware Precision Industries Co Ltd Heat sink package structure and method for fabricating the same
TWI343103B (en) * 2007-06-13 2011-06-01 Siliconware Precision Industries Co Ltd Heat dissipation type package structure and fabrication method thereof
US8115303B2 (en) * 2008-05-13 2012-02-14 International Business Machines Corporation Semiconductor package structures having liquid coolers integrated with first level chip package modules
US8216887B2 (en) * 2009-05-04 2012-07-10 Advanced Micro Devices, Inc. Semiconductor chip package with stiffener frame and configured lid
US9478476B2 (en) 2011-12-16 2016-10-25 Intel Corporation Package for a microelectronic die, microelectronic assembly containing same, microelectronic system, and method of reducing die stress in a microelectronic package
US9257364B2 (en) 2012-06-27 2016-02-09 Intel Corporation Integrated heat spreader that maximizes heat transfer from a multi-chip package
US10573579B2 (en) 2017-03-08 2020-02-25 Mediatek Inc. Semiconductor package with improved heat dissipation

Also Published As

Publication number Publication date
US11282762B2 (en) 2022-03-22
KR20200097659A (ko) 2020-08-19
US20200258807A1 (en) 2020-08-13
EP3693991B1 (en) 2024-04-03
EP3693991A1 (en) 2020-08-12

Similar Documents

Publication Publication Date Title
US5430611A (en) Spring-biased heat sink assembly for a plurality of integrated circuits on a substrate
US6462410B1 (en) Integrated circuit component temperature gradient reducer
US6365964B1 (en) Heat-dissipating assembly for removing heat from a flip chip semiconductor device
US5880524A (en) Heat pipe lid for electronic packages
US7813133B2 (en) Semiconductor device
US7352585B2 (en) Flip chip heat sink package and method
US9922902B2 (en) Semiconductor device and semiconductor package
US7561425B2 (en) Encapsulated multi-phase electronics heat-sink
US20040095727A1 (en) Thermal heat spreaders designed for lower cost manufacturability, lower mass and increased thermal performance
US6657864B1 (en) High density thermal solution for direct attach modules
US12027433B2 (en) Semiconductor package and method for making the same
US20060113663A1 (en) Heat stud for stacked chip package
US8304922B2 (en) Semiconductor package system with thermal die bonding
EP3051584A1 (en) Heat spreader with down set leg attachment feature
CN213752684U (zh) 具有竖直热管理的堆叠式硅封装组件
US5525835A (en) Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element
US6534860B2 (en) Thermal transfer plate
US11587887B2 (en) Semiconductor device and manufacturing method thereof
CN111554643A (zh) 用于倒装芯片球栅阵列的散热器设计
KR102667427B1 (ko) 반도체 패키지 시스템
JPH1168360A (ja) 半導体素子の冷却構造
US20240363473A1 (en) Thermal management systems and methods for semiconductor devices
US11973000B2 (en) Heat dissipation plate and semiconductor device
JPH04299849A (ja) 半導体装置
EP4456128A1 (en) Thermal management systems and methods for semiconductor devices

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination