CN111540709A - Method for integrally preparing two-dimensional semiconductor device circuit - Google Patents
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- CN111540709A CN111540709A CN202010377198.0A CN202010377198A CN111540709A CN 111540709 A CN111540709 A CN 111540709A CN 202010377198 A CN202010377198 A CN 202010377198A CN 111540709 A CN111540709 A CN 111540709A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
- H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
Abstract
The invention provides a method for integrally preparing a two-dimensional semiconductor device circuit, belonging to the technical field of semiconductor device preparation. According to the invention, the metal sacrificial layer and the high-k material are innovatively introduced, the metal patterned electrode and the dielectric layer are firstly prepared into an integrated structure on the metal sacrificial layer, then the structure is stripped, and the integrated structure is transferred to the surface of the two-dimensional material by using a back-position transfer technology to form the whole structure of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor device preparation, and particularly relates to a method for integrally preparing a two-dimensional semiconductor device circuit.
Background
With the continuous and deep development of informatization, computer systems put higher demands on computing chips, and for bottom-layer devices, new miniaturized and portable computing equipment requires devices with smaller size and lower power consumption. The characteristic length of the device can be expressed as
Two-dimensional materials, such as graphene, tungsten disulfide, etc., due to their atomic thickness (t)2D) The method has great advantages in reducing the characteristic length and improving the integration level. The two-dimensional heterojunction combined by van der waals force avoids the harsh conditions of traditional epitaxial growth, and a new generation of FET devices based on two-dimensional materials already show the advantages of low subthreshold swing (high-frequency operation, low power consumption), high on-off ratio (high signal-to-noise ratio) and the like; in addition, the two-dimensional material solves the short channel effect caused by miniaturization of the device while maintaining the process compatibility of the silicon-based integrated circuit. Therefore, the two-dimensional material is attracting attention as the next-generation semiconductor material in academic and industrial fields.
However, in the current semiconductor device based on the two-dimensional material, due to the contact between a channel and a gate dielectric layer, the mobility is sharply reduced because of serious interface scattering; in addition, the problems of interface chemical doping, Fermi level pinning and the like exist at the source-drain contact position, and the device performance is severely restricted by the problems. The interface scattering is mainly caused by the coulomb interaction of interface ionized impurities and channel carriers, and two means are available for reducing the interface scattering: weakened ionized impurity density nCIAnd increasing the carrier concentration n in the channele. Conventional SiO2The surface has a large number of dangling bonds, nCIVery high, dielectric layer modulation of generated neIs low and is not suitable for being used as a dielectric layer of a two-dimensional material.Researchers have introduced a dielectric layer with a high dielectric coefficient (high-k) for top gate control, but the conventional preparation method usually employs ALD technology to directly deposit the dielectric layer on the surface of the two-dimensional material, and the dielectric environment introduced by this method will damage the two-dimensional material itself due to thermal treatment, and introduce defect states. There are two main approaches to solving the problems of chemical doping and fermi level pinning at the interface: the evaporation annealing process of the electrode and the transfer of buffer material at the gold half interface (Tao, S.Ji-Chang, R., Xinyi, L., Shuang, L., Wei L., J.Am.chem.Soc.2019,141,7, 3110-. However, the optimization of the evaporation annealing process still causes damage to the contact interface; although the transfer buffer material can eliminate the damage of evaporation on the surface of the material, the transmission speed of carriers in the buffer layer is far lower than that in a metal electrode, and the mobility and the switching characteristic of a device are influenced.
Therefore, how to realize a two-dimensional semiconductor device to obtain high mobility and low impedance gold half contact, thereby reducing the power consumption of the device and increasing the switching speed of the device becomes a problem to be solved urgently.
Disclosure of Invention
In view of the problems in the background art, the present invention is directed to a method for integrally manufacturing a two-dimensional semiconductor device circuit. According to the invention, the metal sacrificial layer and the high-k (high dielectric constant) material are introduced, the metal patterned electrode and the dielectric layer are prepared into an integrated structure, and then the integrated structure is transferred to the surface of the two-dimensional material by using a back-position transfer technology to form an integral structure of the device, so that the high mobility and low impedance gold-half contact of the two-dimensional semiconductor device are realized.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method for integrally preparing a two-dimensional semiconductor device circuit is characterized by comprising the following steps:
step 1, preparing a metal sacrificial layer on the surface of a substrate by adopting a thermal evaporation method;
step 2, preparing a functional circuit layer on the surface of the metal sacrificial layer prepared in the step 1 by adopting an ultraviolet photoetching-thermal evaporation method or an ALD method;
step 3, preparing an organic membrane supporting layer on the surface of the functional circuit layer by adopting a spin-coating method;
step 4, placing the device with the supporting layer prepared in the step 3 into a solution capable of reacting with the metal sacrificial layer until the functional circuit layer with the supporting layer is separated from the substrate;
step 5, transferring and cleaning the functional circuit layer, and then putting the functional circuit layer into deionized water again;
step 6, preparing a two-dimensional material on another substrate, transferring the functional circuit layer cleaned in the step 5 to the surface of the two-dimensional material, and baking;
and 7, placing the device obtained in the step 6 in an organic solvent to remove the organic membrane supporting layer, and then cleaning the device with deionized water to obtain the required two-dimensional semiconductor device.
Further, the material of the metal sacrificial layer in the step 1 is amphoteric metal, such as Al or Zn, and the thickness is 20-100 nm.
Further, the functional circuit layer in the step 2 is composed of a high dielectric constant dielectric layer and a patterned electrode; the high-dielectric-constant dielectric layer is prepared by an ALD method, and the patterned electrode is prepared by an ultraviolet photoetching-thermal evaporation method.
Furthermore, the patterned electrode comprises a source-drain gate electrode, the source-drain electrode is made of Cr/Au or Ti/Au, the thickness of the Cr or Ti layer is less than 5-10 nm, and the thickness of the Au layer is less than 100 nm.
Further, the high-k dielectric layer material is HfO2And the thickness is less than 30 nm.
Further, the organic film supporting layer in the step 3 is a two-layer structure, a layer of PMMA is spin-coated as a soft supporting layer, and then a layer of PPC hard supporting layer is spin-coated on the surface of the soft supporting layer.
Further, the solution capable of reacting with the metal sacrificial layer in step 4 is an acid or alkali solution, preferably 1mol/L HCl or HNO3Or NaOH solution.
Further, the substrate in step 6 is a silicon substrate, which is convenient for silicon-based integration; the two-dimensional material is two-dimensional material and heterojunction thereof, and the two-dimensional material can be graphene or WS2、WSe2PbS, GaN thin film, etc.; the heterojunction is formed by two-dimensional materials of n type and p type, and can be WS2/WSe2And the like.
Further, the method for preparing the two-dimensional material in the step 6 is a mechanical stripping method or a chemical vapor deposition method; the baking is carried out in two stages, and the baking is carried out for 1-2 hours at the temperature of 30-40 ℃ so as to remove interface water vapor; and then heating to 80-150 ℃, and baking for 10-60 min to increase the van der Waals force of the contact between the integrated circuit and the two-dimensional material.
Further, the organic solvent in step 7 is acetone, chloroform or the like.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
in the conventional two-dimensional semiconductor device manufacturing process, there are two damages to the material: when a source electrode and a drain electrode are evaporated, chemical doping and Fermi level pinning are introduced due to the fact that metal particles impact and a gold/half interface is miscible; when introducing a high-k dielectric layer, the thermal process further introduces defects in the channel due to the ALD process, resulting in carrier scattering. According to the method, the metal sacrificial layer is innovatively introduced, the functional circuit integrated structure is prepared on the metal sacrificial layer, and then the structure is stripped and transferred to the surface of the two-dimensional material, so that the interface scattering, the chemical doping and the Fermi pinning effects in the two-dimensional semiconductor device are effectively reduced, the synchronous optimization of the mobility, the on-off ratio and the subthreshold swing of the two-dimensional material is realized, and the method is simple and clean to prepare, small in destructiveness and high in stability.
Drawings
Fig. 1 is a schematic flow chart of the transfer integration structure according to embodiment 1 of the present invention.
Fig. 2 is a schematic flow chart of the transfer integration structure in embodiment 2 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings.
Example 1
WS (WS)2The method for integrally preparing the two-dimensional semiconductor device circuit comprises the following steps of:
step 1. in Si/SiO2Preparing a 60nm metal sacrificial layer Al film on the surface of the substrate by using a thermal evaporation method, wherein the evaporation rate is 0.2 angstrom/second;
step 2, spin-coating photoresist on the surface of the Al film of the metal sacrificial layer prepared in the step 1 by adopting an ultraviolet lithography method, and performing photoetching, development, evaporation and photoresist removal by combining a mask to obtain a patterned source-drain Cr/Au electrode (6/60 nm);
the specific process of the ultraviolet photoetching method comprises the following steps:
step 2.1, spin coating: the AZ6112 positive glue is firstly rotated for 10s at 1000r/s, then rotated for 30s at 3000r/s and baked for 60s at 100 ℃;
step 2.2. Exposure: exposure time 2s, development 12 s;
step 2.3, glue solidification: heating at 120 deg.C for 6min, depositing 6nm thick Cr layer at 0.1 angstrom/s evaporation rate, and depositing 60nm Au layer at 0.2 angstrom/s evaporation rate;
step 3, preparing a layer of HfO with the thickness of 15nm on the surface of the device with the source and drain electrodes prepared in the step 2 by adopting an ALD method2The film is used as a high-k dielectric layer, and the specific process parameters of ALD are as follows: the working temperature is 200 ℃, the air pressure of the chamber is 0.1 mTorr, the pump time of the water source is 0.15s, the air inflation time is 80s, the pump time of the hafnium source is 0.8s, the air inflation time is 80s, and the pulse cycle is 150 cycles; combining the mask again, and obtaining a patterned grid Cr/Au electrode (6/60nm) between the source electrode and the drain electrode by adopting an ultraviolet lithography method;
step 4, spin-coating a layer of PMMA as a soft supporting layer on the surface of the electrode at 2000r/min, and baking for 2min at 180 ℃ for curing; then spin-coating a layer of PPC as a hard supporting layer at the rotating speed of 1500r/min, and baking for 5s at 100 ℃ for curing;
step 5, placing the device with the prepared supporting layer in the step 4 in 1mol/L HCl solution, and placing for about 1h at 40 ℃ until the supporting layer with the integrated electrode floats on the liquid level;
step 6, transferring the integrated electrode to the surface of the glass slide, then washing the integrated electrode with deionized water, and putting the integrated electrode in the deionized water again after washing;
step 7. in SiO2Preparation of WS on a/Si substrate2Two-dimensional material, and then transferring the cleaned integrated electrode of step 6 to WS2Baking the surface of the two-dimensional material for 1h at 40 ℃ to remove interface water vapor; then heating to 120 ℃, and baking for 30min to enhance the van der Waals force of the contact between the integrated electrode and the two-dimensional material;
and 8, placing the device obtained in the step 7 in an acetone solution for removing the supporting layer material, and then cleaning with deionized water to obtain the two-dimensional semiconductor device.
Example 2
WS (WS)2/WSe2The method for integrally preparing the two-dimensional semiconductor integrated heterojunction inverter circuit comprises the following steps of:
step 1. in Si/SiO2Preparing a 60nm metal sacrificial layer Al film on the surface of the substrate by using a thermal evaporation method, wherein the evaporation rate is 0.2 angstrom/second;
step 2, spin-coating photoresist on the surface of the Al film of the metal sacrificial layer prepared in the step 1 by adopting an ultraviolet photoetching method, and combining mask plate photoetching, developing, ALD and photoresist removal to obtain patterned HfO with the thickness of 15nm2；
The specific process of the ultraviolet photoetching method comprises the following steps:
step 2.1, spin coating: the AZ6112 positive glue is firstly rotated for 10s at 1000r/s, then rotated for 30s at 3000r/s and baked for 60s at 100 ℃;
step 2.2. Exposure: exposure time 2s, development 12 s;
step 2.3, glue solidification: heating at 120 deg.C for 6min, depositing 6nm thick Cr layer at 0.1 angstrom/s evaporation rate, and depositing 60nm Au layer at 0.2 angstrom/s evaporation rate;
the specific process parameters of ALD are: the working temperature is 200 ℃, the air pressure of the chamber is 0.1 mTorr, the pump time of the water source is 0.15s, the air inflation time is 80s, the pump time of the hafnium source is 0.8s, the air inflation time is 80s, and the pulse cycle is 150 cycles;
step 3. HfO prepared in step 22Photoetching, developing, evaporating and removing the surface of the device by combining with a maskGluing to obtain a graphical p-region Pt electrode (60 nm); photoetching, developing, evaporating and removing photoresist by combining the mask again to obtain a graphical n area and an on-chip interconnection Ti electrode (60 nm);
step 4, spin-coating a layer of PMMA as a soft supporting layer on the surface of the electrode at 2000r/min, and baking for 2min at 180 ℃ for curing; then spin-coating a layer of PPC as a hard supporting layer at the rotating speed of 1500r/min, and baking for 5s at 100 ℃ for curing;
step 5, placing the device with the prepared supporting layer in the step 4 in 1mol/L HNO3 solution, and placing for about 1h at 40 ℃ until the supporting layer with the integrated functional circuit floats on the liquid level;
step 6, transferring the integrated functional circuit to the surface of the glass slide, then cleaning the integrated functional circuit by using deionized water, and putting the integrated functional circuit into the deionized water again after cleaning;
step 7. in SiO2Preparation of WS on a/Si substrate2/WSe2And (3) two-dimensional heterojunction, then transferring the cleaned integrated functional circuit obtained in the step (6) to the surface of a two-dimensional material, baking for 1h at 40 ℃, and removing interface water vapor; then heating to 120 ℃, and baking for 30min to enhance the van der Waals force of the contact between the integrated functional circuit and the two-dimensional material;
and 8, placing the device obtained in the step 7 in an acetone solution for removing the supporting layer material, and then cleaning with deionized water to obtain the two-dimensional integrated heterojunction inverter.
The preparation method of the integrated functional circuit structure has universality on two-dimensional materials, and the semiconductor device based on the two-dimensional materials can be used for preparing the electrode by the method, so that the reduction of the device performance caused by preparing the electrode by the conventional method is reduced.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.
Claims (10)
1. A method for integrally preparing a two-dimensional semiconductor device circuit is characterized by comprising the following steps:
step 1, preparing a metal sacrificial layer on the surface of a substrate by adopting a thermal evaporation method;
step 2, preparing a functional circuit layer on the surface of the metal sacrificial layer prepared in the step 1 by adopting an ultraviolet photoetching-thermal evaporation method or an ALD method;
step 3, preparing an organic membrane supporting layer on the surface of the functional circuit layer by adopting a spin-coating method;
step 4, placing the device with the supporting layer prepared in the step 3 into a solution capable of reacting with the metal sacrificial layer until the functional circuit layer with the supporting layer is separated from the substrate;
step 5, transferring and cleaning the functional circuit layer, and then putting the functional circuit layer into deionized water again;
step 6, preparing a two-dimensional material on another substrate, transferring the functional circuit layer cleaned in the step 5 to the surface of the two-dimensional material, and baking;
and 7, placing the device obtained in the step 6 in an organic solvent to remove the organic membrane supporting layer, and then cleaning the device with deionized water to obtain the required two-dimensional semiconductor device.
2. The method for integrally manufacturing a two-dimensional semiconductor device circuit according to claim 1, wherein the metal sacrificial layer in step 1 is made of amphoteric metal and has a thickness of 20-100 nm.
3. The method for circuit integration preparation of a two-dimensional semiconductor device according to claim 2, wherein the amphoteric metal is Al or Zn.
4. The method for circuit integration preparation of a two-dimensional semiconductor device according to claim 1, wherein the functional circuit layer in step 2 is composed of a high dielectric constant dielectric layer and a patterned electrode; the high-dielectric-constant dielectric layer is prepared by an ALD method, and the patterned electrode is prepared by an ultraviolet photoetching-thermal evaporation method.
5. The method of claim 4, wherein the high-k dielectric layer is HfO2And the thickness is less than 30 nm.
6. The method for integrally preparing a two-dimensional semiconductor device circuit according to claim 1, wherein the organic film support layer in step 3 is a two-layer structure, a layer of PMMA is spin-coated as a soft support layer, and then a layer of PPC hard support layer is spin-coated on the surface of the soft support layer.
7. The method for circuit-integrated production of a two-dimensional semiconductor device according to claim 1, wherein the solution capable of reacting with the sacrificial metal layer in step 4 is an acid solution or an alkali solution.
8. The method for circuit integration preparation of a two-dimensional semiconductor device according to claim 1, wherein the substrate of step 6 is a silicon substrate; the two-dimensional material is a two-dimensional material and a heterojunction thereof; the method for preparing the two-dimensional material is a mechanical stripping method or a chemical vapor deposition method; the baking is carried out in two stages, the baking is carried out for 1-2 hours at 30-40 ℃, then the temperature is increased to 80-150 ℃, and the baking is carried out for 10-60 min.
9. The method of claim 8, wherein the two-dimensional material is graphene, WS2、WSe2PbS, GaN; the two-dimensional heterojunction is WS2/WSe2。
10. The method for circuit integration fabrication of a two-dimensional semiconductor device according to claim 1, wherein the organic solvent in step 7 is acetone or chloroform.
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| CN101517700A (en) * | 2006-09-20 | 2009-08-26 | 伊利诺伊大学评议会 | Release strategies for making transferable semiconductor structures, devices and device components |
| CN103000669A (en) * | 2011-09-09 | 2013-03-27 | 中国科学院微电子研究所 | Source-drain buried graphene transistor device on diamond-like carbon substrate and manufacture method |
| CN103956320A (en) * | 2014-04-16 | 2014-07-30 | 苏州大学 | Method for transferring electrode patterns onto any substrates and constructing electronic devices |
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- 2020-05-07 CN CN202010377198.0A patent/CN111540709A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20060068563A1 (en) * | 2004-09-28 | 2006-03-30 | Palo Alto Research Center Incorporated | Method of manufacturing and structure of polycrystalline semiconductor thin-film heterostructures on dissimilar substrates |
| CN101517700A (en) * | 2006-09-20 | 2009-08-26 | 伊利诺伊大学评议会 | Release strategies for making transferable semiconductor structures, devices and device components |
| JP2009124177A (en) * | 2009-02-24 | 2009-06-04 | Canon Anelva Corp | Method for vapor-depositing metal gate on high-k dielectric film, method for improving interface between high-k dielectric film and metal gate, and substrate treatment system |
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