CN103915348B - A kind of method preparing graphene nano line device - Google Patents
A kind of method preparing graphene nano line device Download PDFInfo
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- CN103915348B CN103915348B CN201410157130.6A CN201410157130A CN103915348B CN 103915348 B CN103915348 B CN 103915348B CN 201410157130 A CN201410157130 A CN 201410157130A CN 103915348 B CN103915348 B CN 103915348B
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- graphene
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 88
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000010949 copper Substances 0.000 claims abstract description 10
- 229910052802 copper Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000002070 nanowire Substances 0.000 claims abstract description 5
- 230000006911 nucleation Effects 0.000 claims abstract description 5
- 238000010899 nucleation Methods 0.000 claims abstract description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 239000007792 gaseous phase Substances 0.000 claims description 4
- 239000003153 chemical reaction reagent Substances 0.000 claims description 3
- 239000008187 granular material Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 9
- 239000010410 layer Substances 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 125000000524 functional group Chemical group 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000003599 detergent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- -1 graphite alkene Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004557 single molecule detection Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
Abstract
The invention belongs to carbon back ic manufacturing technology field, a kind of method preparing graphene nano line device.The present invention etches an elongated nanometer groove in one piece of silicon dioxide substrates, deposits many discontinuous copper fritters by mask plate in groove, and these copper are as Graphene nucleation site；Low-pressure chemical vapor deposition is utilized to grow a layer graphene nano wire in groove；Utilize ald to grow high K dielectric in groove, cover on graphene nano line, form the high-K gate dielectric of device；Then the electrode of the source electrode of making devices, drain and gate, forms graphene nano line device.The method is simple and convenient reliably, can prepare overlong nanowire, and graphene nano line energy gap is big, and available ald forms high-K gate dielectric on Graphene.The method can be as a kind of basic skills preparing graphene nano line device.
Description
Technical field
The invention belongs to carbon back ic manufacturing technology field, be specifically related to a kind of method preparing graphene nano line device.
Background technology
In field of semiconductor manufacture, along with device size is increasingly nearer apart from its physics limit, mole epoch after entering.And the discovery of Graphene (Graphene) brings hope.The cellular two dimensional crystal that Graphene (Graphene) is made up of monolayer hexagonal cellular carbon atom, is a layer in graphite, and Fig. 1 show the basic structure schematic diagram of Graphene.Graphene has the carrier mobility high more than silicon, Graphene has under room temperature electron mobility 200 000 cm2 V s at a high speed, quantum hall effect, high theoretical specific surface area 2600 m2/g, also has a high heat conductance 3000 W/m K and outstanding mechanical property (high-modulus 1060GPa, high intensity 130GPa), it is considered to have wide practical use at aspects such as the quantum devices such as single-molecule detection device, integrated circuit, field-effect transistor, functional composite material, energy storage material, catalyst carriers.The two-dimensional structure unique based on Graphene and physical characteristic, Graphene is considered as the important materials being expected to continue Moore's Law in integrated circuit of future generation.
But preferably the energy gap of Graphene is 0, it has metallic character, the state being on all the time, cannot turn off without any process Graphene, thus cannot make switching device.Want to open the forbidden band of Graphene, electric field can be applied for the Graphene of zero energy gap, be doped or be prepared as graphene nano line etc. and process.Wherein being prepared as graphene nano line and can open Graphene forbidden band very well, nano wire is the longest, and the energy gap of Graphene can be the biggest, can effectively reduce the leakage current of graphene device, prepares good graphene device.
The present invention etches an elongated nanometer groove in one piece of silicon dioxide substrates, directly grows graphene nano line in groove, so need not other process, it is not necessary to through steps such as over etchings, it is possible to directly obtains graphene nano line.Separately there is no dangling bonds, chemical property torpescence due to graphenic surface so that on Graphene, directly deposited high K dielectric by Atomic layer deposition method extremely difficult.So the nanometer well width that the present invention utilizes etching is little, cell wall has silicon dioxide dangling bonds, ald long high K dielectric in next life can be utilized, Landfill covering whole nanometer groove, so high K dielectric medium just covers on Graphene, form graphene device high-K gate dielectric, Graphene offer functional group or dangling bonds itself be so provided, next life long high-K gate dielectric.This method can protect the performance of Graphene well, and the impact causing Graphene is little, does not damage the lattice structure of Graphene.This is a kind of effective and novel method, will promote the development of carbon back integrated circuit further.
Summary of the invention
It is an object of the invention to propose that a kind of preparation technology is simple, the preparation method of the graphene nano line device of excellent device performance.
Promoting the development of graphene device, this device just has the biggest Graphene energy gap, and leakage current is little, is formed during high-K gate dielectric little to Graphene infringement, provides the performance of graphene nano line device very well.
The method preparing graphene nano line device that the present invention proposes, concrete steps include:
(1) utilize mask plate, use chemical gaseous phase depositing process to deposit one layer of silicon nitride in silicon dioxide substrates as etch-protecting layer, in silicon dioxide substrates, then etch an elongated nanometer groove；
(2) in nanometer groove, some discontinuous copper fritters are deposited, as Graphene nucleation site；
(3) low-pressure chemical vapor deposition is utilized to grow a layer graphene nano wire in the nanometer groove of above-mentioned process；
(4) utilize ald growing high K dielectric in the nanometer groove of above-mentioned process, cover on graphene nano line, form the high-K gate dielectric of device；
(5) electrode of the then source electrode of making devices, drain and gate, forms graphene nano line device.
Further, described offer silicon dioxide substrates, first through polishing, and to be carried out, remove the impurity on surface, granule, remaining reagent, make substrate surface clean, flat smooth, do not stain.After having processed, it is possible to etch nanometer groove on sample.During etching nanometer groove, need to utilize mask plate and chemical gaseous phase to be deposited on sample one layer of silicon nitride of deposit as etch-protecting layer, then etch an elongated nanometer groove; then get rid of silicon nitride, after having had nanometer groove, copper fritter can be deposited in groove; discontinuously, thus it is not turned on；Then utilize copper as Graphene nucleation site, owing to copper fritter is the most intensive, one layer of continuous print graphene nano line can be grown.As long as finally utilizing ald to fill high K dielectric (such as aluminium oxide) in nanometer groove, high K dielectric just directly overlies on Graphene as gate medium, the most do not damage the electric property of Graphene, reduce the defect on Graphene, thus maintain the performances such as the high mobility of ideal graphite alkene as far as possible.Owing to nanometer groove can be made the longest, Graphene energy gap so can be made big as far as possible, improve the turn-off performance of graphene device, leakage current is little.
The present invention can go out graphene nano line with direct growth, avoid the processing steps such as etching, Simplified flowsheet, and reduce the damage to Graphene performance, the shape of the graphene nano line of direct growth can control, by the design of mask plate, variously-shaped nanometer groove can be etched, thus grow variously-shaped graphene nano line.When growing high-K gate dielectric, it is not necessary to Graphene Shang You functional group or dangling bonds, thus cause on Graphene defective.The high K dielectric of growth is entirely physics and covers up, and the mode not over chemical bond brings change to the structure of Graphene, and the impact so caused the electric property of Graphene is minimum, thus prepares the graphene nano line device of function admirable.This method is simple and convenient, reduces processing step, and the impact causing Graphene is little, does not destroy the lattice structure of Graphene.The method can be as preparing graphene nano line device one basic skills.
Accompanying drawing explanation
Fig. 1 is the basic structural representation of Graphene.
Fig. 2 to Fig. 5 prepares graphene nano line device process schematic diagram for what the present invention provided.
Fig. 6 is operational flowchart of the present invention.
Detailed description of the invention
The present invention utilizes and etches nanometer groove on substrate, thus direct growth goes out required overlength graphene nano line in groove.Dangling bonds followed by the silicon dioxide of nanometer groove sidewall, use the method growth high K dielectric of ald, fill nanometer groove with high K dielectric, so that high K dielectric physics covers on Graphene, form the high-K gate dielectric of Graphene, so reduce the damage to Graphene.The following stated is to use the proposed by the invention embodiment preparing graphene nano line device.
In the drawings, for convenience of explanation, structure size and ratio do not represent actual size.
First, it is provided that silicon dioxide (SiO2 ) film sample 101, sample is cleaned, removes some magazines at sample surfaces, granule, remaining reagent etc., make Graphene silica sample very neat and tidy.As shown in Figure 2.
Then perform etching, first with utilize mask plate and chemical gaseous phase be deposited on sample deposit one layer of silicon nitride as etch-protecting layer, then etch the nanometer groove of an overlength, a height of 5000 × 100 × 100nm of length and width of groove3, then get rid of silicon nitride, form nanometer groove 102, as shown in Figure 3.
It follows that utilize the method for physical vapour deposition (PVD) or ald to deposit many copper fritters in nanometer groove, as Graphene nucleation site, copper fritter is discontinuous, is distributed in nanometer trench bottom, so has abundant copper sheet 103, and its top view is as shown in Figure 4.
It follows that put into by sample in the reacting furnace of low-pressure chemical vapor deposition, open reacting furnace.It is passed through argon, disposes the air in reacting furnace, then pass to hydrogen 5sccm and 500sccm argon, heating reaction furnace, treat that temperature rises to 1000 degree, close argon, open methane 10sccm, hydrogen 10sccm and react 5 minutes.Quickly cooling, finally treats that sample is cooled to room temperature, takes out sample.Grow graphene nano 104, as shown in Figure 5.
It follows that fill nanometer groove by the means of ald, graphene nano line covers high K dielectric aluminium oxide.Concretely comprising the following steps, arranging reaction temperature is 110 DEG C and reacting by heating chamber, and sample is put into ALD reaction chamber, when temperature reaches design temperature, selects trimethyl aluminium and water as reaction source, sets number reaction time, proceed by ald.After reaction terminates, close source, detergent line, take out sample, form high K dielectric aluminium oxide.The last electrode that just can prepare source electrode, drain and gate, forms device.
As it has been described above, without departing from the spirit and scope of the invention, it is also possible to constituting many has the embodiment of very big difference.The invention is not restricted to specific embodiment described in the description.
Claims (2)
1. the method preparing graphene nano line device, it is characterised in that concretely comprise the following steps:
(1) utilize mask plate, use chemical gaseous phase depositing process to deposit one layer of silicon nitride in silicon dioxide substrates as etch-protecting layer, in silicon dioxide substrates, then etch an elongated nanometer groove；
(2) in nanometer groove, some discontinuous copper fritters are deposited, as Graphene nucleation site；
(3) low-pressure chemical vapor deposition is utilized to grow a layer graphene nano wire in the nanometer groove that step (2) processes；
(4) utilize ald growing high K dielectric in the nanometer groove that step (3) processes, cover on graphene nano line, form the high-K gate dielectric of device；
(5) electrode of the then source electrode of making devices, drain and gate, forms graphene nano line device.
The most according to claim 1, method, it is characterised in that described silicon dioxide liner basal surface first through polishing, and to be carried out, remove the impurity on surface, granule and remaining reagent, makes substrate surface clean, and flat smooth is not stained.
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| CN106531613B (en) * | 2016-04-22 | 2020-07-17 | 中国科学院微电子研究所 | Selective modification processing method and device for graphene surface |
| CN106526716B (en) * | 2016-11-22 | 2018-06-22 | 武汉华星光电技术有限公司 | A kind of production method and display device of micro-nano structure antireflective film |
| CN111129113B (en) * | 2019-12-24 | 2021-06-25 | 中国科学院上海微系统与信息技术研究所 | Graphene nanoribbon device array and preparation method thereof |
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| CN102683217A (en) * | 2012-05-24 | 2012-09-19 | 中国科学院上海微系统与信息技术研究所 | Preparation method of graphite-based double-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
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| US8557643B2 (en) * | 2011-10-03 | 2013-10-15 | International Business Machines Corporation | Transistor device with reduced gate resistance |
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| CN102683217A (en) * | 2012-05-24 | 2012-09-19 | 中国科学院上海微系统与信息技术研究所 | Preparation method of graphite-based double-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
Non-Patent Citations (1)
| Title |
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| "石墨烯的制备研究进展";袁小亚;《无机材料学报》;20110630;第26卷(第6期);第561页-第567页 * |
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