CN111524971A - 4H-SiC groove insulated gate bipolar transistor - Google Patents
4H-SiC groove insulated gate bipolar transistor Download PDFInfo
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- 230000004888 barrier function Effects 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims abstract description 8
- 238000003860 storage Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 6
- 230000005684 electric field Effects 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 239000000969 carrier Substances 0.000 abstract description 3
- 108091006146 Channels Proteins 0.000 abstract 1
- 238000000605 extraction Methods 0.000 abstract 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 25
- 230000015556 catabolic process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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Abstract
The invention discloses a 4H-SiC groove insulated gate bipolar transistor, which comprises a P + ohmic contact region, an N + emission region, a P type channel region, a carrier storage layer, an N-voltage barrier layer, an N + buffer layer, a P + collector region, a P type polysilicon region and a groove type grid electrode, wherein the P + ohmic contact region is arranged on the P + emission region; compared with the traditional structure, the invention mainly provides that a groove type p-poly/p-SiC heterojunction is introduced at one side of the collector of the device. The heterojunction is made into a groove shape, so that the hole injection efficiency can be improved when the device is normally conducted, and the on-state voltage drop of the device is reduced; meanwhile, due to the introduction of the heterojunction, the new structure provides a low-resistance channel for the leakage of current carriers in the voltage barrier layer in the turn-off process, so that the extraction of electrons can be accelerated, and the turn-off loss is further reduced.
Description
Technical Field
The invention relates to an insulated gate bipolar transistor device, in particular to a high-voltage 4H-SiC groove insulated gate bipolar transistor with breakdown voltage larger than 15 kV.
Background
Silicon (Si) -based power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT) devices are the most widely used power electronic devices today. A MOSFET is often suitable for high switching frequency applications, but since it is a device that conducts on the unipolar principle, its on-resistance is relatively large, and thus is generally limited in practical applications to the environment of the breakdown voltage of kilovolts. The IGBT device has the working principle of MOS grid voltage control and BJT bipolar conduction at the same time, so that the IGBT device has attraction in a large voltage range from breakdown voltage 600V to thousands of volts. As a representative material of the third generation wide bandgap semiconductor, SiC is most promising for manufacturing electronic devices instead of Si material due to its excellent material characteristics, such as: which is about 10 times higher than the Si material in terms of breakdown electric field, higher thermal conductivity, and lower intrinsic carrier concentration, etc. These outstanding properties enable silicon carbide devices to operate at high temperatures, high voltages, and high switching frequencies, further meeting the demanding requirements of modern power and electronic systems.
Meanwhile, although the on-state voltage drop of the device can be reduced due to the existence of the conductance modulation effect, a large number of minority carriers are stored in the voltage blocking layer in the on state, and the minority carriers need to be discharged for a certain time in the turn-off process of the device, so that a large trailing current with long duration can be caused, and large turn-off loss is finally formed. How to improve the trade-off relationship between the turn-on voltage drop and turn-off loss of the SiC IGBTs device has been one of the research directions in the industry.
Disclosure of Invention
Aiming at the defects in the existing SiC IGBTs technology, the invention provides a novel device structure, wherein a groove-type p-poly/p-SiC heterojunction is introduced at one side of a collector at the back of the structure, and an extra low-resistance path is provided for the discharge of electrons when the device is turned off, so that the discharge speed of the electrons is greatly accelerated, and the turn-off loss is reduced; meanwhile, the area of the collector region of the device is equivalently increased by the groove-type heterojunction collector electrode, and holes can be injected into the voltage barrier layer in the forward conduction process, so that a stronger conductivity modulation effect is generated in the voltage barrier layer, and the on-state voltage drop is reduced. The existence of the back groove type heterojunction collector electrode enables the turn-off loss of the device to be low, and the turn-on voltage drop and the turn-off loss of the device are improved.
The technical scheme for realizing the aim of the invention is as follows:
the invention provides a 4H-SiC groove insulated gate bipolar transistor, which comprises a lightly doped N-type voltage barrier layer, wherein an N-type current storage layer, a P-type channel region, a P + ohmic contact region and an N + emission region are sequentially formed on the N-type voltage barrier layer; the device comprises a trench gate structure consisting of a gate oxide dielectric layer and a polysilicon electrode, and a P + electric field shielding layer positioned below the trench, wherein the P + electric field shielding layer is connected with an emitter electrode through a metal electrode, and the emitter electrode is positioned above a P + ohmic contact region and an N + emitter region; the 4H-SiC groove insulated gate bipolar transistor also comprises an N-type buffer layer, a P + collector region and a polysilicon region which are sequentially arranged below the N-type voltage barrier layer; the collector electrode is positioned on the back surface of the device and is connected with the P + collector region and the polysilicon region in the groove heterojunction collector region; polysilicon regions in the heterojunction current collecting regions of the plurality of non-adjacent grooves extend into the N-type voltage barrier layer and form P-poly/P-SiC heterojunction with the P + current collecting region, the depth of the polysilicon regions is several microns to dozens of microns, and the width of the polysilicon regions is zero microns to several microns; the doping concentration is 1015～1017Between orders of magnitude; the doping concentration of the groove heterojunction region P + collector region is 1017～1019Between orders of magnitude, and between fractions of a micron and several microns thick.
Preferably, the doping concentration of the N-type voltage barrier layer is 1014In order of magnitude, the thickness is at least 100 μm or more.
Preferably, the doping concentration of the N-type buffer layer is 10 higher than that of the N-type voltage blocking layer16～1017On the order of magnitude, with a thickness of between a few microns and a few tens of microns.
Preferably, the doping concentration of the N-type current storage layer is 10 higher than that of the N-type voltage blocking layer15～1016Order of magnitude, thicknessThe degree is between a few tenths of a micron and a few microns.
Preferably, the doping concentration of the P-type channel region is 1017～1018On the order of magnitude, with a thickness of between a fraction of a micron and several microns.
According to the invention, the groove type p-poly/p-SiC heterojunction introduced at one side of the collector is utilized to provide an extra low-resistance path for the discharge of electrons in the voltage barrier layer in the turn-off process of the device, so that the size and duration of trailing current are reduced, and the turn-off loss is further reduced. By utilizing the advantage that the area of the collector region is equivalently increased by using the groove type heterojunction, a stronger conductance modulation effect can be caused in the voltage barrier layer when the device is in an on state, and finally the on state voltage drop is reduced. Thereby improving the on-state voltage drop and the off-state loss of the device.
Drawings
Fig. 1 is a schematic structural diagram of a conventional 4H-SiC trench insulated gate bipolar transistor.
Fig. 2 is a schematic structural diagram of a 4H-SiC trench insulated gate bipolar transistor provided by the invention.
Fig. 3 to 7 are schematic views of the manufacturing process of the 4H-SiC trench insulated gate bipolar transistor in the embodiment.
Fig. 8 is a graph comparing the turn-off curves of the conventional 4H-SiC trench insulated gate bipolar transistor and the 4H-SiC trench insulated gate bipolar transistor in the example.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is specifically described below with reference to the accompanying drawings.
As shown in fig. 1, it is a schematic diagram of a conventional 4H-SiC trench insulated gate bipolar transistor structure;
as shown in figure 2, the 4H-SiC groove insulated gate bipolar transistor comprises a lightly doped N-type voltage barrier layer 9, an N-type current storage layer 5, a P-type channel region 4, a P + ohmic contact region 2, an N + emission region 3, a groove gate structure consisting of a gate oxide dielectric layer 7 and a polysilicon electrode 6, a P + electric field shielding layer 8 positioned below a groove, and a P + electric field shielding layer 9The shielding layer 8 is connected with the emitter electrode 1 through a metal electrode, and the emitter electrode 1 is positioned on the P + ohmic contact region 2 and the N + emitter region 3; the 4H-SiC groove insulated gate bipolar transistor also comprises an N-type buffer layer 10, a P + collector region 11 and a polysilicon region 14 which are sequentially arranged below the N-type voltage barrier layer 9; the collector electrode 12 is positioned on the back surface of the device and is connected with the P + collector region 11 and the polysilicon region 14 in the groove heterojunction collector region; polysilicon regions 14 in the plurality of non-adjacent groove heterojunction collector regions deeply penetrate into the N-type voltage barrier layer 9 and form P-poly/P-SiC heterojunction with the P + collector region 11, wherein the depth of the polysilicon regions 14 is several micrometers to dozens of micrometers, and the width of the polysilicon regions is zero micrometers to several micrometers; the doping concentration is 1015～1017Between orders of magnitude; the doping concentration of the groove heterojunction region P + collector region 11 is 1017～1019Between orders of magnitude, and between fractions of a micron and several microns thick.
The N-type voltage barrier layer 9 has a doping concentration of 10 to withstand a voltage of 15kV or more14In order of magnitude, the thickness is at least 100 μm or more.
The doping concentration of the N-type buffer layer 10 is 10 higher than that of the N-type voltage barrier layer 916～1017On the order of magnitude, with a thickness of between a few microns and a few tens of microns.
The doping concentration of the N-type carrier storage layer 5 is higher than that of the N-type voltage barrier layer 9 and is 1015～1016On the order of magnitude, with a thickness of between a fraction of a micron and several microns.
The doping concentration of the P-type channel region 4 is about 1017～1018On the order of magnitude, with a thickness of between a fraction of a micron and several microns.
The invention also provides a manufacturing method of the novel 4H-SiC groove insulated gate bipolar transistor, which comprises the following steps:
step 1: a P + collector region 11, an N-type buffer layer 10, an N-type voltage blocking layer 9, an N-type current storage layer 5, and a P-type channel region 4 are epitaxially formed in this order on an N-type substrate layer 13, as shown in fig. 3.
Step 2: the trench gate region is etched to expose the P + ohmic contact region 2, the N + emitter region 3, and the P + electric field shielding layer 8 by ion implantation, as shown in fig. 4.
And step 3: the substrate 13 is completely removed and thermal oxidation is performed to create the gate oxide dielectric layer 7, followed by filling with polysilicon to form the polysilicon electrode 6 as a gate electrode, as shown in fig. 5.
And 4, step 4: the wafer is flipped over and the trench heterojunction region is etched using dry etching, and an N-type buffer layer 10 is formed by high-energy ion implantation, as shown in fig. 6.
And 5: the P + collector region 11 is formed at the trench heterojunction sidewalls and bottom portion using high energy ion implantation techniques, as shown in fig. 7.
Step 6: the polysilicon 14 is filled to form a heterojunction, and then emitter metal and collector metal are deposited to form an emitter electrode 1 and a collector electrode 12, respectively, resulting in a new 4H-SiC trench insulated gate bipolar transistor as shown in fig. 2.
As shown in fig. 8, compared with the existing 4H-SiC trench insulated gate bipolar transistor, the turn-off curve of the 4H-SiC trench insulated gate bipolar transistor of the present invention shows that the turn-off loss of the present invention is much smaller than that of the existing 4H-SiC trench insulated gate bipolar transistor.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1.4H-SiC groove insulated gate bipolar transistor, its characterized in that: the N-type current source device comprises a lightly doped N-type voltage barrier layer (9), wherein an N-type current storage layer (5), a P-type channel region (4), a P + ohmic contact region (2) and an N + emission region (3) are sequentially formed on the N-type voltage barrier layer (9); a trench gate structure composed of a gate oxide dielectric layer (7) and a polysilicon electrode (6), and a P + electric field shielding layer (8) located below the trench, wherein the P + electric field shielding layer (8) is connected with the emitter electrode (1) through a metal electrodeThe emitter electrode (1) is positioned on the P + ohmic contact region (2) and the N + emitter region (3); the method is characterized in that: the N-type voltage blocking layer is characterized by further comprising an N-type buffer layer (10), a P + collector region (11) and a polysilicon region (14) which are sequentially arranged below the N-type voltage blocking layer (9); the collector electrode (12) is positioned on the back surface of the device and is connected with the P + collector region (11) and the polysilicon region (14) in the groove heterojunction collector region; polysilicon regions (14) in the plurality of non-adjacent groove heterojunction current collecting regions deeply penetrate into the N-type voltage barrier layer (9) and form P-poly/P-SiC heterojunction with the P + current collecting region (11), wherein the depth of the polysilicon regions (14) is several micrometers to dozens of micrometers, and the width of the polysilicon regions is between a few tenths of micrometers and several micrometers; the doping concentration is 1015～1017Between orders of magnitude; the doping concentration of the groove heterojunction region P + collector region (11) is 1017～1019Between orders of magnitude, and between fractions of a micron and several microns thick.
2. The 4H-SiC trench insulated gate bipolar transistor of claim 1, characterized in that: the doping concentration of the N-type voltage barrier layer (9) is 1014In order of magnitude, the thickness is at least 100 μm or more.
3. The 4H-SiC trench insulated gate bipolar transistor of claim 1, characterized in that: the doping concentration of the N-type buffer layer (10) is higher than that of the N-type voltage barrier layer (9) and is 1016～1017On the order of magnitude, with a thickness of between a few microns and a few tens of microns.
4. The 4H-SiC trench insulated gate bipolar transistor of claim 1, characterized in that: the doping concentration of the N-type current storage layer (5) is higher than that of the N-type voltage barrier layer (9) and is 1015～1016On the order of magnitude, with a thickness of between a fraction of a micron and several microns.
5. The 4H-SiC trench insulated gate bipolar transistor of claim 1, characterized in that: the doping concentration of the P-type channel region (4) is 1017～1018On the order of magnitude, with a thickness of between a fraction of a micron and several microns.
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| CN202010023568.0A CN111524971A (en) | 2020-01-09 | 2020-01-09 | 4H-SiC groove insulated gate bipolar transistor |
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| CN202010023568.0A CN111524971A (en) | 2020-01-09 | 2020-01-09 | 4H-SiC groove insulated gate bipolar transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687746A (en) * | 2020-12-29 | 2021-04-20 | 电子科技大学 | Silicon carbide planar MOSFET device and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0615292A1 (en) * | 1993-03-10 | 1994-09-14 | Hitachi, Ltd. | Insulated gate bipolar transistor |
| US20140225126A1 (en) * | 2011-08-02 | 2014-08-14 | Rohm Co., Ltd. | Semiconductor device, and manufacturing method for same |
| CN107799588A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
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2020
- 2020-01-09 CN CN202010023568.0A patent/CN111524971A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0615292A1 (en) * | 1993-03-10 | 1994-09-14 | Hitachi, Ltd. | Insulated gate bipolar transistor |
| US20140225126A1 (en) * | 2011-08-02 | 2014-08-14 | Rohm Co., Ltd. | Semiconductor device, and manufacturing method for same |
| CN107799588A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
Non-Patent Citations (1)
| Title |
|---|
| HONG-KAI MAO ET.AL: "Simulation Study of 4H-SiC Trench Insulated Gate Bipolar Transistor with Low Turn-Off Loss", 《MICROMACHINES》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687746A (en) * | 2020-12-29 | 2021-04-20 | 电子科技大学 | Silicon carbide planar MOSFET device and preparation method thereof |
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Application publication date: 20200811 |