CN117219665A - Gate commutated thyristor chip and thyristor - Google Patents
Gate commutated thyristor chip and thyristor Download PDFInfo
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Abstract
The application belongs to the technical field of semiconductor devices, and particularly relates to a gate commutated thyristor chip and a thyristor, a cathode metal layer, gate metal layers positioned at two sides of the cathode metal layer, an anode metal layer opposite to the cathode metal layer, and a semiconductor substrate formed between the cathode metal layer and the anode metal layer; the semiconductor substrate comprises five-layer region structure or six-layer region structure, each structure region has different conductivity types, the P base region is designed to form a 'concave' main junction in a partitioning manner, the junction depth and the concentration of the P base region below the cathode comb strip are improved, and the current gain alpha of an npn transistor corresponding to the equivalent part is reduced 21 The on-state loss and the off-state loss can be reduced simultaneously. The application is especially suitable for reverse resistanceGCT can reduce the thickness of the sheet and realize better design of blocking, on-state and off-state compromise.
Description
Technical Field
The application belongs to the technical field of semiconductor devices, and particularly relates to a gate commutated thyristor chip and a thyristor.
Background
IGCT (integrated gate commutated thyristor) is used as a fully-controlled power semiconductor device, and has wide application prospect in the field of power grids due to the characteristics of large power capacity, low on-state loss, firm short-circuit failure mode and the like. IGCT devices are used as core devices of power devices, and gate commutated thyristors are also called GCTs, wherein the loss characteristics of GCT chips are closely related to the energy transmission efficiency of the power devices.
The main structure of the conventional trench type GCT chip in the longitudinal direction comprises four PNPN regions, as shown in figure 1. According to the degree of doping, the material can be further subdivided into P + 、N′、N - 、P、P + 、N + Six regions respectively corresponding to P + Anode emitter, N' buffer layer, N - Base region, P + Short base region and N + Emitter region (also referred to as cathode sliver). The inside of the chip is provided with 3 PN junctions, namely a J1 junction (anode transparent junction), a J2 junction (blocking voltage main junction) and a J3 junction (gate cathode junction) from the anode to the cathode, wherein the cathode and the gate form a step through the groove. And the cathode strips are uniformly distributed in a wafer by adopting sector circular arcs or circumferences when seen from the transverse direction of the GCT chip. For GCT tube cores with different diameters, cathode strips are generally distributed in a radial manner according to 2-16 split circles.
For the trench type GCT, as shown in FIG. 1, the trench structure can form a gap to perform gate-cathode isolation, and the trench depth can control the current gain alpha 2 of an npn equivalent transistor and the current gain alpha 1 of another pnp equivalent transistor contained in the GCT chip, so as to optimize the loss characteristic and turn-off capability of the GCT chip. Secondly, for the existing HPT (high power technology ) GCT structure, as shown in fig. 2, under the condition of a certain waveform height, the main junction depth must be increased to reduce the npn equivalent transistor current gain α2 under the cathode comb strip in order to improve the turn-off capability, which will result in an increase in the GCT single crystal specification slice thickness, resulting in an increase in the turn-off and on loss of the device, especially in the GCT reverse blocking type. On the other hand, the existing HPT technology only utilizes a transverse electric field to rapidly extract hole carriers in the area below the cathode sliver, but improves the cathode electron emission efficiency in the area, so that the effect on the GCT on improving the turn-off current capability is limited. In summary, the existing HPT GCT loss regulation always has a design contradiction that the turn-on loss and the turn-off loss are difficult to compromise, and the turn-off capability is limited to be improved. Therefore, a wave-shaped GCT chip structure scheme is provided, the turn-off capability is improved, and the turn-on loss and the turn-off loss are reduced at the same time.
Disclosure of Invention
The application aims to solve the technical problem of providing a gate commutated thyristor chip and a thyristor, which can improve the turn-off capability and reduce the turn-on loss and turn-off loss.
The application provides a gate commutated thyristor chip, comprising: the semiconductor device comprises a cathode metal layer, gate metal layers positioned on two sides of the cathode metal layer, an anode metal layer opposite to the cathode metal layer and a semiconductor substrate formed between the cathode metal layer and the anode metal layer;
the semiconductor substrate comprises a five-layer area structure or a six-layer area structure, and each structural area has different conductivity types;
the five-layer zone structure comprises: n in contact with the cathode metal layer + Emitter, gate metal layer and N + P of emitter contact + Short base region, and P + P base region in short base region contact, N in contact with P base region - Base region, and N - P of base contact + An anode emission region; the P is + The anode emission area is contacted with the anode metal layer;
the six-layer zone structure comprises: n in contact with the cathode metal layer + Emitter, gate metal layer and N + P of emitter contact + Short base region, and P + P base region in short base region contact, N in contact with P base region - Base region, and N - N 'buffer layer or P type anode emitter region contacted with base region, and P contacted with N' buffer layer or P type anode emitter region + An anode emission region; the P is + The anode emission area is contacted with the anode metal layer;
the P base region has a convex structure, and the N is - The base region has a concave structure, and the convex structure is embedded in the concave structure.
Optionally, the N + Partial embedding of emitter region into P + In the short base region, the embedding depth is 0-30 μm.
Optionally, the N + The doping concentration of the emitter region is 1E16cm -3 -1E22cm -3 The diffusion depth is 5 μm-40 μm.
Optionally, the P + The doping concentration of the short base region is 1E15cm -3 -5E18cm -3 The diffusion depth is about 20 μm to 80 μm.
Optionally, the doping concentration of the P base region is 1E13cm -3 -2E16cm -3 The diffusion depth is 60 μm-200 μm.
Optionally, the doping concentration of the P-type anode emission region is 1E13cm -3 -2E16cm -3 The diffusion depth is 60 μm-200 μm.
Optionally, the N' buffer layer has a doping concentration of 1E12cm -3 -1E17cm -3 The diffusion depth is typically 10 μm to 100 μm.
Optionally, the P + The doping concentration of the anode emission region is 1E15cm -3 -5E18cm -3 The diffusion depth is 0.5 μm-80 μm.
A thyristor comprises the gate commutated thyristor chip.
Optionally, the thyristor comprises the gate commutated thyristor chip and a fast recovery diode chip, and the gate commutated thyristor chip and the fast recovery diode chip are connected in anti-parallel through an NPN isolation structure to form the thyristor.
The gate pole converter thyristor chip has the beneficial effects that the P base region is designed to form the concave corrugated main junction in a partitioned manner, the junction depth and the concentration of the P base region below the cathode comb strip are increased, and the current gain alpha of an npn transistor corresponding to the equivalent part is reduced 21 On one hand, the efficiency of cathode electron emission in the turn-off process is improved, and meanwhile, the lateral electric field below prevents carriers in the body from gathering in the P base region below the cathode comb strip, so that the turn-off current is improved; the junction depth and concentration of the P base region below the gate electrode are reduced, and the current gain alpha of the npn transistor corresponding to the equivalent part is improved 22 The carrier regulation effect of the npn transistor under the gate metal layer (more than 60% of the chip area) in on state is enhanced to reduce on state voltage drop. Simulation design verifies that compared with the groove type GCT under the same current working condition, the on-state loss and the off-state loss can be reduced simultaneously; the method is particularly suitable for the reverse resistance GCT, can reduce the sheet thickness, and realizes better design of blocking and compromise between on-state and off-state.
Drawings
FIG. 1 is a schematic diagram of a trench GCT chip;
FIG. 2 is a schematic diagram of a conventional HPT GCT chip;
FIG. 3 is a schematic diagram of a reverse-blocking GCT chip according to an embodiment of the present application;
FIG. 4 is a schematic diagram II of a planar inverted resistive GCT chip according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a planar asymmetric GCT chip according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an asymmetric GCT chip according to an embodiment of the present application;
FIG. 7 is a schematic diagram II of an asymmetric GCT chip according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a reverse-conducting GCT chip according to an embodiment of the present application.
In the figure: 1.N + an emission region; 2. p (P) + A short base region; 3. a P base region; 4. n (N) - A base region; 5. a P-type anode emission region; 6. p (P) + An anode emission region; 7. an N' buffer layer; 8. a cathode metal layer; 9. an anode metal layer; 10. a gate metal layer; 11. a J1 junction; 12. a J2 junction; 13. a J3 junction; 14. FRD-P + An anode emission region; 15. a P anode region; 16. n (N) + A cathode emission region; 17. n (N) - And isolating the base region.
Detailed Description
As shown in fig. 3-8, an embodiment of the present application provides a gate commutated thyristor chip, including: a cathode metal layer 8, a gate metal layer 10 located at both sides of the cathode metal layer 8, an anode metal layer 9 opposite to the cathode metal layer 8, and a semiconductor substrate formed between the cathode metal layer 8 and the anode metal layer 9; the semiconductor substrate comprises a five-layer area structure or a six-layer area structure, and each layer of structure area has different conductivity types;
the five-layer zone structure comprises: n in contact with the cathode metal layer 8 + Emitter 1, gate metal layer 10 and N + P contacted by emitter region 1 + Short base region 2, and P + P base region 3 in contact with short base region 2, N in contact with P base region 3 - Base region 4, and N - P contacted by base region 4 + An anode emission region 6; p (P) + The anode emission area 6 is in contact with the anode metal layer 9;
the six-layer zone structure comprises: n in contact with the cathode metal layer 8 + Emitter 1, gate metal layer 10 and N + P contacted by emitter region 1 + Short base region 2, and P + P base region 3 in contact with short base region 2, N in contact with P base region 3 - Base region 4, and N - An N 'buffer layer 7 or a P-type anode emitter region 5 in contact with the base region 4, and P in contact with the N' buffer layer 7 or the P-type anode emitter region 5 + An anode emission region 6; p (P) + The anode emission area 6 is in contact with the anode metal layer 9;
the P base region 3 has a convex structure, N - The base region 4 has a concave structure, the convex structure is embedded in the concave structure, and the cross section of the formed J2 junction 12 is concave.
Compared with the prior art, the application providesThe gate commutated thyristor chip designs the P base region 3 into a concave corrugated main junction in a partitioning way, increases the junction depth and concentration of the P base region 3 below the cathode comb strip, and reduces the current gain alpha of an npn transistor corresponding to the equivalent part 21 On one hand, the efficiency of cathode electron emission in the turn-off process is improved, and meanwhile, the lateral electric field below prevents carriers in the body from gathering in the P base region 3 below the cathode comb strip, so that the turn-off current is improved; the junction depth and concentration of the P base region 3 below the gate electrode are reduced, and the current gain alpha of the npn transistor corresponding to the equivalent part is improved 22 The carrier regulating effect of npn transistors under gate metal layer 10 (more than 60% of the chip area) in on-state is enhanced to reduce on-state voltage drop. Simulation design verifies that compared with the groove type GCT under the same current working condition, the on-state loss and the off-state loss can be reduced simultaneously; the method is particularly suitable for the reverse resistance GCT, can reduce the sheet thickness, and realizes better design of blocking and compromise between on-state and off-state.
Compared with standard GCT of the same grade, the wavy GCT provided by the application has the advantage that the turn-off capability is improved by more than 20% through simulation. In the same on-state loss design structure, the loss is reduced by more than 10%. Therefore, the turn-off capability can be better improved, and the turn-off and on-state loss of the device can be conveniently designed in a compromise manner.
Example 1
The application is applied to a reverse-blocking gate commutated thyristor, as shown in fig. 3 and 4;
the structure of the reverse resistance type GCT chip is N from top to bottom + Emitter regions 1, P + Short base region 2, P base region 3, N - Base region 4, P-type anode emitter region 5 and P + An anode emission region 6; inverse resistance type GCT chip P + Short base regions 2 and N + The emitting areas 1 are positioned on the same side, P + Short base regions 2 and N + The emitter regions 1 are located on the same side, and the height difference (grooving depth) between the emitter regions is 0-30 μm. When the height difference is 0, the planar inverted resistance type GCT chip is adopted. The reverse resistance GCT chip is divided into four working states: blocking, triggering (on), on state and off, the working process is as follows:
blocking state: when the anode-cathode is between (P + Anode emitter region 6-N + Emitter zone 1) application ofForward voltage V DC The device is in a forward blocking state, and the blocking voltage is mainly formed by a reverse biased J2 junction (P base region 3-N - PN junction formed by the base region). When the anode-cathode is between (P + Anode emitter region 6-N + Emitter region 1) application of reverse voltage-V DC The device is in a reverse blocking state, the blocking voltage is mainly formed by a reverse biased J1 junction 11 (N - The PN junction formed by the base-P type anode emitter region 5). However, the GCT blocks the device gate-cathode J3 junction 13 (N + Emitter regions 1 and P + PN junction formed by the short base region 2) is applied with a reverse bias voltage (or short circuit) within-20V to avoid the significant reduction of the device withstand voltage due to the positive bias injection effect of the J3 junction 13.
Triggering (opening) procedure: before triggering, the device is in a blocking state, namely the J2 junction 12 and the J3 junction 13 are in a reverse bias blocking state. Applying a positive bias voltage to the gate-cathode (J3 junction 13) of the chip and the gate forward pulse current amplitude (I GT ) And the rising rate (di/dt) is large enough, at this time, the J3 junction 13 will uniformly inject electrons and finally pump away from the anode terminal through diffusion, and the PNP tube J1 junction 11 will uniformly inject holes and finally pump away from the cathode terminal through diffusion. When the sum of the current amplification coefficients of the two equivalent transistors is greater than 1 (i.e., alpha PNP +α NPN >1) When the GCT is in the high-resistance state, the GCT is turned on and kept in the holding state, and the GCT is macroscopically converted from the high-resistance state to the low-resistance state.
On state: the GCT enters a conducting state after being turned on, and the device shows the characteristics of a thyristor. Due to the "holding" effect, the GCT can remain on in the forward direction even if the gate current is removed. Meanwhile, due to the conductance modulation effect generated by bipolar carriers of the N base region and the P base region, the GCT has the advantages of low on-state voltage and strong through-current capability.
The turn-off process is as follows: applying a-20V bias to the gate-cathode of the GCT in conduction turns off the J3 junction 13 and the cathode current is switched all the way to the gate (i.e., hard off) before the voltage of the J2 junction 12 rises, the GCT enters the PNP tube mode of operation with an open base. At this time, the excessive electron carriers of the N-base region diffuse and pass through the anode J1 to be extracted, and the excessive hole carriers of the P base region are extracted and discharged through the gate electrode, so that the anode current of the GCT is reliably turned off in a very short time, and the J2 junction 12 recovers blocking capability. Macroscopically, the GCT switch is converted from a low-resistance state to a high-resistance state.
N + The doping concentration of the emitter region 1 is 1E16cm -3 -1E22cm -3 The diffusion depth is 5-40 μm;
P + the doping concentration of the short base region 2 is 1E15cm -3 -5E18cm -3 The diffusion depth is about 20 μm-80 μm; wherein, as shown in FIG. 4, P in the reverse resistance GCT chip structure + The short base region 2 is divided into N + P directly under the emitter region 1 1 + Short base region and P 1 + P on both sides of short base region 2 + A short base region; introduction of P 1 + Design of short base region, consisting of N + Emitter regions 1, P 1 + Short base region and N - Base formed equivalent NPN transistor (equivalent current gain alpha thereof NPN1 ) Leading the chip to open the function, thereby solving the problem of free regulation and control of the opening characteristic and the on-state loss; introduction of P 2 + Design of short base region, consisting of N + Emitter regions 1, P 2 + Short base region and N - Base formed equivalent NPN transistor (equivalent current gain alpha thereof NPN2 ) For leading the chip turn-off function, the problem of free regulation and control of the turn-off capability and turn-off loss of the GCT is solved.
The doping concentration of the P base region 3 is 1E13cm -3 -2E16cm -3 The diffusion depth is 60-200 μm, which depends on the design of the compromise between the blocking voltage and the on-state loss;
the J2 junction 12 of the P base region 3 is rectangular, trapezoidal, conical or multi-step, and the shape design determines the transverse electric field strength, electric field distribution and NPN transistor current gain alpha NPN2 The size is designed according to the compromise between the turn-off capability and the on-state loss characteristic. When the IGCT is turned off, on one hand, a transverse electric field of a J2 junction is utilized to rapidly extract hole carriers in the area below the cathode comb strip; on the other hand, the control by the J2 junction shape design is controlled by N + Emitter regions 1, P 2 + Short base region and N - Base region formed equivalent NPN transistor current gain alpha NPN2 Reducing the electron emission efficiency of the cathode, thereby integratingThe carrier concentration below the cathode sliver is reduced, and the shutdown re-triggering failure is avoided, so that the shutdown capability of the chip is improved, and the shutdown loss of the device is controlled.
N - The doping concentration and width of the base region 4 depend on the blocking voltage design;
the doping concentration of the P-type anode emission region 5 is 1E13cm -3 -2E16cm -3 The diffusion depth is 60-200 μm, which depends on the design of the compromise between the blocking voltage and the on-state loss;
P + the doping concentration of the anode emitter region 6 was 1E15cm -3 -5E18cm -3 The diffusion depth is 0.5-80 μm, and depends on the compromise design of the on-state loss of the device;
the P is + The short base region 2 is typically drawn through one or more overlying gate metal layers 10;
the N is + The emitter region 1 is typically drawn through one or more stacked gate metal layers 10;
the P is + The anode emissive region 6 is typically drawn through one or more stacked gate metal layers 10.
Example two
The application is applied to an asymmetric gate commutated thyristor, as shown in fig. 5-7;
wherein the asymmetric GCT chip (GCT chip) structure comprises an N+ emitter region 1, a P+ short base region 2, a P base region 3 and an N from top to bottom - Base region 4 (or N' -containing buffer layer 7) and P + An anode emission region 6; the asymmetric GCT chip is divided into four working states: blocking, triggering (on), on state and off, the working process is as follows:
blocking state: when the anode-cathode is between (P + Anode emitter region 6-N + Emitter region 1) applying a forward voltage V DC The device is in a forward blocking state, and the blocking voltage is mainly formed by a reverse biased J2 junction (P base region 3-N - PN junction formed by the base region). However, when GCT is blocked, the junction between the device gate and the cathode J3 (N + Emitter regions 1 and P + The PN junction formed by the short base region 2 is applied with a reverse bias voltage (or short circuit) within minus 20V to avoid the positive bias injection due to the J3 junctionThe device withstand voltage is significantly reduced by the in-effect.
Triggering (opening) procedure: before triggering, the device is in a blocking state, namely the J2 junction 12 and the J3 junction 13 are in a reverse bias blocking state. Applying a positive bias voltage to the gate-cathode (J3 junction 13) of the chip and the gate forward pulse current amplitude (I GT ) And the rising rate (di/dt) is large enough, at this time, the J3 junction 13 will uniformly inject electrons and finally pump away from the anode terminal through diffusion, and the PNP tube J1 junction 11 will uniformly inject holes and finally pump away from the cathode terminal through diffusion. When the sum of the current amplification coefficients of the two equivalent transistors is greater than 1 (i.e., alpha PNP +α NPN >1) When the GCT is in the high-resistance state, the GCT is turned on and kept in the holding state, and the GCT is macroscopically converted from the high-resistance state to the low-resistance state.
On state: the GCT enters a conducting state after being turned on, and the device shows the characteristics of a thyristor. Due to the "holding" effect, the GCT can remain on in the forward direction even if the gate current is removed. Meanwhile, due to the conductance modulation effect generated by bipolar carriers of the N base region and the P base region, the GCT has the advantages of low on-state voltage and strong through-current capability.
The turn-off process is as follows: applying a-20V bias to the gate-cathode of the GCT in conduction turns off the J3 junction 13 and the cathode current is switched all the way to the gate (i.e., hard off) before the voltage of the J2 junction 12 rises, the GCT enters the PNP tube mode of operation with an open base. At this time, the excessive electron carriers of the N-base region diffuse across the junction 11 of the transparent anode J1 (N' buffer layer 7 and P + PN junction formed by the anode emitter region 6), and excessive hole carriers of the P base region are extracted and discharged through the gate electrode, so that the anode current of the GCT is reliably turned off in a very short time, and meanwhile, the J2 junction 12 recovers blocking capability. Macroscopically, the GCT switch is converted from a low-resistance state to a high-resistance state.
The P+ short base region 2 and the N+ emitter region 1 of the GCT chip are positioned on the same side, the height difference (grooving depth) of the two is 0-30 mu m, and when the height difference is 0, the GCT chip is a plane type asymmetric GCT chip;
N + the doping concentration of the emitter region 1 is 1E16cm -3 -1E22cm -3 The diffusion depth is 5-40 μm;
P + the doping concentration of the short base region 2 is 1E15cm -3 -5E18cm -3 The diffusion depth is about 20 μm-80 μm;
the doping concentration of the P base region 3 is 1E13cm -3 -2E16cm -3 The diffusion depth is 60-200 μm, which depends on the design of the compromise between the blocking voltage and the on-state loss;
the J2 junction 12 of the P base region 3 is rectangular, trapezoidal, conical or multi-step, and the shape design determines the transverse electric field strength, electric field distribution and NPN transistor current gain alpha NPN2 The size is designed according to the compromise between the turn-off capability and the on-state loss characteristic; when the IGCT is turned off, on one hand, a transverse electric field of a J2 junction is utilized to rapidly extract hole carriers in the area below the cathode comb strip; on the other hand, the control by the J2 junction shape design is controlled by N + Emitter regions 1, P 2 + Short base region and N - Base region formed equivalent NPN transistor current gain alpha NPN2 The electron emission efficiency of the cathode is reduced, so that the carrier concentration below the cathode comb strip is comprehensively reduced, the shutdown re-triggering failure is avoided, the shutdown capability of the chip is improved, and the shutdown loss of the device is controlled.
N - The doping concentration and width of the base region 4 depend on the blocking voltage design;
an N' buffer layer 7 with a doping concentration of 1E12cm -3 -1E17cm -3 The diffusion depth is 10 μm-100 μm, and the design depends on the device voltage level.
P + Anode emitter region 6 with a doping concentration of 1E15cm -3 -5E18cm -3 The diffusion depth is 0.5-20 μm, and depends on the design of the on-state loss and the off-state loss characteristic compromise.
The P is + The short base region 2 is typically drawn through one or more stacked gate metal layers 10.
The N is + The emissive layer is typically drawn through one or more stacked gate metal layers 10.
The P is + The anode emitter region 6 is typically drawn through one or more stacked gate metal layers 10.
Example III
The application is applied to the reverse-conduction gate commutated thyristor, the GCT structure and the FRD structure are connected in anti-parallel through an NPN isolation structure to form a structure shown in figure 8, and the FRD is a fast recovery diode; the reverse-conduction GCT chip is divided into five working states: blocking, triggering (on), on state, off and reverse recovery state, the working process is as follows:
blocking state: when the anode-cathode is between (P + Anode emitter region 6/N + Cathode emission regions 16-N + Emitter region 1/P + Anode emitter 14) is applied with a forward voltage V DC The device is in a forward blocking state, and blocking voltage is mainly formed by reversed biased J2 junction 12 () P base region 3-N - Base region 4, P anode region 15-N - The PN junction formed by the base region 4). However, the GCT blocks the device gate-cathode J3 junction 13 (N + Emitter regions 1 and P + PN junction formed by the short base region 2) is applied with a reverse bias voltage (or short circuit) within-20V to avoid the significant reduction of the device withstand voltage due to the positive bias injection effect of the J3 junction 13.
Triggering (opening) procedure: before triggering, the device is in a blocking state, namely the J2 junction 12 and the J3 junction 13 are in a reverse bias blocking state. Applying a positive bias voltage to the gate-cathode (J3 junction 13) of the chip and the gate forward pulse current amplitude (I GT ) And the rising rate (di/dt) is large enough, at this time, the J3 junction 13 will uniformly inject electrons and finally pump away from the anode terminal through diffusion, and the PNP tube J1 junction 11 will uniformly inject holes and finally pump away from the cathode terminal through diffusion. When the sum of the current amplification coefficients of the two equivalent transistors is greater than 1 (i.e., alpha PNP +α NPN >1) When the GCT is in the high-resistance state, the GCT is turned on and kept in the holding state, and the GCT is macroscopically converted from the high-resistance state to the low-resistance state.
On state: the GCT enters a conducting state after being turned on, and the device shows the characteristics of a thyristor. Due to the "holding" effect, the GCT can remain on in the forward direction even if the gate current is removed. Meanwhile, due to the conductance modulation effect generated by bipolar carriers of the N base region and the P base region, the GCT has the advantages of low on-state voltage and strong through-current capability.
The turn-off process is as follows: applying a-20V bias to the gate-cathode of the GCT in conduction to turn off the J3 junction 13, and before the voltage of the J2 junction 12 rises, the cathode current is allSwitching to the gate (i.e., hard off), the GCT enters a PNP tube mode of operation with an open base, with the FRD already in a blocking state. At this time, the excessive electron carriers of the N-base region diffuse across the junction 11 of the transparent anode J1 (N' buffer layer 7 and P + PN junction formed by the anode emitter region 6), and excessive hole carriers of the P base region are extracted and discharged through the gate electrode, so that the anode current of the GCT is reliably turned off in a very short time, and meanwhile, the J2 junction 12 recovers blocking capability. Macroscopically, the GCT switch is converted from a low-resistance state to a high-resistance state.
Reverse recovery state: after the FRD structure of the GCT chip is reversely and completely conducted, the N-base region 4 is filled with a large amount of free carriers due to the phenomenon of conductivity modulation. When FRD structure between anode and cathode (P + Anode emitter region 6/N + Cathode emission regions 16-N + Emitter region 1/P + Anode emitter 14) is applied with a forward voltage V DC At this time, carriers in the N-base region need to be rapidly extracted to form a depletion layer wide enough to bear the withstand voltage, and holes are pulled to an anode (P) in the FRD structure by an electric field + Anode emitter region 14/N + Emitter 1), electrons are swept back by the electric field to the "cathode" (N) in the FRD structure + Cathode emission region 16/P + Anode emitter 6) to generate a reverse current and reach I soon RR . The carriers at the center in the body are then depleted through the recombination center and the IRR slowly reverts to 0. Macroscopically, the switch in GCT is converted from a low-resistance state to a high-resistance state.
Wherein the GCT chip structure is sequentially N from top to bottom + Emitter regions 1, P + Short base region 2, P base region 3, N - Base region 4 (or N' -containing buffer layer 7) and P + An anode emission region 6; the FRD chip structure is FRD-P from top to bottom + Anode emitter region 14, P anode region 15, N - Base region 4 (or N' -containing buffer layer 7), N + A cathode emission region 16; wherein the GCT chip and the FRD chip pass through N - Isolating base region 17 by P of GCT chip + Short base region 2/P base region 3, N-base region and FRD-P + The anode emitter/P-anode region 15 is laterally isolated by an NPN transistor structure, as shown in phantom in fig. 8.
Wherein,p of GCT chip + Short base regions 2 and N + The emitting area 1 is positioned on the same side, the height difference (grooving depth) of the emitting area and the emitting area is 0-30 mu m, and when the height difference is 0, the emitting area is a plane type asymmetric GCT chip;
n of GCT chip + The doping concentration of the emitter region 1 is 1E16cm -3 -1E22cm -3 The diffusion depth is 5-40 μm;
n in FRD structure in GCT chip + The doping concentration of the cathode emission region 16 is 1E16cm -3 -1E22cm -3 The diffusion depth is 5-60 μm;
p of GCT chip + The doping concentration of the short base region 2 is 1E15cm -3 -5E18cm -3 The diffusion depth is about 20 μm-80 μm;
p in FRD structure in GCT chip + The doping concentration of the anode emitter region 14 was 1E15cm -3 -5E18cm -3 The diffusion depth is about 20 μm-80 μm;
the doping concentration of the P base region 3 of the GCT chip and the P anode region 15 of the FRD chip is 1E13cm -3 -2E16cm -3 The diffusion depth is 60-200 μm, which depends on the design of the compromise between the blocking voltage and the on-state loss;
the doping concentration of the P anode region 15 in the FRD structure in the GCT chip is 1E13cm -3 -2E16cm -3 The diffusion depth is 60-200 μm, which depends on the design of the compromise between blocking voltage and reverse soft recovery characteristics;
the J2 junction 12 of the P base region 3 of the GCT chip is rectangular, trapezoidal, conical or multi-step and the like, and is designed specifically according to the compromise between the turn-off capability and the on-state loss characteristic; its shape design determines the transverse electric field strength, electric field distribution and NPN transistor current gain alpha NPN2 The size is designed according to the compromise between the turn-off capability and the on-state loss characteristic; when the IGCT is turned off, on one hand, a transverse electric field of a J2 junction is utilized to rapidly extract hole carriers in the area below the cathode comb strip; on the other hand, the control by the J2 junction shape design is controlled by N + Emitter regions 1, P 2 + Short base region and N - Base region formed equivalent NPN transistor current gain alpha NPN2 The electron emission efficiency of the cathode is reduced, thereby comprehensively reducing the carrier concentration below the cathode comb strip and avoiding turn-offAnd triggering failure again, so that the turn-off capability of the chip is improved and the turn-off loss of the device is controlled.
N of GCT chip and FRD chip - The doping concentration and width of the base region 4 depend on the design of the compromise between blocking voltage and reverse recovery characteristics;
N - isolation base region 17 has a doping concentration equal to N of GCT chip and FRD chip - The base region 4 has a surface isolation width L of typically 5 μm to 60 μm depending on the isolation electrical characteristic design.
N' buffer layer 7 of GCT chip and FRD chip with doping concentration of 1E12cm -3 -1E17cm -3 The diffusion depth is 10 μm-100 μm, and the design depends on the device voltage level.
P of GCT chip + Anode emitter region 6 with a doping concentration of 1E15cm -3 -5E18cm -3 The diffusion depth is 0.5-20 μm, and depends on the design of the on-state loss and the off-state loss characteristic compromise;
the P is + The short base region 2 is typically drawn through one or more stacked gate metal layers 10.
The N is + The emitter region 1 is typically drawn through one or more stacked gate metal layers 10.
The P is + The anode emitter region 6 is typically drawn through one or more stacked gate metal layers 10.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of protection of the application is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order and there are many other variations of the different aspects of one or more embodiments of the application as described above, which are not provided in detail for the sake of brevity.
One or more embodiments of the present application are intended to embrace all such alternatives, modifications and variations as fall within the broad scope of the present application. Accordingly, any omissions, modifications, equivalents, improvements and others which are within the spirit and principles of the one or more embodiments of the application are intended to be included within the scope of the application.
Claims (10)
1. A gate commutated thyristor chip, comprising: a cathode metal layer (8), a gate metal layer (10) located on both sides of the cathode metal layer (8), an anode metal layer (9) opposite to the cathode metal layer (8), and a semiconductor substrate formed between the cathode metal layer (8) and the anode metal layer (9);
the semiconductor substrate comprises a five-layer area structure or a six-layer area structure, and each structural area has different conductivity types;
the five-layer zone structure comprises: n in contact with the cathode metal layer (8) + Emitter region (1), gate metal layer (10) and N + P contacted by emitter region (1) + Short base region (2), P + A P base region (3) contacted with the short base region (2), and N contacted with the P base region (3) - Base region (4), and N - P with contact of base region (4) + An anode emission region (6); the P is + The anode emission area (6) is contacted with the anode metal layer (9);
the six-layer zone structure comprises: n in contact with the cathode metal layer (8) + Emitter region (1), gate metal layer (10) and N + P contacted by emitter region (1) + Short base region (2), P + A P base region (3) contacted with the short base region (2), and N contacted with the P base region (3) - Base region (4), and N - An N 'buffer layer (7) or a P-type anode emitter region (5) in contact with the base region (4), and P in contact with the N' buffer layer (7) or the P-type anode emitter region (5) + An anode emission region (6); the P is + The anode emission area (6) is contacted with the anode metal layer (9);
the P base region (3) has a convex structure, and the N is - The base region (4) has a concave structure, and the convex structure is embedded in the concave structure.
2. The method according to claim 1The gate commutated thyristor chip is characterized in that the N is as follows + The emitter region (1) is partially embedded with P + In the short base region (2), the embedding depth is 0-30 mu m.
3. The gate commutated thyristor chip of claim 1, wherein the N + The doping concentration of the emitter region (1) is 1E16cm -3 -1E22cm -3 The diffusion depth is 5 μm-40 μm.
4. The gate commutated thyristor chip of claim 1, wherein P is + The doping concentration of the short base region (2) is 1E15cm -3 -5E18cm -3 The diffusion depth is about 20 μm to 80 μm.
5. The gate-commutated thyristor chip according to claim 1, characterized in that the doping concentration of the P-base region (3) is 1E13cm -3 -2E16cm -3 The diffusion depth is 60 μm-200 μm.
6. The gate-commutated thyristor chip according to claim 1, characterized in that the doping concentration of the P-type anode emitter region (5) is 1E13cm -3 -2E16cm -3 The diffusion depth is 60 μm-200 μm.
7. The gate-commutated thyristor chip according to claim 1, characterized in that the doping concentration of the N' buffer layer (7) is 1E12cm -3 -1E17cm -3 The diffusion depth is typically 10 μm to 100 μm.
8. The gate commutated thyristor chip of claim 1, wherein P is + The doping concentration of the anode emission region (6) is 1E15cm -3 -5E18cm -3 The diffusion depth is 0.5 μm-80 μm.
9. A thyristor comprising a gate commutated thyristor chip according to any one of claims 1-8.
10. The thyristor according to claim 9, comprising the gate commutated thyristor chip and a fast recovery diode chip, the gate commutated thyristor chip and fast recovery diode chip being antiparallel formed into a thyristor by an NPN isolation structure.
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