CN111509047A - Graphene field effect transistor and preparation method thereof - Google Patents

Graphene field effect transistor and preparation method thereof Download PDF

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CN111509047A
CN111509047A CN202010191621.8A CN202010191621A CN111509047A CN 111509047 A CN111509047 A CN 111509047A CN 202010191621 A CN202010191621 A CN 202010191621A CN 111509047 A CN111509047 A CN 111509047A
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layer
graphene
silicon oxide
substrate
field effect
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CN111509047B (en
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王程
贾原
叶巍翔
张博
李扬
赵晓楠
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Tianjin Normal University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The present invention relates to a graphene field effect transistor, comprising: a substrate; the grid structure is arranged on the substrate, and a plurality of micron-scale or nano-scale grooves are formed on the surface of the grid structure; the graphene channel layer is arranged on the grid structure, spans the grooves and forms a plurality of first cavities with the grooves; the protective layer covers the graphene channel layer in an inverted U shape, and a second cavity is formed between the protective layer and the graphene channel layer; the first source electrode and the first drain electrode are arranged in the second cavity and are respectively positioned at two ends of the graphene channel layer; a second source and a second drain disposed outside the second cavity; and an electrically conductive layer disposed on the substrate in electrical communication with the first source electrode and the second source electrode. The invention also relates to a preparation method of the graphene field effect transistor.

Description

Graphene field effect transistor and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor electronic devices, in particular to a graphene field effect transistor and a preparation method thereof.
Background
A Graphene Field-Effect-Transistor (GFET) is a Transistor manufactured by using semiconductor characteristics of Graphene, wherein Graphene is used for forming a channel of the GFET, as shown in fig. 12, which is a schematic cross-sectional structure diagram of a conventional solid-state gate CVD Graphene Field-Effect Transistor, and the conventional solid-state gate CVD Graphene Field-Effect Transistor 200 includes a substrate 210, a gate 220 disposed on the substrate 210, a first solid-state dielectric layer 230 covering the gate 220, a Graphene channel layer 240 disposed on the first solid-state dielectric layer 230 and opposite to the gate 220, a source 251 and a drain 252 disposed on the first solid-state dielectric layer 230 and respectively connected to two ends of the Graphene channel layer 240, and a second solid-state dielectric layer 260 covering the Graphene channel layer 240.
The theoretical carrier mobility of the graphene can be as high as 2 × 105cm2Theoretically, electrons (or holes) in graphene can form maximum current under the driving of an electric field with the same intensity, and the graphene field effect transistor is expected to be an electronic device capable of realizing the fastest response and the most power saving, but the carrier mobility is reduced due to the scattering of electrons (holes) in graphene by a substrate, and the carrier mobility of the traditional graphene field effect transistor is only 1 × 104cm2around/Vs, far from the theoretical carrier mobility of graphene.
Based on this, a new graphene field effect transistor and a method for manufacturing the same are needed to improve carrier mobility.
Disclosure of Invention
Based on this, it is necessary to provide a novel graphene field effect transistor and a method for manufacturing the same, which can improve carrier mobility of the graphene field effect transistor.
The present invention provides a graphene field effect transistor, comprising: a substrate; the grid structure is arranged on the substrate, and a plurality of micron-scale or nano-scale grooves are formed on the surface of the grid structure; the graphene channel layer is arranged on the grid structure, spans the grooves and forms a plurality of first cavities with the grooves; the protective layer covers the graphene channel layer in an inverted U shape, and a second cavity is formed between the protective layer and the graphene channel layer; the first source electrode and the first drain electrode are arranged in the second cavity and are respectively positioned at two ends of the graphene channel layer; a second source and a second drain disposed outside the second cavity; and an electrically conductive layer disposed on the substrate in electrical communication with the first source electrode and the second source electrode.
In one embodiment, the first cavity and the second cavity are both in a vacuum state.
In one embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer.
In one embodiment, the semiconductor device further includes an insulating layer disposed on the substrate and adjacent to the second source or the second drain.
In one embodiment, the graphene channel layer is a large-area graphene thin film with uniform synthesis performance.
The invention also provides a preparation method of the graphene field effect transistor, which comprises the following steps:
providing a substrate, wherein a silicon oxide layer is formed on the substrate;
forming a gate structure precursor and an electrically conductive layer under the silicon oxide layer of the substrate;
removing a portion of the silicon oxide layer, forming a first silicon oxide layer and a second silicon oxide layer with spaces on the electrically conductive layer and the substrate to expose the gate structure precursor and source and drain regions to be disposed;
etching a plurality of grooves on the grid structure precursor, and then covering a dielectric to form a grid structure;
a first drain electrode and a second drain electrode are respectively arranged at two ends of the first silicon oxide layer, and a first source electrode and a second source electrode are respectively arranged at two ends of the second silicon oxide layer;
arranging a graphene channel layer on the grid structure, wherein two ends of the graphene channel layer are respectively connected with a first source electrode and a first drain electrode, and a plurality of first cavities are formed between the graphene channel layer and the grooves; and
bonding another silicon oxide layer between the first silicon oxide layer and the second silicon oxide layer to form an inverted U-shaped protection layer, wherein a second cavity is formed between the protection layer and the graphene channel.
In one embodiment, the step of etching a plurality of recesses in the gate structure precursor comprises:
forming a high-resolution precise photoresist optical layer on the exposed area after removing part of the silicon oxide layer, and carrying out photoetching patterning on the precise photoresist optical layer to expose a groove area to be etched; and etching the groove area to be etched.
In one embodiment, the precision photoresist optical layer is formed by using an electron beam photoresist or an extreme ultraviolet photoresist.
In one embodiment, the graphene channel layer is a graphene thin film deposited by Chemical Vapor Deposition (CVD).
In one embodiment, the first cavity and the second cavity are vacuumized, so that the pressure on two sides of graphene in the graphene conductive channel layer is 0.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a graphene field effect transistor according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a graphene field effect transistor according to an embodiment of the present invention;
fig. 3 to 10 are schematic cross-sectional structures of intermediate structures of a method for manufacturing a graphene field effect transistor according to an embodiment of the present invention;
FIG. 11 is a schematic flow chart illustrating the formation of a recess in a gate structure according to an embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view of a conventional solid-state gate CVD graphene field effect transistor;
fig. 13 is a graph of carrier mobility for a graphene field effect transistor and a conventional solid-state gate CVD graphene field effect transistor according to an embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The inventors found that the main reason for the low carrier mobility of graphene-based field effect transistors is that: in a traditional graphene field effect transistor device, a graphene channel layer is attached to a solid substrate, the roughness and pollution impurities of the substrate can destroy the periodicity of graphene lattices through long-range coulomb scattering and short-range non-coulomb scattering, and the excellent carrier mobility performance of graphene is greatly reduced.
Therefore, the invention provides a graphene field effect transistor with a suspended graphene channel layer. Referring to fig. 1, a graphene field effect transistor 100 according to an embodiment of the present invention includes a substrate 110, a gate structure 120 and an electrically conductive layer 130 disposed on the substrate 110, a graphene channel layer 140 disposed on the gate structure 120, a protection layer 150 covering the graphene channel layer 140 in an inverted U shape, and a source and a drain. A plurality of grooves 121 are formed on the surface of the gate structure 120. The graphene channel layer 140 spans a plurality of the grooves 121. A plurality of first cavities 180 are formed between the plurality of grooves 121 and the graphene channel layer 140. A second cavity 190 is formed between the protection layer 150 and the graphene channel layer 140. The source includes a first source 161 and a second source 162, and the drain includes a first drain 171 and a second drain 172. The first source electrode 161 and the first drain electrode 171 are disposed in the second cavity 180 and located at two ends of the graphene channel layer 140, respectively. The second source 162 and the second drain 172 are disposed outside the second cavity 190. The first source electrode 161 and the second source electrode 162 are disposed on the substrate 110, and are electrically connected through the substrate 110. The first drain electrode 171 and the second drain electrode 172 are both disposed on an electrically conductive layer 130, through which electrical communication is made.
According to the graphene field effect transistor 100 provided by the invention, the plurality of grooves 121 are formed in the gate structure 120, and the plurality of first cavities 180 are formed between the plurality of grooves 121 and the graphene channel layer 140, so that the graphene channel layer 140 is partially suspended, the influence of the substrate on graphene is reduced, and the carrier mobility of graphene is improved. In addition, the protection layer 150 may prevent the graphene from being contaminated by external contaminants to affect the stability of the carrier mobility of the graphene. Therefore, the graphene field effect transistor 100 has high carrier mobility and stability, and the consistency of the same batch production can be improved by using the device of the graphene field effect transistor 100 of the present invention.
The substrate 110 may be a silicon substrate or a semiconductor substrate formed of other materials, such as germanium. The substrate 110 may be a doped semiconductor substrate. The doped semiconductor substrate can be an n-type doped semiconductor substrate or a p-type doped semiconductor substrate. In one embodiment, the substrate 110 is a p-type doped silicon substrate.
The gate structure 120 may include a gate electrode layer 122 and a gate dielectric layer 124. The gate electrode layer 122 is disposed on the substrate 110, and the gate dielectric layer 124 is disposed on the gate electrode layer 122, as shown in fig. 7.
The gate electrode layer 122 may be formed of any suitable material. In one embodiment, the gate electrode layer 122 may be formed of a metal material. An insulating layer (e.g., SiO) may be formed between the gate electrode layer 122 and the substrate 1102An insulating layer). The metal material may be at least one of Ti, Pt, Cr, Au, Al, Ni, Cu, Ag, and the like. In another embodiment, the substrate 110 is a doped semiconductor substrate, and the doped semiconductor substrate may be directly doped with a local complementary dopant to form the gate electrode layer 122. For example, a p-doped silicon substrate may be locally heavily n-doped to form conductive gate electrode layer 122.
The material of the gate dielectric layer 124 may be a high-k dielectric material. The material of the gate dielectric layer 124 may include HfO2、ZrO2And Al2O3At least one of (1). In one embodiment, the material of the gate dielectric layer 124 is hafnium aluminum oxide composite (Hf)xAlyO2From HfO2With Al2O3Composite formation). The thickness of the gate dielectric layer 124 may be 1nm to 100 nm. Preferably, the thickness of the gate dielectric layer 124 is 10nm to 15nm, which does not induce a pinhole breakdown risk. The gate dielectric layer 124 can be prepared by atomic layer evaporation deposition, and the gate dielectric layer prepared by the method is better in uniformity and coverage. Dry oxygen oxidation (using O3 precursor) is preferred to avoid the risk of pinhole breakdown from steam oxidation.
A plurality of recesses 121 are formed in the gate electrode layer 122. The shape of the groove 121 is not limited, and may be any shape, such as a cylinder, a rectangular parallelepiped, a cube, a sphere, a cone, and the like. The shape and size of the grooves 121 and the spacing between the grooves affect the carrier mobility of the graphene fet.
In one embodiment, the groove 121 is cylindrical, the diameter of the cylindrical groove is 400nm to 600nm, and the depth of the cylindrical groove is 50nm to 150 nm. In one embodiment, the number of the grooves 121 is multiple, and the distance between the centers of the adjacent grooves 121 is 0.5 μm to 2 μm. Preferably, the spacing between adjacent grooves is the same.
In one embodiment, every adjacent four of the grooves are arranged in a square shape.
In order to obtain better carrier mobility, the ratio of the total area of the grooves 121 to the area of the graphene conductive channel layer 140 is greater than or equal to pi/16.
The electrically conductive layer 130 may be formed of any electrically conductive material. In one embodiment, the electrically conductive layer may be formed of a metal material. In another embodiment, the substrate 110 is a doped semiconductor substrate, and the electrically conductive layer 130 may be formed by directly performing local complementary doping on the doped semiconductor substrate.
The graphene channel layer 140 may be at least one of single-layer graphene, double-layer graphene, and multi-layer graphene. Single layer graphene is preferred. The graphene channel layer 140 may be disposed vertically above the gate structure 120.
The graphene channel layer 140 may be formed by a chemical vapor deposition method to form a graphene thin film, and then the graphene thin film is transferred onto the gate structure 120.
The source electrode (including first source electrode 161 and second source electrode 162) and the drain electrode (including first drain electrode 171 and second drain electrode 172) may be formed of any suitable material. For example, the material of the source electrode and the drain electrode may include at least one of Ti, Pt, Cr, Au, Al, Ni, Cu, Ag, ITO, and the like. The source electrode and the drain electrode may be the same material. The source electrode and the drain electrode may be simultaneously formed in the same process.
In one embodiment, the first source electrode 161 and the first drain electrode 171 partially overlap the gate dielectric layer 124.
In an embodiment, the first source electrode 161 and/or the first drain electrode 171 are partially covered by the graphene channel layer.
The material of the protection layer 150 is an insulating material, preferably silicon oxide. Preferably, the protection layer 150 is in contact with the first source electrode 161, the second source electrode 162, the first drain electrode 171, and the second source electrode 172.
In order to ensure that no conductive part except for an electrode in the graphene field effect transistor 100 is exposed, in an embodiment, the graphene field effect transistor 100 further includes an insulating layer 102, and the insulating layer 102 is disposed on the substrate 100 and adjacent to the second source 162 or the second drain 172. The material of the insulating layer 102 may be the same as that of the protective layer 150. Preferably silicon oxide.
Referring to fig. 2, the present invention further provides a method for manufacturing the graphene field effect transistor, including:
s10, providing a substrate 110, wherein a silicon oxide layer 112 is formed on the substrate 110;
s20, forming a gate structure precursor 126 and an electrically conductive layer 130 under the silicon oxide layer 112 of the substrate 110;
s30, removing a portion of the silicon oxide layer, forming a first silicon oxide layer 114 and a second silicon oxide layer 116 with a gap between the conductive layer 130 and the substrate 110 to expose the gate structure precursor 126 and the source and drain regions to be disposed;
s40, etching a plurality of grooves 121 on the gate structure precursor 126, and then covering a dielectric (i.e., the gate dielectric layer 124) to form a gate structure 120;
s50, disposing a first drain 171 and a second drain 172 at two ends of the first silicon oxide layer 114, and disposing a first source 161 and a second source 162 at two ends of the second silicon oxide layer 116;
s60, disposing a graphene channel layer 140 on the gate structure 120, where two ends of the graphene channel layer 140 are respectively connected to the first source 161 and the first drain 171, and a plurality of first cavities 180 are formed between the graphene channel layer 140 and the groove 121; and
s70, bonding another silicon oxide layer between the first silicon oxide layer and the second silicon oxide layer to form an inverted U-shaped protection layer 150, and forming a second cavity 190 between the protection layer 150 and the graphene channel 140.
According to the preparation method of the graphene field effect transistor, the field effect transistor with high carrier mobility, good consistency and stable performance can be prepared in a large batch. Unless otherwise specified, various structures of the present invention may be provided, prepared, or formed using processes known in the art.
The method for manufacturing the graphene field effect transistor according to the present invention is described in detail below with reference to fig. 3 to 11.
Referring to FIG. 3 and step S10, a substrate 110 is provided, a silicon oxide layer 112 is formed on the substrate 110, and in one embodiment, SiO may be grown on the substrate 1102A thin film constituting the silicon oxide layer 112.
The substrate 110 may be a silicon substrate or a semiconductor substrate formed of other materials, such as germanium. The substrate 110 as the present invention may be a doped semiconductor substrate. The doped semiconductor substrate can be an n-type doped semiconductor substrate or a p-type doped semiconductor substrate. Hereinafter, a method for manufacturing a graphene field effect transistor will be described by taking a p-type doped semiconductor substrate as an example.
Referring to fig. 4 and step S20, a gate structure precursor 126 and an electrically conductive layer 130 are formed under the silicon oxide layer 112 of the substrate 110.
In one embodiment, the step of forming the gate structure precursor 126 and the electrically conductive layer 130 comprises:
s21, performing photolithography patterning on the substrate 110 with the silicon oxide layer 112 to expose the region where the gate structure precursor 126 and the electrically conductive layer 130 are to be formed; and
s22, the p-doped silicon substrate 110 is locally heavily doped n-type to form the gate structure precursor 126 and the electrically conductive layer 130.
The method may further include a step of repairing the silicon oxide layer 112, and specifically, the substrate 110 may be heated to 500 to 600 ℃ for 20 to 40 minutes.
Referring to fig. 5 and step S30, a portion of the silicon oxide layer is removed, and a first silicon oxide layer 114 and a second silicon oxide layer 116 are formed on the electrically conductive layer 130 and the substrate 110 with a space therebetween to expose the gate structure precursor 126 and the source and drain regions to be disposed.
The method for removing part of the silicon oxide layer may be any one of the prior art. In one embodiment, photolithographic patterning is performed on the silicon oxide layer 112 to expose areas of the silicon oxide layer to be removed, and then the exposed areas are etched. The photoresist is preferably a positive photoresist. The etching is preferably performed with a wet chemical etchant including, but not limited to, a hydrofluoric acid solution.
In step S30, the silicon oxide layer is partially removed for the purpose of exposing the gate structure precursor 126 and the source and drain regions to be disposed and forming the first silicon oxide layer 114 and the second silicon oxide layer 116 with a space therebetween. A first silicon oxide layer 114 is on the electrically conductive layer 140, i.e., the drain region, and a second silicon oxide layer 116 is on the source region of the substrate 110. In one embodiment, in order to prevent the conductive portions of the graphene fet 100 from being exposed except for the electrodes, a silicon oxide layer, such as the insulating layer 102, is remained in other positions.
Referring to fig. 6 and step S40, a plurality of recesses 121 are etched in the gate structure precursor 126 to form the gate electrode layer 122, and then a gate structure 120 is formed overlying the dielectric (i.e., gate dielectric layer 124).
In one embodiment, referring to fig. 11, the step of etching a plurality of grooves 121 on the gate structure precursor 126 includes:
s41, forming a high-resolution precise photoresist optical layer 118 on the exposed region after removing part of the silicon oxide layer 112, and performing photolithography patterning on the precise photoresist layer 118 to expose the region of the groove 121 to be etched; and
and S42, etching the area of the groove 121 to be etched.
The nanometer-scale grooves are prepared by using the optical resolution precision photoresist. The precision photoresist photo layer 118 is formed using an electron beam photoresist or an extreme ultraviolet photoresist. In one embodiment, the precision photoresist optical layer 118 is formed using a positive electron beam resist, polymethyl methacrylate. The precision photoresist optical layer 118 may block subsequent etching steps.
The etching method may be any one of the prior art, and in an embodiment, the groove 121 is formed by plasma dry etching. The plasma may be, but is not limited to, sulfur hexafluoride (SF)6) Carbon tetrafluoride (CF)4) And mixing oxygen (O) in various proportions2). Adjusting the plasma etch power and time controls the depth of the recess 121.
In an embodiment, after step S42 is completed, the precision photoresist is not removed, and a second photolithography patterning is directly performed to expose only the region where the gate dielectric layer 124 is to be disposed. And removing the precision photoresist after the dielectric is deposited, wherein the dielectric layer only covers the gate structure 120 region, or covers the gate structure 120 region and the range of 1-10 μm around the gate structure 120 region, so that the gate dielectric layer 124 is partially overlapped with the first source electrode 161 and the first drain electrode 171.
The dielectric may be formed over the gate electrode layer 122, forming a gate dielectric layer 124, as shown in fig. 7, in a process known to those skilled in the art. Since the recess 121 is smaller in size, the gate electrode layer cannot be shown in the same figure, and the gate structure 120 is described as a whole in the remaining figures. Preferably, an atomic layer vapor deposition process is used to grow a dielectric layer on the gate electrode layer 126 to form the gate dielectric layer 124, and the gate dielectric layer manufactured by the method has better uniformity and coverage.
Referring to fig. 8 and step S50, a first drain 171 and a second drain 172 are disposed at two ends of the first silicon oxide layer 114, and a first source 161 and a second source 162 are disposed at two ends of the second silicon oxide layer 116.
In one embodiment, step S50 includes:
s51, performing photolithography patterning on the substrate on which the gate structure 120, the electrically conductive layer 130, and the first and second silicon oxide layers 114 and 116 are formed after the step S40, to expose only regions where the source and the drain are to be disposed; and
s52, metal is deposited to form the first source 161, the second source 162, the first drain 171, and the second drain 172.
Referring to fig. 9 and step S60, a graphene channel layer 140 is disposed on the gate structure 120, two ends of the graphene channel layer 140 are respectively connected to the first source 161 and the first drain 171, and a plurality of first cavities 180 are formed between the graphene channel layer 140 and the groove 121.
In an embodiment, the step of disposing the graphene channel layer 140 on the gate structure 120 includes:
s61, preparing a graphene layer, transferring the graphene layer onto the structure prepared in step S50, so that the graphene covers at least the gate structure 120 and connects the first source electrode 161 and the first drain electrode 171;
s62, performing photolithography patterning on the graphene, and reserving a region where the graphene channel layer 140 is to be disposed; and
and S63, removing the graphene in the reserved area.
The graphene layer can be prepared by a chemical vapor deposition method (such as low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition), and a high-quality large-area graphene film can be obtained.
The method for removing graphene may be any one of the prior art. In one embodiment, a plasma dry etch is used. Preferably, the plasma is pure oxygen.
Referring to fig. 10 and step S70, another silicon oxide layer 117 is bonded between the first silicon oxide layer 114 and the second silicon oxide layer 116 to form an inverted U-shaped protection layer 150. A second cavity 190 is formed between the protective layer 150 and the graphene channel 140. The protective layer 150 covers the first source electrode 161, the first drain electrode 171, and the graphene channel layer 140.
The bonding between the first silicon oxide layer 114 and the second silicon oxide layer 116 and the further silicon oxide layer 117 may be performed by any method known in the art, and in an embodiment, may be performed by using a vacuum bonding machine.
The silicon oxide layer 117 may be the silicon oxide layer removed in the above step S30.
In an embodiment, the method for manufacturing the graphene field effect transistor further includes performing vacuum-pumping processing on the first cavity 180 and the second cavity 190, so that the pressure at two sides of the graphene in the graphene conducting channel layer is 0, and the graphene conducting channel layer is kept in a suspended state.
The graphene channel layer in the graphene field effect transistor obtained by the preparation method can generate mechanical displacement (such as up-down shaking).
The photoresist used in the photolithographic patterning in the present invention is not particularly limited, and a positive photoresist is preferably used. Methods for removing the photoresist include, but are not limited to, oxygen plasma dry etching, sulfuric acid and hydrogen peroxide wet chemical reaction, and the like, which are known to those skilled in the art.
The following are specific examples.
Example 1
S10, providing n-2 × 10 impurity concentration16cm-3The boron-doped p-type silicon wafer of (1), the surface of the silicon wafer having a silicon dioxide layer of about 100nm to form ion jet scattering.
S20, carrying out photoetching and patterning on the silicon wafer substrate to expose the region where the gate structure precursor and the electric conduction layer are to be formed, injecting phosphorus element into the exposed region and carrying out annealing activation to form the silicon wafer substrate with the thickness of about 500nm and the impurity concentration of about 2 × 1018cm-3Is heavily doped with n-type gate. Wherein, when injecting phosphorus element, the ion injection energy is about 150keV, the beam density of phosphorus element is about 1015cm-2. The annealing activation condition was annealing at 1050 ℃ for 30 seconds.
S30, performing a photo-etching pattern on the silicon dioxide layer to expose the gate structure precursor and the source and drain regions to be formed, removing the exposed silicon dioxide layer with a buffered oxide etching solution (BOE), and removing the photoresist to form a first silicon oxide layer and a second silicon oxide layer.
S40, forming a high-molecular layer on the exposed area after removing part of the silicon oxide layer by using positive electron beam resist polymethyl methacrylate (PMMA)And a resolution precision photoresist photosphere is used for carrying out photoetching patterning and plasma dry etching, a plurality of cylindrical nano-scale grooves which are arranged at equal intervals are etched on the grid structure precursor, the diameter d of each groove is 500nm, the depth h of each groove is 100nm, every two adjacent grooves are arranged in a square mode, and the distance between the centers of the adjacent grooves is 1 mu m. Carrying out secondary exposure and development on the precise photoresist photosphere to only expose the region of the gate dielectric layer to be arranged, and growing a layer of HfO with the thickness of 15nm on the gate structure precursor by using an atomic layer evaporation deposition process2A dielectric (i.e., a gate dielectric layer) forming a gate structure.
S50, carrying out photoetching patterning and metal deposition on the substrate on which the grid structure, the electric conduction layer, the first silicon oxide layer and the second silicon oxide layer are formed to manufacture a source electrode and a drain electrode, wherein the source electrode comprises a first source electrode and a second source electrode, the drain electrode comprises a first drain electrode and a second drain electrode which are both of double-layer metal structures, the inner layer is a chromium or titanium adhesion layer with the thickness of 5nm, and the outer layer is gold or platinum with the thickness of 45 nm. The first drain electrode and the second drain electrode are arranged at two ends of the first silicon oxide layer, and the first source electrode and the second source electrode are arranged at two ends of the second silicon oxide layer.
And S60, preparing a graphene layer, transferring the graphene layer to the structure prepared in the step S50, enabling graphene to at least cover the gate structure, connecting a first source electrode and a first drain electrode (covering part of the first source electrode and the first drain electrode), carrying out photoresist patterning and plasma etching on the graphene layer, and obtaining the length L of the graphene channel, the width W of the graphene channel and the width W of the graphene channel, wherein the graphene channel is partially suspended on the groove and forms a plurality of first cavities together with the groove, and the ratio of the total area of the suspended part of graphene to the area of the graphene conductive channel is about pi/16.
And S70, bonding another silicon oxide layer between the first silicon oxide layer and the second silicon oxide layer through a vacuum bonding machine, and forming a second cavity between the protective layer and the graphene channel, wherein in the vacuum bonding process, the two cavities are both in a vacuum state.
The carrier mobility of the graphene field effect transistor prepared in the above example was measured, and the result is shown in fig. 13, comparing with the conventional solid gate CVD graphene field effect transistor (structure is shown in fig. 12). During the test, the carrier mobility was measured using 3 graphene field effect transistors prepared in the above examples and 3 conventional solid gate CVD graphene field effect transistors under the same experimental conditions. As can be seen from the figure, compared with the conventional solid-state gate CVD graphene field effect transistor, the carrier mobility of the graphene field effect transistor prepared in the above embodiment is significantly improved, and the uncertainty range of the mobility is very small (basically close to that of the conventional solid-state gate CVD graphene field effect transistor), which indicates that the stability and consistency of the carrier mobility of the graphene field effect transistor prepared in the above embodiment are good, and the large-scale integrated tape-out manufacturing is facilitated. The method for measuring the carrier mobility is a method commonly used by those skilled in the art.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
The invention is supported by the following researches, namely, China national natural science fund (61901300), Jiangsu province natural science fund (BK20180384), Tianjin City natural science fund (18JCYBJC86000,18JCYBJC86400 and 19JCQNJC01300), Tianjin City instructor scientific research plan (2018KJ153,2019KJ087), Tianjin facultative university talent introduction fund (011/5R L153).

Claims (10)

1. A graphene field effect transistor, comprising:
a substrate;
the grid structure is arranged on the substrate and is provided with a plurality of micron-scale or nano-scale grooves;
the graphene channel layer is arranged on the grid structure, spans the grooves and forms a plurality of first cavities with the grooves;
the protective layer covers the graphene channel layer in an inverted U shape, and a second cavity is formed between the protective layer and the graphene channel layer;
the first source electrode and the first drain electrode are arranged in the second cavity and are respectively positioned at two ends of the graphene channel layer;
a second source and a second drain disposed outside the second cavity; and
an electrically conductive layer disposed on the substrate in electrical communication with the first source electrode and the second source electrode.
2. The graphene field effect transistor of claim 1, wherein the first cavity and the second cavity are both in a vacuum state.
3. The graphene field effect transistor of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer.
4. The graphene field effect transistor of claim 1, further comprising an insulating layer disposed on the substrate and adjacent to the second source or the second drain.
5. The graphene field effect transistor according to claim 1, wherein the graphene channel layer is a graphene thin film with uniform large-area synthesis performance.
6. The method for preparing the graphene field effect transistor according to any one of claims 1 to 5, comprising:
providing a substrate, wherein a silicon oxide layer is formed on the substrate;
forming a gate structure precursor and an electrically conductive layer under the silicon oxide layer of the substrate;
removing a portion of the silicon oxide layer, forming a first silicon oxide layer and a second silicon oxide layer with spaces on the electrically conductive layer and the substrate to expose the gate structure precursor and source and drain regions to be disposed;
etching a plurality of grooves on the grid structure precursor, and then covering a dielectric to form a grid structure;
a first drain electrode and a second drain electrode are respectively arranged at two ends of the first silicon oxide layer, and a first source electrode and a second source electrode are respectively arranged at two ends of the second silicon oxide layer;
arranging a graphene channel layer on the grid structure, wherein two ends of the graphene channel layer are respectively connected with a first source electrode and a first drain electrode, and a plurality of first cavities are formed between the graphene channel layer and the grooves; and
bonding another silicon oxide layer between the first silicon oxide layer and the second silicon oxide layer to form an inverted U-shaped protection layer, wherein a second cavity is formed between the protection layer and the graphene channel.
7. The method of claim 6, wherein the step of etching a plurality of recesses in the gate structure precursor comprises:
forming a high-resolution precise photoresist optical layer on the exposed area after removing part of the silicon oxide layer, and carrying out photoetching patterning on the precise photoresist optical layer to expose a groove area to be etched; and etching the groove area to be etched.
8. The method of claim 7, wherein the precision photoresist optical layer is formed using an electron beam photoresist or an extreme ultraviolet photoresist.
9. The method of manufacturing a graphene field effect transistor according to claim 6, wherein the graphene channel layer is a graphene thin film deposited by chemical vapor deposition.
10. The method for manufacturing the graphene field effect transistor according to claim 6, further comprising vacuumizing the first cavity and the second cavity so that the pressure on two sides of the graphene in the graphene conductive channel layer is 0.
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