TWI765717B - Reconfigurable quantum electronic device - Google Patents

Abstract

This invention provides a reconfigurable quantum electronic device, which includes a semiconductor substrate, and at least one quantum unit. The quantum unit comprises two conductive ridges, a quantum dot, an isolation layer, and an electrode group. The conductive ridges are arranged on the semiconductor substrate at an angle to each other to define an angled area. The quantum dot is formed on the semiconductor substrate and located within the angled area. The quantum dot is surrounded by the isolation layer. The electrode group is arranged between the conductive ridges, and aligned with the quantum dot.

Description

Configurable quantum electronics

The present invention relates to a quantum electronic component, particularly a configurable quantum electronic component.

Since the birth of quantum computer (QC), extensive research on superconducting circuits and semiconductor quantum dots (quantum dots QDs) has enabled quantum bit (qubit) technology to achieve remarkable progress in a wide range of applications.

Another application of quantum dots is a single electron transistor (SET) that can effectively control the change of a single charge. It uses quantum dots as the basic core, and uses quantum dots to have a unique coulomb blockade (coulomb blockade). It is increasingly important to operate single-electron or hole changes by the effect of single-electron transistors, which can be used as logic elements and memory elements, and integrated with field-effect transistors.

Generally, there are common process methods for forming semiconductor quantum dots, such as electrical quantum dots formed by constraining the carrier density by an electric field, or physical quantum dots formed by lithography and etching.

The advantage of using the electric field confinement method is that it is highly controllable, and the energy level or spin characteristics of quantum dots can be adjusted through electrodes, but multiple electrodes need to be fabricated, so there are disadvantages of large area and serious parasitic capacitance effects; Although the lithography and etching process can use the advanced and mature CMOS lithography and etching process method to define the production of semiconductor quantum dots, it is also more likely to realize single-electron transistors operating at room temperature, but it is very difficult to test the resolution and efficiency of lithography. ability to align.

Therefore, the purpose of the present invention is to provide a configurable quantum electronic device.

Thus, the configurable quantum electronic device of the present invention includes a semiconductor substrate and at least one quantum unit.

The at least one quantum unit includes two conductive ridges, a quantum dot, an isolation layer, and an electrode group. The conductive ridges are arranged on the semiconductor substrate at an angle to each other to define an included angle area. The quantum dots are arranged on the semiconductor substrate and located in the included angle region. The isolation layer is located in the angle region and surrounds the quantum dot. The electrode set is positioned between the conductive ridges in alignment with the quantum dots.

The effect of the present invention is that the included angle region is defined by arranging the conductive ridges, so that the quantum dots can be easily arranged on the semiconductor substrate and located at the included angle position. The diameter and uniformity of each quantum dot can be highly controlled. In addition, the self-organized isolation layer and the quantum dots can be tightly coupled to each other, and the self-aligned electrode group can be used to inject or manipulate charges. Appropriate bias voltage can be applied according to the needs of practical applications, providing a variety of new quantum dot device configurations, with high reconfigurability.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are designated by the same reference numerals.

Referring to FIG. 1 and FIG. 2 , an embodiment of the configurable quantum electronic device of the present invention includes a semiconductor substrate 2 and a plurality of quantum units 3 arranged on the semiconductor substrate 2 in an array; wherein each of the quantum units 3 includes two The conductive ridge 31 , a quantum dot 32 , an isolation layer 33 , and an electrode group 34 . The semiconductor substrate 2 is a silicon-on-insulator (SOI) substrate having a single crystal silicon (c-Si) layer.

Specifically, in this embodiment, the quantum units 3 are arranged in an array around an axis L. Preferably, one of the conductive ridges 31 of the quantum units 3 is connected to each other on the semiconductor substrate 2 The array is arranged in a circle, and the conductive ridges 31 connected to each other are in the form of fan-shaped ridges. It should be noted that this embodiment only takes the array arrangement in a circle as an example for illustration, but it is not limited to this, as long as the quantum units 3 are arranged in an array, and the number of the quantum units 3 is not particularly The limitation may be only one. In this embodiment, eight quantum units 3 are used as an example for description.

In detail, in each of the quantum units 3, the conductive ridges 31 are disposed on the semiconductor substrate 2 at an angle to each other, and the conductive ridges 31 respectively include two facing each other and jointly define a fan-shaped one. The sidewalls 311 of the corner region 310, in this embodiment, each of the conductive ridges 31 is formed of silicon nitride (Si ₃ N ₄ ).

The quantum dots 32 are disposed on the semiconductor substrate 2 and located in the corner region 310 , and the isolation layer 33 is located in the corner region 310 to surround the quantum dots 32 . It should be noted that the placement position of the quantum dots 32 Or the size can be adjusted, preferably, in this embodiment, the quantum dots 32 are disposed adjacent to the included angle of the included angle region 310, and the quantum dots 32 are circular and its diameter can be between 5nm~20nm , and the distance between the adjacent quantum dots 32 can be controlled to be about 12 nm.

Since the material for forming the quantum dots 32 in this embodiment is made of silicon-germanium alloy and is formed by high-temperature thermal oxidation, after the silicon-germanium alloy is thermally oxidized at high temperature, the silicon of the silicon-germanium alloy will be oxidized in multiple directions to form silicon dioxide ( SiO ₂ ), and germanium (Ge) will be precipitated and pushed into the core and concentrated to form the quantum dots 32 . At this time, the silicon dioxide (SiO ₂ ) surrounding the germanium quantum dots 32 is the isolation layer 33 . In this embodiment, the thickness of the isolation layer 33 ranges from 15 nm to 20 nm. It should be noted that, the materials selected to form the quantum dots 32 and the isolation layer 33 are not limited to the aforementioned silicon-germanium alloy, as long as an alloy with selective oxidation can be found.

The electrode group 34 is aligned with the quantum dots 32 and disposed between the conductive ridges 31 for electrical adjustment of the quantum dots 32 to tune/detuning the quantum dots Charge exchange interactions between 32. Preferably, in this embodiment, the electrode group 34 includes a plunger gate 341 disposed on the semiconductor substrate 2 and located between the conductive ridges 31 , and two respectively disposed on the sidewalls 311 . The upper sidewall gates 342, and the material for forming the plunger gates 341 and the sidewall gates 342 is polysilicon (poly-Si).

It should be noted that, FIGS. 1 and 2 of this embodiment show that each of the quantum units 3 has the plunger gate 341 and the sidewall gates 342 for convenience of description, but the actual application may be selected according to the situation. Only the plunger gate 341 is provided in some of the quantum units 3, and the related structure will be described later.

By first setting the conductive ridges 31 arranged in an array on the semiconductor substrates 2 and defining the included angle regions 310 , the subsequent quantum dots 32 can be ensured to be formed between the conductive ridges 31 . At the included angle between them, the plunger gates 341 and the sidewall gates 342 can be accurately aligned with the corresponding quantum dots 32 .

Referring to FIG. 3, FIG. 3 shows an energy dispersive X-ray spectrum (EDS) composition map of this embodiment, and it can be seen from FIG. 3 that the quantum dots 32 are respectively arranged in the two between the conductive ridges 31 and have the isolation layer 33 composed of silicon dioxide (SiO ₂ ), and the electrode groups 34 disposed between the conductive ridges 31 and aligned with the quantum dots 32 respectively, and It can be known that the spacing between the quantum dots 32 is between 30 nm and 50 nm, and the spacing is mainly determined by the width and thickness of the conductive ridges 31 ; wherein, silicon (Si) is shown in blue in FIG. 3( a ) , while germanium (Ge) is shown in green, nitrogen (N) in Fig. 3(b) is shown in red, and oxygen (O) in Fig. 3(c) is shown in white.

Referring to FIG. 4, FIG. 4 shows that two adjacent quantum units 3 are selected from the implementation of the configurable quantum electronic device of the present invention, or only two adjacent quantum units 3 are arranged on the semiconductor substrate 2 Unit 3. FIG. 4 shows that the quantum units 3 are arranged adjacent to each other, so that one of the conductive ridges 31 in the quantum units 3 is connected to each other, but the difference from the aforementioned quantum unit 3 is that FIG. 4 only includes two arranged on the On the semiconductor substrate 2, the plunger gates 341 are respectively located between the conductive ridges 31, thereby forming double quantum dots (DQDs).

Further, in this double quantum dot device, the quantum dots 32 are mainly used as qubits, and the conductive ridges 31 of this structure can be directly used as electrodes without the need to set the sidewalls Gate 342. Further, when the conductive ridges 31 are directly used as electrodes, the interaction between the adjacent quantum dots 32 can be adjusted, that is, the conductive ridges 31 are directly biased or reverse biased. When pressed, the adjacent quantum dots 32 can directly interact with each other or isolate the quantum dots 32 from each other.

However, it should be noted that the configurable quantum electronic element of the present invention can also be used as a single quantum bit (qubit), that is, only a single quantum unit 3 is arranged on the semiconductor substrate 2, and the quantum unit 2 is also set on the semiconductor substrate 2. There is only the plunger gate 341 between the conductive ridges 31, and the conductive ridges 31 are directly used as electrodes.

Referring to FIG. 5 , it is shown that one of the quantum units 3 is selected from the implementation of the configurable quantum electronic device of the present invention, or only a single quantum unit 3 is provided on the semiconductor substrate 2 . Similar to the structure of the quantum unit 3 described above, the electrode group 34 includes the plunger gate 341 and the sidewall gates 342 to form a quantum dot single-electron transistor (QD-SET). The plug gate 341 is used as the electrode of the gate G of the quantum dot single-electron transistor, and the sidewall gates 342 are used as the electrodes of the source S and the drain D, respectively.

Referring to FIG. 6, FIG. 6 shows the selection of two adjacent quantum units 3 from the implementation of the configurable quantum electronic device of the present invention, the structure of which is substantially the same as that of FIG. 5, but also has the plunger gates The poles 341 and the sidewall gates 342 form a logic circuit of complementary quantum dots through two adjacent two quantum units 3 .

Referring to FIG. 7, FIG. 7 is the integration of the quantum units 3 in the array of FIG. 1, and the plunger gates 341 and the sidewall gates 342 are correspondingly arranged according to different applications, so as to connect the qubits and single electrons The transistors are integrated with each other. Figure 7 illustrates the example of six qubits and two single-electron transistors.

In order to clearly illustrate the structure of this embodiment of the configurable quantum electronic device of the present invention, the steps for fabricating this embodiment of the configurable quantum electronic device are described below.

Referring to FIG. 8 , on a silicon-on-isulator (SOI) substrate 4 having a single crystal silicon (c-Si) layer, nitride nitride is deposited by low-pressure chemical vapor deposition (LPCVD) The silicon (Si ₃ N ₄ ) layer 41 is combined with electron-beam lithography (EBL) and SF ₆ /C ₄ F ₈ plasma etching to generate patterned sectors on the substrate 4 Ridge 5.

Referring to FIG. 9 and FIG. 10 , then, a silicon nitride (Si ₃ N ₄ ) layer 41 and a polycrystalline silicon germanium (poly-Si _0.85 Ge _0.15 ) layer 6 with different thicknesses are sequentially deposited on the patterned fan-shaped ridge 5 . A double-layer mold is formed to cover the ridges 5 (see FIG. 8 ); then, a direct etch-back is performed by using SF ₆ /C ₄ F ₈ plasma to be symmetrical on the sidewalls corresponding to the ridges 5 Polysilicon germanium islands 61 are created (as shown in FIG. 10 ).

Referring to FIGS. 11 and 12 , the central regions of the fan-shaped ridges 5 are partially covered by the photoresist layer 7 to etch the polysilicon germanium islands 61 to define the lengths of the polysilicon-germanium islands 61 on the sidewalls of the fan-shaped ridges 5 .

Referring to FIG. 13 , after the length of the polycrystalline silicon germanium island 61 is defined in FIG. 12 , thermal oxidation is performed at 850° C. to 900° C. for 25 minutes to 40 minutes in a H ₂ O environment to remove the defined polycrystalline silicon germanium island. 61 is converted into germanium (Ge) quantum dots 32 at the included angles of the adjacent fan-shaped ridges 5 , and at the same time, the isolation layer 33 (SiO ₂ ) surrounding the corresponding quantum dots 32 is formed.

Referring to FIG. 1 and FIG. 14 , finally, a polysilicon (poly-Si) layer 8 is deposited on the device shown in FIG. 13 and selectively etched to form self-aligned polysilicon external electrodes between the fan-shaped ridges 5 . To form a quantum electronic component that can be configured as shown in Figure 1.

It can be seen from the foregoing process that the length of the polysilicon germanium island 61 defined by exposure through the photoresist layer 7 can be used to determine the content and size of the germanium quantum dots 32, and the number and position of the germanium quantum dots 32 can be formed. Determining the configuration through the pre-defined fan-shaped ridges 5 can effectively improve the shortcomings of the existing lithography and etching processes to form quantum dots, which need to test the lithography resolution and alignment ability.

To sum up, by defining the patterned conductive ridges 31 with the included corner regions 310, a plurality of tightly coupled germanium quantum dots 32 can be formed at the corner positions at the same time, so that each germanium quantum dot can be highly controlled The diameter and uniformity of the quantum dots 32 have good diameter control and uniformity, and in the process of forming the quantum dots 32, the self-organized silicon dioxide (SiO ₂ ) isolation layer 33 and the quantum dots 32 can be tightly coupled to each other. In addition, three adjacent self-aligned electrode designs such as plunger gate 341 and sidewall gate 342 are further arranged in quantum unit 3, which can be applied with suitable bias voltage according to the needs of practical applications, providing a variety of new quantum The point element configuration is highly reconfigurable. The self-aligned electrode technology established by it can directly integrate quantum dot qubits and single-electron transistor circuits to improve the accuracy of reading quantum states. achieve the purpose of the present invention.

However, the above are only examples of the present invention, and should not limit the scope of implementation of the present invention. Any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the contents of the patent specification are still included in the scope of the present invention. within the scope of the invention patent.

2: Semiconductor substrate 3: Quantum unit 31: Conductive Ridges 310: Angle area 311: Sidewall 32: Quantum Dots 33: isolation layer 34: Electrode set 341: Plunger gate 342: sidewall gate 4: Substrate 41: Silicon nitride layer 5: Scalloped Ridge 6: Polycrystalline silicon germanium layer 61: Polycrystalline silicon germanium island 7: Photoresist layer 8: Polysilicon layer L: axis

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: FIG. 1 is a schematic perspective view illustrating an embodiment of the configurable quantum electronic device of the present invention; FIG. 2 is a top view Figure 1 is a schematic diagram to illustrate this embodiment of the present invention; Figure 3 is an energy dispersive X-ray spectroscopy (EDS) component map, illustrating; Figure 4 is a schematic circuit diagram illustrating this embodiment of the present invention Wherein two or two quantum units constitute a double quantum dot (double quantum dots, DQDs); Fig. 5 is a circuit schematic diagram, which illustrates that one of the quantum units of this embodiment of the present invention constitutes a quantum dot single electron transistor (quantum dot single electron transistor) transistor, QD-SET); FIG. 6 is a schematic circuit diagram illustrating a logic circuit in which two or two quantum units constitute a complementary quantum dot in this embodiment of the present invention; FIG. 7 is a circuit schematic diagram illustrating the embodiment of the present invention. The qubits and single-electron transistors composed of these quantum units are integrated with each other; FIG. 8 is a schematic diagram illustrating the defining steps of photolithography patterning when the configurable quantum electronic device of this embodiment is formed according to the present invention, so as to A patterned fan-shaped ridge is generated; FIG. 9 is a schematic diagram illustrating the deposition of silicon nitride (Si ₃ N ₄ ) and polycrystalline silicon germanium (poly-Si _0.85 Ge _0.15 ) when the configurable quantum electronic device of this embodiment is formed according to the present invention; FIG. 10 is a schematic diagram illustrating the etch-back process when the configurable quantum electronic device of this embodiment is formed according to the present invention; FIG. 11 is a schematic diagram illustrating the transmission of the photoresist when the configurable quantum electronic device of this embodiment is formed by the present invention. to define the length of the polycrystalline silicon germanium (poly-Si _0.85 Ge _0.15 ) island; FIG. 12 is a schematic diagram illustrating the state of the polycrystalline silicon germanium island after etching when the configurable quantum electronic device of this embodiment is formed by the present invention; FIG. 13 is a A schematic diagram illustrating the formation of the configurable quantum electronic device of this embodiment of the present invention, the thermal oxidation of polysilicon germanium islands to form germanium quantum dots at the included corners; and FIG. 14 is a schematic diagram illustrating the formation of the configurable quantum electronic device of this embodiment of the present invention. In quantum electronic devices, polysilicon is deposited and etched back to form the electrode groups.

2: Semiconductor substrate

3: Quantum unit

310: Angle area

311: Sidewall

32: Quantum Dots

33: isolation layer

34: Electrode set

341: Plunger gate

342: sidewall gate

L: axis

Claims (9)

A configurable quantum electronic component comprising: a semiconductor substrate; and At least one quantum unit, including: Two conductive ridges are arranged on the semiconductor substrate at an angle to each other to define an included angle area; a quantum dot, disposed on the semiconductor substrate and located in the angle region; an isolation layer located in the corner region and surrounding the quantum dot; and An electrode set is positioned between the conductive ridges in alignment with the quantum dots. The configurable quantum electronic device of claim 1, wherein the electrode set includes a plunger gate disposed on the semiconductor substrate and between the conductive ridges. The configurable quantum electronic device according to claim 1, wherein the two sidewalls facing each other of the conductive ridges jointly define the angle region, the electrode group comprises two sidewall gates respectively disposed on the sidewalls, and a A plunger gate disposed on the semiconductor substrate and located between the conductive ridges. The configurable quantum electronic component as claimed in claim 1 includes two quantum units, the quantum units are arranged adjacently, so that one of the conductive ridges in the quantum units is connected to each other, and the electrode groups include two arranged on the On the semiconductor substrate, the plunger gates are respectively located between the conductive ridges. The configurable quantum electronic device according to claim 1, comprising a plurality of quantum units, and one of the conductive ridges of the adjacent quantum units is connected to each other and arranged in an array. The configurable quantum electronic device of claim 5, wherein the quantum units are arrayed in a circle around an axis. The configurable quantum electronic device of claim 6, wherein the electrode sets of each quantum unit include a plunger gate disposed on the semiconductor substrate and between the conductive ridges, and Some of the electrode groups further include two sidewall gate electrodes respectively disposed on the two sidewalls of the conductive ridges facing each other. The configurable quantum electronic device according to claim 6, wherein the conductive ridges connected to each other are in the shape of fan-shaped ridges, and each of the included angle regions is in the shape of a fan. The configurable quantum electronic device according to claim 1, wherein the material constituting the quantum dots is selected from germanium, and the material constituting the isolation layer is selected from silicon dioxide.

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