TWI614890B - Inducing localized strain in vertical nanowire transistors - Google Patents

Abstract

A device includes a semiconductor substrate and a vertical nanowire above the semiconductor substrate. The vertical nanowire includes a bottom source / drain region, a channel region above the bottom source / drain region, and a top source / drain region above the channel region. A top interlayer dielectric (ILD) surrounds the top source / drain region. The device further includes a bottom interlayer dielectric surrounding the bottom source / drain region, a gate electrode surrounding the channel region, and a strain applying layer, the strain applying layer having the top interlayer dielectric, The bottom interlayer dielectric and vertical portions on opposite sides of the gate electrode, and contact the top interlayer dielectric, the bottom interlayer dielectric, and opposite sidewalls of the gate electrode.

Description

Local strain induced in vertical nanowire transistors

The present invention relates to the technology of the semiconductor field, and in particular to the technology of vertical transistors in the field of semiconductors.

Vertical transistors have recently been studied. In the vertical transistor, a vertical pillar, which may be a vertical nanowire formed of a semiconductor material, is formed on a substrate, which may be a monolithic semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. The gate dielectric and the gate electrode are formed to surround the nanowire, wherein the enclosed portion of the nanowire forms a corresponding vertical transistor channel. A source and a drain are formed, one of which is under the channel and the other is over the channel. The vertical transistor has a fully enclosed gate structure because the gate may completely surround the channel. With the all-enclosed gate structure, the driving current of the vertical transistor is high, and the short channel effect is minimized.

An embodiment of the present disclosure provides a device including: a semiconductor substrate; a vertical nano-wire above the semiconductor substrate, the vertical nano-wire including: a bottom source / drain region; above the bottom source / drain region A channel region; and a top source / drain region above the channel region; a top interlayer dielectric (ILD) surrounding the top source / drain region; a bottom interlayer dielectric surrounding the bottom source / Drain region; a gate electrode surrounding the channel region; and a strain applying layer including the top interlayer dielectric, the bottom interlayer dielectric, and the gate electrode And a vertical portion on the opposite side of and contact the top interlayer dielectric, the bottom interlayer dielectric, and the opposite sidewall of the gate electrode.

In an embodiment of the present disclosure, the strain applying layer forms a complete ring surrounding the top interlayer dielectric, the bottom interlayer dielectric, and the gate electrode. The device further includes a plurality of vertical nanowires, the plurality of vertical nanowires including the vertical nanowire, wherein the complete ring surrounds the plurality of vertical nanowires. At least one of the top interlayer dielectric, the bottom interlayer dielectric, and the gate electrode extends in all lateral directions to contact the strain applying layer. The gate electrode has a Young's modulus that is lower than the Young's modulus of the top interlayer dielectric and the bottom interlayer dielectric and the vertical nanowire. The device further includes an additional dielectric layer between the Young's modulus at the bottom and the gate electrode, wherein the additional dielectric layer has a Young's modulus that is lower than the Young's modulus at the top , Young's modulus of the bottom, Young's modulus of the vertical nanowire and the gate electrode. The device further includes an additional dielectric layer between the Young's modulus of the top and the gate electrode, wherein the additional dielectric layer has a Young's modulus that is lower than the Young's modulus of the top , Young's modulus of the bottom, Young's modulus of the vertical nanowire and the gate electrode. In addition, the device further includes a top hard layer above the Young's modulus of the top and surrounding the top source / drain region, wherein the vertical portion of the strain application layer is further in contact with the top hard layer. Opposite sidewall contact.

Another embodiment of the present disclosure provides a device including: a semiconductor substrate; a plurality of vertical nanowires above the semiconductor substrate, wherein each of the plurality of vertical nanowires includes: a bottom source / drain region A channel region above the bottom source / drain region; and a top source / drain region above the channel region; a top interlayer dielectric surrounding the top of each of the plurality of vertical nanowires A source / drain region; a bottom interlayer dielectric surrounding the bottom source / drain region of each of the plurality of vertical nanowires; a gate electrode surrounding each of the plurality of vertical nanowires One of the channel region; and a strain-applying layer that surrounds the top interlayer dielectric, the bottom interlayer dielectric, and a sidewall of the gate electrode and is in contact with the top interlayer dielectric, the bottom interlayer dielectric, and the The sidewalls of the gate electrode are in physical contact.

Yet another embodiment of the present disclosure provides a device including: a semiconductor substrate; a vertical semiconductor nanowire above the semiconductor substrate; a stack of four edge-containing layers, wherein the layer stack surrounds the vertical semiconductor nanowire and includes : A bottom interlayer dielectric above the semiconductor substrate; a gate electrode above the bottom interlayer dielectric; and a top interlayer dielectric above the gate electrode, wherein the bottom interlayer dielectric and the gate electrode And the top interlayer dielectric is connected; and a strain applying layer extending from a first layer on the bottom of the vertical semiconductor nanowire to a second layer on the top surface of the vertical semiconductor nanowire, wherein the strain is applied The layer has a height and a thickness less than the height, wherein the four edges of the layer stack contact the sidewall of the strain-applying layer.

20‧‧‧ substrate

22‧‧‧Source / Drain Region

22A‧‧‧ bottom source / drain region

22B‧‧‧Embedded

23‧‧‧ passage area

25‧‧‧Epicenter

26‧‧‧Nano wire

Part 26A, 26B, 26C ‧‧‧

28, 60, 64, 160‧‧‧ rigid photoresist

30, 40, 92, 102‧‧‧ dielectric layers

32‧‧‧ Gate dielectric layer

34‧‧‧Gate electrode layer

36‧‧‧ sacrificial oxide

38‧‧‧Low viscosity spacer

42‧‧‧Impermeable layer

44‧‧‧oxide ring

46‧‧‧ tensile strain

48‧‧‧Source / Drain Region

50, 150‧‧‧ Transistors

52, 56‧‧‧ source / drain contact plugs

54‧‧‧Gate contact plug

62‧‧‧ opening

66‧‧‧ spacer

Lines 70, 72, 80, 82, 170, 172‧‧‧

84‧‧‧ strain application layer

86‧‧‧Bottom dielectric layer

88‧‧‧ top dielectric layer

90‧‧‧ hard top

146‧‧‧compressive stress

164‧‧‧Semiconductor cover

166‧‧‧oxide region

D1‧‧‧ Depth

H1‧‧‧ height

T1‧‧‧thickness

W1, W2‧‧‧Horizontal width

The aspects of this disclosure are best understood from the following detailed description and accompanying drawings. Note that according to industry standard implementations, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or reduced.

1A to 1Q are cross-sectional views of an intermediate stage in the manufacture of a vertical NMOS transistor according to some exemplary embodiments; FIGS. 2A to 2G are cross-sectional views of an intermediate stage in the manufacture of a vertical NMOS transistor according to alternative exemplary embodiments 3A to 3G are cross-sectional views of an intermediate stage in the manufacture of a vertical PMOS transistor according to some exemplary embodiments; FIG. 4 illustrates a vertical NMOS structure for simulating stress in an NMOS transistor; FIG. 5 illustrates a vertical NMOS Analog stress in the structure; Figure 6 illustrates a vertical PMOS structure used to simulate stress in a PMOS transistor; Figure 7 illustrates an analog stress in a vertical PMOS structure; Figure 8 illustrates stress in a vertical transistor, the vertical transistor contains Two Germanium channels between silicon regions; Figure 9 illustrates simulated stress in the vertical transistor shown in Figure 8; Figures 10A, 10B, 10C, and 10D illustrate a perspective, top view of a vertical nanowire transistor according to some embodiments And cross-sectional views; FIG. 11 illustrates a cross-sectional view of a vertical nanowire electrical transistor with a soft gate electrode according to some embodiments; FIG. 12 illustrates a vertical nanowire electrical circuit with a soft dielectric layer under the gate electrode according to some embodiments A cross-sectional view of a crystal; FIG. 13 illustrates a cross-sectional view of a vertical nanowire transistor having a soft dielectric layer over a gate electrode according to some embodiments; FIG. 14 illustrates a cross-section of a vertical nanowire transistor according to some embodiments FIG. 15 shows a contact plug; FIG. 15 illustrates a top view of a vertical nanowire transistor according to an alternative embodiment; and FIG. 16 schematically illustrates a number of available shapes of the nanowire 26.

The following disclosure provides many different embodiments or examples for implementing different features of the disclosure. Specific examples of devices and configurations are described below to simplify the disclosure of this disclosure. Of course, these are just examples and are not intended to be limiting. For example, the following description forms a first feature on or above a second feature, and may include an embodiment in which the first and second features are in direct contact, or an embodiment in which other features are formed between the first and second features. Therefore, the first and second features are not in direct contact. In addition, the disclosure may repeat device symbols and / or letters in different examples. This repetition is for simplicity and clarity, rather than describing the relationship between the different embodiments and / or the architecture in question.

Furthermore, this disclosure can use spatially relative terms such as "under", "below", "lower", "above", "higher" and other similar terms to describe diagrams The relationship between one device or feature and another device or feature. The spatial relative terminology is used to include different orientations in use or steps in addition to the orientation of the device as described in the drawings. The device may be repositioned (rotated 90 degrees or in other orientations), and the corresponding description of the space used in this disclosure may be explained accordingly.

FIG. 1A illustrates the initial steps for forming a vertical MOS transistor. A substrate 20 is provided as part of a semiconductor wafer. The substrate 20 may be a semiconductor substrate, for example, a silicon substrate, but other materials such as silicon germanium and silicon carbide may also be used. The substrate 20 may also be a monolithic semiconductor substrate or a silicon-on-insulator substrate. In some embodiments, the substrate 20 is slightly doped with a p-type impurity. The region 22 is formed in the substrate 20, for example, by an implantation step. The region 22 may be one of a source region or a drain region of the resulting vertical MOS transistor, and is therefore referred to as a first source / drain region hereinafter. Throughout the description, when a region is referred to as a "source / drain" region, the region may be a source region or a drain region. The first source / drain region 22 (also referred to as the bottom source / drain region) may be heavily doped with n-type impurities, such as, for example, phosphorus, arsenic, etc., with an impurity concentration between approximately 1 × 10 ¹⁹ / cm3 and about 1x10 ²¹ / cm3.

A nanowire 26 is formed above the substrate 20, wherein the first source / drain region 22 may extend into the nanowire 26. In some embodiments, the nanowire 26 has a horizontal dimension W1 between about 10 nm and about 40 nm. It should be understood, however, that the values recited throughout the specification are merely examples and may be changed to different values. The height H1 of the nanowire 26 may be between about 10 nm and about 45 nm. The hard photoresist 28 is formed over the nanowire 26 and may include silicon nitride, however other materials such as silicon oxide or oxynitride may be used. The formation of the nanowire 26 may include, after implanting a surface portion of the substrate 20 to form the source / drain regions 22, performing epitaxy to make a semiconductor layer (for example, silicon, silicon germanium, III-V semiconductor, or the like) ) Is grown over the substrate 20, a hard photoresist layer is formed over the epitaxial layer, and then the hard photoresist layer and the epitaxial layer are patterned to form the hard photoresist 28 and the nanowire 26 accordingly. The epitaxial layer may have a uniform structure having a uniform material such as silicon or silicon germanium. Alternatively, the epitaxial layer may have a heterogeneous structure including more than one layer. For example, the portion 26C of the nanowire 26 may be formed of germanium or silicon germanide And portions 26A and 26B may be formed of silicon or silicon germanium. In embodiments where sections 26A, 26B, and 26C all include silicon germanide, the percentage of germanium in section 26C is greater than the percentage of germanium in sections 26A and 26B. In the patterning for forming the nanowire 26, a slight over-etching may be performed so that the top portion of the substrate 20 forms a bottom portion of the nanowire 26. The corresponding nanowire 26 therefore contains an epitaxial portion 25 above the first source / drain region 22. The epitaxial portion 25 may be a p-type region, an internal region, or an n-type region, and may be doped in-situ during the epitaxy.

Referring to FIG. 1B, a dielectric layer 30 is formed. In some embodiments, the dielectric layer 30 includes an oxide such as silicon oxide. The top surface of the dielectric layer 30 is higher than the hard photoresist 28. Next, as shown in FIG. 1C, chemical mechanical polishing (CMP) is performed to make the top surface of the dielectric layer 30 flush with the top surface of the hard photoresist 28. In a subsequent step, as shown in FIG. 1D, etch-back is performed on the dielectric layer 30, and the dielectric layer 30 is recessed. In some embodiments, the interface between the top surface of the dielectric layer 30 and the source / drain region 22 and the epitaxial portion 25 is flush or lower than the interface, however, the top surface of the dielectric layer 30 may be Higher than or at the same height as the interface.

FIG. 1E illustrates the formation of a gate dielectric layer 32. In some embodiments, the gate dielectric layer 32 is formed during a conformal deposition process. The gate dielectric layer 32 may include a high-k dielectric material, such as hafnium dioxide, zirconia, or the like. Other oxides and / or nitrides of Hf, Al, La, Lu, Zr, Ti, Ta, Ba, Sr and / or the like may also be used in the gate dielectric layer 32. As shown in FIG. 1F, an etching step is subsequently performed to remove the horizontal portion of the gate dielectric layer 32, while the vertical portion of the gate dielectric layer 32 is left on the sidewall of the nanowire 26. Next, a gate electrode layer 34 is formed over the gate dielectric layer 32, as further shown in FIG. 1F. The gate electrode layer 34 may include Al, Ti, Ta, W, Mo, Ru, Pt, Co, Ni, Pd, Nb, or an alloy thereof. In other embodiments, the gate electrode layer 34 further includes a metal compound, such as TiN, TaC, or TaN.

FIG. 1G illustrates the formation of a sacrificial oxide 36 that is deposited to a level above the top surface of the hard photoresist 28. CMP is then performed so that the top surface of the sacrificial oxide 36 is flush with the top surface of the hard photoresist 28. As shown in Figure 1H, an etch-back step is subsequently performed to The vertical portion of the gate electrode layer 34 and the exposed portion of the gate dielectric layer 32 are removed. The removed portion of the gate dielectric layer 32 is above the horizontal portion of the gate electrode layer 34. The remaining vertical portion of the gate dielectric layer 32 is hereinafter referred to as a gate dielectric 32.

Next, referring to FIG. 1I, the gate electrode 34 is further patterned. The remaining portion of the gate electrode layer 34 is hereinafter referred to as a gate electrode 34. The gate dielectric 32 and the gate electrode 34 form a gate stack of the resulting vertical MOS transistor. In a plan view of the structure in FIG. 1I, the gate dielectric 32 and the gate electrode 34 surround the nanowire 26.

Next, as shown in FIG. 1J, a low-viscosity spacer 38 is formed on the sidewall of the nanowire 26 and above the gate electrode 34. The low-viscosity spacer 38 surrounds and contacts the top portion of the nanowire 26. The material of the low-viscosity spacer 38 is selected such that the low-viscosity spacer 38 is at least softened at a temperature for the subsequent oxidation of the nanowire 26 (eg, between about 400 ° C and about 1,000 ° C). Viscosity, and therefore stress, can be generated more efficiently in the nanowire 26. In some embodiments, the low viscosity spacer 38 includes boron-doped phosphate silicate glass (BPSG), silicon germanium oxide, or the like, which has a melting and softening temperature below that of silicon oxide. In other words, when heated at a gradually increasing temperature, the low-viscosity spacer 38 becomes softer earlier than silicon oxide. According to an exemplary embodiment, the thickness T1 of the low-viscosity spacer 38 may be between about 0.5 nm and about 4 nm.

FIG. 1K illustrates the formation of the dielectric layer 40 and the CMP steps. In some embodiments, the dielectric layer 40 includes silicon oxide (SiO ₂ ), but other dielectric materials may be used. The dielectric layer 40 and the low-viscosity spacer 38 are subsequently etched back, as shown in FIG. 1L, and thus the top surfaces of the dielectric layer 40 and the low-viscosity spacer 38 are recessed. The depth D1 of the resulting dielectric layer 40 and the low-viscosity spacer 38 may have a depth D1 greater than, for example, about 2 nm. The top portion of the nanowire 26 therefore protrudes above the top surface of the dielectric layer 40.

According to some embodiments, the hard photoresist 28 may be removed and the resulting structure is shown in FIG. 1M. In an alternative embodiment, the hard photoresist 28 is removed in a later step, for example, in a step after the step shown in FIG. 10, and before the step shown in FIG. 1P. An impermeable layer 42 is formed on the top surface and the side wall of the protruding nanowire 26. The impermeable layer 42 is formed of a material that is impermeable to oxygen (O ₂ ). The thickness of the impermeable layer 42 is also large enough to prevent the penetration of oxygen, and the thickness may be between about 1 nm and about 5 nm according to an exemplary embodiment. The impermeable layer 42 has the shape of a cover with a top portion and a ring portion below the top portion and connected to the top portion. The annular portion surrounds the low-viscosity spacer 38.

The structure in FIG. 1M may then undergo a local oxidation process during which the structure in FIG. 1M is placed in an oxygen-containing environment and heated. The oxygen-containing environment may include, for example, oxygen (O ₂ ). In local oxidation, the corresponding wafer may be heated to an elevated temperature between about 450 ° C and about 1,000 ° C. Local oxidation can be performed over a period of time between about 1 minute and about 100 minutes. In other embodiments, the oxidation is performed at a low temperature by chemical oxidation using, for example, a chemical oxidizing agent or an oxidizing plasma. During the partial oxidation, the impermeable layer 42 prevents the penetration of oxygen, and therefore the portion of the nanowire 26 protected by the impermeable layer 42 is not oxidized. Due to the local oxidation, oxygen penetrates the top portion of the dielectric layer 40 and thus the middle portion of the nanowire 26 is oxidized to form an oxide ring 44 that surrounds and extends into the nanowire 26. The oxidized intermediate portion approaches the interface between the impermeable layer 42 and the dielectric layer 40. The oxide ring 44 extends beyond the corresponding sidewall of the nanowire 26. The resulting nanowire 26 therefore includes a first portion above the oxide ring 44, a second portion below the oxide ring 44, and a third portion surrounded by the oxide ring 44. The first and second portions of the nanowire 26 may have a similar horizontal width W1, while the third portion has a second horizontal width W2 that is smaller than the horizontal width W1. The oxide ring 44 may contact the lower low-viscosity layer 38 and the lower impermeable layer 42.

Due to local oxidation, the resulting oxide ring 44 has a volume larger than that of the oxidized portion of the nanowire 26. The oxide ring 44 thus expands in volume over the oxidized portion of the nanowire 26, generating a tensile strain 46 in the nanowire 26. During the oxidation, the low-viscosity spacer 38 softens at least slightly, and therefore the nanowire 26 is more likely to have a change in shape and volume, and therefore it is easier to generate tensile strain 46. The low viscosity spacer 38 thus acts as a lubricant for the generation of tensile strain 46. By analogy, the tensile strain 46 can be as high as about 2GPa Ska to about 8G Pascal. The formation of the low-viscosity spacer 38 can be ignored, provided that the strain is expected to be concentrated in the upper part (drain side) of the corresponding transistor.

Next, referring to FIG. 10, the top portion of the impermeable layer 42 (this portion is above the nanowire 26) is removed. If the hard photoresist 28 (FIG. 1L) has not been removed, it can also be removed at this stage. The side wall portion of the impermeable layer 42 surrounding the top portion of the nanowire 26 may not be removed. FIG. 1P illustrates the doping of the top portion of the nanowire 26 to form a source / drain region 48, where the doping step can be achieved by implanting an n-type impurity. Throughout the description, the source / drain region 48 is also referred to as the top source / drain region. The source / drain region 48 may be heavily doped to an impurity concentration between about 1 × 10 ¹⁹ / cm 3 and about 1 × 10 ²¹ / cm 3. At least a portion of the nanowire 26 surrounded by the gate electrode 34 is not doped in this step, and the portion forms a channel of the resulting vertical MOS transistor 50. Alternatively, the doping of the top portion of the wire may be performed before the growth of the strain generating oxide.

FIG. 1Q illustrates the formation of the gate contact plug 54 and the source / drain contact plugs 52 and 56. The gate contact plug 54 may include a metal including W, Ti, Ni, Co, or a silicide thereof, including TiSi2, NiSi2, WSi2, CoSi2, or the like. The gate contact plug 54 is electrically coupled to the gate electrode 34. The source contact plug 52 and the drain contact plug 56 are electrically coupled to the source region 48 and the drain region 22, respectively. Thus, a MOS transistor 50 is formed. The MOS transistor 50 is an NMOS transistor, and thus the tensile strain 46 (FIG. 1N) helps improve its drive current ions.

2A to 2G illustrate cross-sectional views at an intermediate stage in the formation of an NMOS transistor according to an alternative embodiment. Unless otherwise specified, the materials and formation methods of the devices in these embodiments are substantially the same as similar devices, which are denoted by similar reference numerals as in the embodiments shown in FIGS. 1A to 1Q. Details on the formation process and materials of the components shown in FIGS. 2A to 2G can therefore be found in the discussion of the embodiment shown in FIGS. 1A to 1Q.

The initial steps of these embodiments are substantially the same as those shown in FIGS. 1A to 1I. Next, referring to FIG. 2A, a low-viscosity spacer 38 is formed on a side wall of the nanowire 26 and surrounds the nanowire 26. The low viscosity spacer 38 may include, for example, BPSG or silicon germanium oxide. Return It becomes an impermeable layer 42, which can be formed, for example, from silicon nitride. In these embodiments, the impermeable layer 42 forms a ring surrounding the low viscosity spacer 38. Therefore, the impermeable layer 42 is hereinafter referred to as an impermeable ring 42.

Referring to FIG. 2B, a dielectric layer 40 is formed, followed by a CMP step, in which a hard photoresist 28 and an impermeable layer 42 can serve as a CMP stop layer. The dielectric layer 40 is then recessed, as shown in FIG. 2C, followed by a local oxidation step to generate an oxide region 44, as shown in FIG. 2D. Local oxidation is performed by oxidizing the top portion (top ring) of the nanowire 26. The top of the oxide ring 44 is substantially flush with the top surface of the nanowire 26. The oxide ring 44 also extends beyond the corresponding sidewall of the nanowire 26. Also, due to the expansion of the volume of the oxidized portion of the nanowire 26, tensile stress can be generated in the nanowire 26, with the low-viscosity spacer 38 making it easier to generate tensile stress. The formation of the low-viscosity spacer 38 can be ignored, provided that the strain is expected to be concentrated in the upper part (drain side) of the corresponding transistor.

FIG. 2E illustrates the supplementation of the dielectric layer 40. Next, as shown in FIG. 2F, implantation is performed to form a source / drain region 48. The source / drain region 48 may be heavily doped to an n-type impurity concentration between about 1 × 10 ¹⁹ / cm 3 and about 1 × 10 ²¹ / cm 3. Contact plugs 52, 54, and 56 are then formed to complete the formation of the vertical MOS transistor 50, as shown in FIG. 2G. Alternatively, the doping of the top portion of the transistor may be achieved before the growth of the strain-generating oxide.

3A to 3G illustrate cross-sectional views at an intermediate stage in the formation of a vertical PMOS transistor according to an alternative embodiment. Unless otherwise specified, the materials and formation methods of the devices in these embodiments are substantially the same as similar devices, which are denoted by similar reference numerals as in the embodiments shown in FIGS. 1A to 2G. Details on the formation process and materials of the components shown in FIGS. 3A to 3G can therefore be found in the discussion of the embodiment shown in FIGS. 1A to 2G.

The initial steps of these embodiments are similar to those shown in FIGS. 1A to 1I. In these embodiments, the source / drain region 22 is p-type. Next, referring to FIG. 3A, a dielectric layer 40 is formed, followed by etch-back of the dielectric layer 40. After the etch-back, the top portion of the nanowire 26 is higher than the top surface of the dielectric layer 40. A hard photoresist layer 60 is then formed on the hard photoresist 28 and the dielectric layer 40 square. According to some embodiments, the hard photoresist layer 60 may include silicon nitride, but different materials that are difficult for oxygen to penetrate may be used. Next, as shown in FIG. 3B, for example, in the CMP step, the hard photoresist 28 and the portion of the hard photoresist layer 60 overlapping the hard photoresist 28 are removed. The top surface of the nanowire 26 is exposed through the hard photoresist 60. Similar to the embodiment shown in FIGS. 1A to 2G, for vertical PMOS transistors, a low viscosity spacer 38 may be formed to surround the nanowire 26 as schematically illustrated in FIG. 3B.

FIG. 3C illustrates a depression of the nanowire 26 including an etched nanowire 26. The opening 62 is thus formed in the hard photoresist 60. The top surface of the remaining nanowire 26 may be substantially flush with or lower than the bottom surface of the hard photoresist 60. The hard photoresist layer 64 is then formed as a substantially conformal layer over the hard photoresist 60 and the dielectric layer 40 and extends into the opening 62. The hard photoresist layer 64 has a thickness less than half the thickness of the hard photoresist 60 and may be less than about 25% of the thickness of the hard photoresist 60. According to some embodiments, the hard photoresist layer 64 may include silicon nitride, but other materials that are difficult for oxygen to penetrate may also be used.

FIG. 3E illustrates the removal of the horizontal portion (FIG. 3D) of the hard photoresist layer 64, which can be achieved, for example, by an anisotropic etching step. The remainder of the hard photoresist layer 64 in the opening 62 forms a spacer 66, which is a ring on the side wall of the hard photoresist 60. However, the spacer ring 66 and the hard photoresist 60 may be formed of the same material or different materials. Because they are formed in different processes, there may be an identifiable interface between the spacer ring 66 and the hard photoresist 60, whether or not they are formed of the same material. A portion of the nanowire 26 is exposed through the center region of the spacer ring 66.

Next, as shown in FIG. 3F, local oxidation is performed to oxidize the top portion of the nanowire 26. In some embodiments, the process conditions are selected such that all top layers of the nanowire 26 are oxidized, and thus the edge portion of the resulting oxide region 44 extends beyond the corresponding sidewall of the nanowire 26 and directly on the hard photoresist 60 extends below. The edge portion of the oxide region 44, which is overlapped by the hard photoresist 60, may also have a ring shape. Due to the expansion of the volume of the oxidized portion of the nanowire 26 and further due to the fact that the hard photoresist 60 suppresses the expansion of the volume, a compressive stress 146 is generated in the nanowire 26. After local oxidation, for example contact plugs are formed The remaining components such as 52, 54, and 56 complete the formation of the PMOS transistor 150, as shown in FIG. 3G. In the resulting PMOS transistor 150, the remainder of the oxide region 44 may also form a ring, where the source / drain contact plug 52 extends through the oxide ring 44 to be electrically coupled to the source / drain region 48. .

FIG. 4 illustrates a structure for simulating tensile stress generated in the NMOS transistor 50 (FIGS. 1Q and 2G). In the analog structure, the semiconductor cover 164 is positioned above and connected to the nanowire 26. Oxidation of an outer portion of the semiconductor cover 164 generates an oxide region 166. A portion of the oxide region 166 extends below an edge portion of the semiconductor cover 164 and overlaps by an edge portion of the semiconductor cover 164. The formation of the oxide region 166 causes the volume of the oxidized portion of the semiconductor cover 164 to expand, and thus a tensile stress is generated in the nanowire 26. The simulation results of the stress in FIG. 5 are shown as lines 70, where the tensile stress in the nanowire 26 is illustrated as a function of the distance D1 (FIG. 4), where the distance D1 is measured from the bottom of the semiconductor cover 164. The result indicating the tensile stress can be as high as 8G Pascal, and the stress can still be higher when the distance D1 is less than about 0.02 μm. This means that high tensile stress can be formed in the channel of the vertical NMOS transistor, provided that the distance of the channel from the bottom of the semiconductor cover 164 is less than about 0.02 μm. The wire 70 is simulated by a low viscosity layer 38 (FIG. 6) surrounding the nanowire 26. If the low-viscosity layer 38 is replaced by hard silicon oxide, the corresponding simulation results are shown as lines 72. Compared with the line 70, the line 72 decreases faster than the line 70 as the distance D1 increases. This means that it is more difficult to generate high tensile stress in the channel if the low viscosity layer 38 is not formed, unless the channel is formed very close to the bottom of the semiconductor cover 164.

FIG. 6 illustrates a structure for simulating a compressive stress generated in the vertical PMOS transistor 150 (FIG. 3G). In the analog structure, the semiconductor cover 164 is positioned above and connected to the nanowire 26. Oxidation of the semiconductor cover 164 generates an oxide region 166. The hard photoresist 160 is formed to suppress the volume expansion caused by the formation of the oxide region 166, and thus a compressive stress is generated in the nanowire 26. The stress simulation results are shown as a line 170 in FIG. 7, where the compressive stress in the nanowire 26 is illustrated as a function of the distance D1 (FIG. 6) from the bottom of the semiconductor cover 164. The results indicating the compressive stress can also be as high as -8G Pascal, and the stress can still be higher when the distance D1 is less than about 0.02 μm. This means that high tensile stress can be formed in vertical PMOS transistors It is assumed that the distance between the channel and the bottom of the semiconductor cover 164 is less than about 0.02 μm. In addition, the wire 170 is simulated by a low viscosity layer 38 (FIG. 6) surrounding the nanowire 26. If the low-viscosity layer 38 is replaced by a quality silicon oxide, the corresponding result is shown as line 172. Compared with the line 170, the line 172 drops faster than the line 170 as the distance D1 increases. This means that it is more difficult to generate high compressive stress in the channel if the low viscosity layer 38 is not formed, unless the channel is formed very close to the bottom of the semiconductor cover 164.

According to some embodiments, the generated stress may be concentrated in the channel region by using a semiconductor material having a low Young's modulus to form the channel region. For example, as shown in FIGS. 1Q, 2G, and 3G, the channel region may include a portion 26C formed substantially of pure germanium or silicon germanium. The overlying portion 26A and the underlying portion 26B of the nanowire 26 may be formed of silicon not including germanium therein, or may be formed of silicon germanium, where the concentration of germanium is less than the concentration of germanium in portion 26C.

FIG. 8 illustrates a structure for simulating the concentration of compressive stress, in which the nanowire portions 26A and 26B are silicon nanowire portions, and the portion 26C is a germanium nanowire portion. The simulated stress is shown in FIG. 9. It is shown by line 80 that the stress in portion 26C is significantly greater than that in adjacent portions 26A and 26B. For comparison, if portions 26A, 26B, and 26C are all formed of silicon, the simulated stress will be shown as line 82, which shows that the compressive stress in portion 26C is not greater than the compressive stress in portions 26A and 26B.

10A, 10B, 10C, and 10D illustrate a perspective view, a top view, and a cross-sectional view of a vertical nanowire wire transistor according to some exemplary embodiments. Unless otherwise specified, the materials and formation methods of the devices in these embodiments are substantially the same as similar devices, which are denoted by similar reference numerals as in the embodiments shown in FIGS. 1A to 1Q. Details on the formation process and materials of the components shown in FIGS. 10A to 15 can therefore be found in the discussion of the embodiment shown in FIGS. 1A to 1Q.

FIG. 10A illustrates a perspective view of a vertical nanowire wire transistor 50 according to some embodiments of the present disclosure. A plurality of nanowires 26 are formed close to each other and form a nanowire group. according to In some embodiments of the present disclosure, the nanowires 26 are arranged in an array including one or more rows and one or more columns. For example, the number of rows and the number of columns may be in a range between 1 and about 5. A plurality of nanowires 26 may also be arranged in a pattern other than the array. For example, a plurality of nanowires 26 may be arranged in a hexagonal pattern. Some features of the vertical nanowire transistor 50 such as a gate dielectric, a gate electrode, a contact plug, or the like are not shown in FIG. 10A and can be found in a cross-sectional view.

The nanowire 26 forms a plurality of vertical nanowire transistors, each of which is associated with a corresponding gate dielectric 32 and a gate electrode 34 (not shown in FIG. 10A, refer to FIGS. 11 to 14). A vertical nanowire transistor is formed. The source regions (one of the source regions 22 and the drain regions 48 (FIGS. 11 to 14) of the plurality of vertical nanowire transistors are interconnected to form a common source. The drains of the plurality of vertical nanowire transistors The electrode region (the other of the source region 22 and the drain region 48 (Figures 11 to 14) is interconnected to form a common drain. Multiple vertical nanowire transistors also share a common gate electrode 34 (Figures 11 to 14 Therefore, multiple vertical nanowire transistors are combined to act as a single vertical nanowire transistor, which is also denoted by reference numeral 50.

According to some embodiments, the strain applying layer 84 is formed as a ring surrounding a region of the nanowire transistor 50. The strain applying layer 84 is used to apply a desired strain to a selected area of the vertical nanowire transistor 50. According to some embodiments of the present disclosure, the strain applying layer 84 applies a compressive strain to the nanowire 26. For example, when the corresponding nanowire transistor 50 is a PMOS transistor, a compressive strain may be applied. According to an alternative embodiment of the present disclosure, the strain applying layer 84 applies a tensile strain to the nanowire 26. For example, when the corresponding nanowire transistor 50 is an NMOS transistor, a tensile strain may be applied.

FIG. 10B illustrates a top view of some features of the vertical nanowire transistor 50. In some exemplary embodiments, multiple nanowires 26 are illustrated as forming an array. The top view can be obtained from the level of the top source / drain region 48 (refer to FIG. 10C), where the illustrated portion of the nanowire 26 is the top source / drain portion of the nanowire 26. The top view can also be obtained from the level of the channel region 23, wherein the illustrated portion of the nanowire 26 is the channel region 23 of the nanowire 26. Looking down The diagram can also be obtained from the level of the bottom source / drain region, where the illustrated portion of the nanowire 26 is the bottom source / drain region 22A of the nanowire 26. As shown in FIG. 10B, the strain applying layer 84 may form a complete loop surrounding the nanowire 26. In some exemplary embodiments, the top source / drain region 48 is a drain region, and the bottom source / drain region 22A is a source region. According to an alternative embodiment, the top source / drain region 48 is a source region, and the bottom source / drain region 22A is a drain region.

The strain applying layer 84 may be formed of a dielectric material, which may be an oxide (for example, silicon oxide), a nitride (for example, silicon nitride), an oxynitride (for example, silicon oxynitride), Carbide (for example, silicon carbide) or multiple layers thereof. The formation process is adjusted to generate a desired strain in the strain application layer 84 so that the strain application layer 84 can apply the desired strain to the nanowire 26.

To maximize the strain application effect, the strain application layer 84 is formed close to the nanowire 26. In some exemplary embodiments, the distances D1 and D2 between the strain applying layer 84 and the nearest one of the nanowires 26 are less than about 15 nm. The distances D1 and D2 may also be in a range between about 5 nm and about 10 nm. In addition, the shape of the top view of the strain application layer 84 may be rectangular, circular, elliptical, hexagonal, or the like, wherein the shape of the top view of the strain application layer 84 may depend on the layout selection of the nanowire 26, so that the strain application layer 84 and The distance between the nanowires 26 is minimized, provided that no design rules are violated.

FIG. 10C is a cross-sectional view of the vertical nanowire transistor 50, where the cross-sectional view is obtained from a plane containing BB ′ in FIG. 10B. As shown in FIG. 10C, each of the nanowires 26 includes a bottom portion 22A, which is a portion of the bottom source / drain region 22. Each of the nanowires 26 includes a middle portion 23 forming a channel region of a corresponding vertical nanowire transistor 50. Each of the nanowires 26 further includes a top portion 48 forming a top source / drain region of the vertical nanowire transistor 50. A gate dielectric 32 surrounds the channel region 23.

A bottom dielectric layer 86, also referred to as a bottom interlayer dielectric (ILD), is formed as a nanowire portion 22A surrounding the bottom source / drain region 22. Gate electrode 34 is formed at the bottom ILD 86 Above and surrounds each of the gate dielectrics 32. A top dielectric layer 88, also referred to as a top ILD, is formed to surround the top source / drain region 48. The top source / drain region 48 may also be part of the nanowire 26.

In addition, a hard top layer 90 may be formed over the top ILD 88. According to some embodiments of the present disclosure, the hard top layer 90 is a conductive layer and may be formed of doped silicon (eg, doped polycrystalline silicon or doped silicon epitaxially grown on top of a nanowire) or silicide. The hard top layer 90 may electrically couple the individual top source / drain regions 48 to form a common top source / drain region.

The strain-applying layer 84 surrounds and therefore includes portions on opposite sides of the entire region including the nanowire 26, the bottom ILD 86, the gate dielectric 32, the gate electrode 34, the top ILD 88, and the hard top layer 90 therein. Further, the strain applying layer 84 may be in physical contact with the sidewall of the bottom ILD 86, the gate electrode 34, the top ILD 88, and the hard top layer 90. The bottom source / drain region 22 may include an embedded portion 22B in the semiconductor substrate 20, where the embedded portion 22B electrically couples individual bottom source / drain nanowire portions 22A to form a common bottom source / drain. region. According to some embodiments, the embedded portion 22B may extend laterally beyond the outer edge of the strain applying layer 84. In an alternative embodiment, the embedded portion 22B is confined in a region immediately below the region surrounded by the strain applying layer 84.

According to some embodiments of the present disclosure, the strain application layer 84 extends to the semiconductor substrate 20 and may contact the embedded source / drain region 22B, which is part of the semiconductor substrate 20 in some embodiments. The strain applying layer 84 may or may not include some horizontal portions (not shown) connected to the bottom end of the illustrated vertical strain applying layer 84 and extending outward. The strain applying layer 84 may be formed as a conformal layer in which its height H1 is significantly larger than, for example, five times or more its thickness T1.

FIG. 10D is a cross-sectional view of the vertical nanowire transistor 50, where the cross-sectional view is obtained from a plane containing AA ′ in FIG. 10B. This cross-sectional view is similar to the cross-sectional view shown in FIG. 10C, except that more nanowires 26 are illustrated. In addition, FIG. 10D illustrates that the embedded portion 22B can extend sufficiently far from the outer edge of the strain applying layer 84 in one direction (for example, toward the left side) The embedded portion 22B is made available for connection to a source / drain contact plug (as shown in FIG. 14).

FIGS. 11, 12, and 13 illustrate cross-sectional views of a vertical nanowire transistor 50 in which strain is concentrated on different portions of the nanowire 26 according to various exemplary embodiments. In the following discussion, compressive strain is used as an example to illustrate the concept of the present disclosure. The corresponding vertical nanowire transistor 50 is a PMOS device accordingly. It should be understood that tensile strain may also be applied according to other embodiments, where the strain applied through the strain application layer 84 is a tensile strain. The corresponding vertical nanowire transistor 50 is a corresponding NMOS device.

FIG. 11 schematically illustrates some embodiments in which strain is concentrated in the channel region 23. Referring to FIG. 11, the nanowire 26 including portions 22A, 23 and 48 is formed of a material having a relatively high first Young's modulus. In other words, the nanowire 26 is formed of a relatively hard material. What is achieved is that the modulus of a material can be affected by its size. For example, the overall silicon has a high Young's modulus equal to about 180 GPa. When formed as a nanowire rather than a whole area, the Young's modulus of silicon decreases, sometimes as low as about 80 GPa. Therefore, when selecting an appropriate material to form a nanowire, factors such as size need to be considered in order to obtain a desired modulus.

The gate electrode 34 is selected to have a second Young's modulus. According to some embodiments, the second Young's modulus is less than the first Young's modulus of the nanowire 26. According to an alternative embodiment, the second Young's modulus is equal to or greater than the first Young's modulus of the nanowire 26. The gate electrode 34 is formed of a conductive material. In some exemplary embodiments, the gate electrode 34 is formed of aluminum, which has a Young's modulus equal to about 69 GPa. The top ILD 88 and the bottom ILD 86 are formed of a material having a third Young's modulus greater than the Young's modulus of the gate electrode 34. Therefore, the strain is finally applied to the nanowire 26 by the strain applying layer 84 that applies a strain (compression or stretching). In addition, since the gate electrode 34 is softer than the overlying ILD 88 and the underlying ILD 86, strain is concentrated in the channel region 23. The arrows in Figure 11 schematically illustrate how the strain is concentrated.

In addition, in order to maximize the strain in the channel region 23, the first Young's modulus of the nanowire 26 may also be greater than the Young's modulus of both the top ILD 88 and the bottom ILD 86 and the Young's modulus of the gate electrode 34. So that the strain is concentrated on the nanowire 26 instead of the top ILD 88 and the bottom ILD 86 and gate electrode 34.

According to some exemplary embodiments, the Young's modulus of the gate electrode 34 is smaller than the Young's modulus of both the top ILD 88 and the bottom ILD 86 by about 5 GPa or more, so that strain can be effectively concentrated in the channel region 23. In addition, the Young's modulus of the gate electrode 34 may be less than about 80% or less than about 50% of the Young's modulus of both the top ILD 88 and the bottom ILD 86. The Young's modulus of the gate electrode 34 may be between about 20% and about 80% of the Young's modulus of both the top ILD 88 and the bottom ILD 86. It should be understood that the Young's modulus of a material is affected by various factors, such as the material itself, porosity, formation conditions (eg, temperature), size, and so on. Therefore, the same material may not have the same Young's modulus.

As shown in FIG. 11, when the vertical nanowire transistor 50 is a PMOS transistor, the strain applying layer 84 is configured to apply a compressive strain to a region surrounded by the strain applying layer 84. The compressive strain is concentrated in the channel region 23, and thus the hole mobility in the channel region 23 is improved. In an alternative embodiment, when the vertical nanowire transistor 50 is an NMOS transistor, the strain applying layer 84 is configured to apply a tensile strain to a region surrounded by the strain applying layer 84. The tensile strain is also concentrated in the channel region 23, and thus the electron mobility in the channel region 23 is improved.

FIG. 11 also schematically illustrates the results of a simulation that reveals the strain distribution in the nanowire 26, with the simulation results shown on the right side of the cross-sectional view. The X-axis represents the magnitude of the strain, and the Y-axis represents the vertical position in the nanowire 26. The analog result indicates that the strain at the position corresponding to the channel region has a larger magnitude than that corresponding to the source region 22A and the drain region 48, indicating that the strain is concentrated in the channel region 23, where the source portion 22A of the nanowire and the The drain portion 48 has a much smaller strain.

FIG. 12 schematically illustrates some embodiments in which strain is concentrated to a bottom source / drain junction region, which is a region near the interface between the channel region 23 and the corresponding underlying source / drain portion 22A. In these embodiments, a dielectric layer 92 is formed between the bottom ILD 86 and the gate electrode 34. The dielectric layer 92 is formed of a relatively soft material that is softer than the ILDs 86 and 88 and the gate electrode 34. In other words, the Young's modulus of the dielectric layer 92 is less than the bottom ILD 86, the top Young's modulus of the ILD 88 and the gate electrode 34. The Young's modulus of the dielectric layer 92 may be smaller than the Young's modulus of the hard top layer 90. In some exemplary embodiments, the Young's modulus of the dielectric layer 92 may be less than 80% of the Young's modulus of the bottom ILD 86, the top ILD 88, and the gate electrode 34 or between about the Young's modulus Between 20% and about 80% to effectively focus strain.

The top surface of the dielectric layer 92 may contact the bottom surface of the gate electrode 34 and may be substantially flush with the interface between the channel region 23 and the corresponding underlying source / drain portion 22A. The dielectric layer 92 may serve as a gate spacer for the corresponding vertical nanowire transistor 50. The dielectric layer 92 may extend in all lateral directions to contact the strain applying layer 84. Candidate materials for the dielectric layer 92 include (and are not limited to) boron-doped phosphate silicate glass (BPSG), phosphate silicate glass (PSG), and borosilicate glass (BSG). The thickness of the dielectric layer 92 may be greater than about 5 nm, or greater than about 10 nm.

Since the dielectric layer 92 is softer than the bottom ILD 86, the top ILD 88, the gate electrode 34 and the hard top layer 90, the strain is concentrated in the bottom bonding region, which is close to the channel region 23 and the bottom source / drain The portion of the nanowire 26 bonded between the regions 22A. The arrows in Figure 12 schematically illustrate how the strain is concentrated. FIG. 12 also schematically illustrates the results of a simulation (on the right side of the cross-sectional view) that reveals the strain distribution in the nanowire 26. The X-axis represents the magnitude of the strain, and the Y-axis represents the vertical position in the nanowire 26. An analog result indicates that the strain is concentrated in the bottom junction area, with the rest of the nanowire 26 having much less strain.

Advantageously, the concentration of strain to the bottom junction region results in an improvement in the performance of the vertical nanowire transistor 50. For example, if the bottom source / drain region 22A is a source region, the carrier injection speed will increase. On the other hand, if the bottom source / drain region 22A is a drain region, the peak carrier velocity will increase.

FIG. 13 schematically illustrates some embodiments in which strain is concentrated in a top source / drain junction region, which is a region near the interface between the channel region 23 and the corresponding overlying source / drain region 48. These embodiments are similar to the embodiment shown in FIG. 12, except that a soft dielectric layer 92 is interposed between the top ILD 88 and the gate electrode 34.

In these embodiments, the bottom surface of the dielectric layer 92 may contact the top surface of the gate electrode 34. The dielectric layer 92 may also function as a gate spacer. Since the dielectric layer 92 is softer than the bottom ILD 86, the top ILD 88, the gate electrode 34, and the hard top layer 90, strain is concentrated on the top junction area of the nanowire 26. The arrows in FIG. 13 schematically illustrate how the strain is concentrated. FIG. 13 also schematically illustrates the results of a simulation revealing strain distribution in the nanowire 26. The X-axis represents the magnitude of the strain, and the Y-axis represents the vertical position in the nanowire 26. An analog result indicates that the strain is concentrated in the top junction area, with the rest of the nanowire 26 having much less strain.

Advantageously, the concentration of strain to the top junction region results in an improvement in the performance of the vertical nanowire transistor 50. For example, if the top source / drain region 48 is a source region, the carrier injection speed will increase. On the other hand, if the top source / drain region 48 is a drain region, the peak carrier velocity will increase.

FIG. 14 illustrates a cross-sectional view of a vertical nanowire transistor 50, in which the contact plugs 56, 52, and 54 are illustrated. The cross-sectional view is obtained from a plane containing a line AA ′ in FIG. 10B. The ILD 94 is formed to surround the strain applying layer 84 and may extend to a level above the top surface of the top source / drain region 48 and the hard top layer 90. The ILD 94 may be formed of a homogeneous dielectric material or may have a composite structure including multiple layers. The source / drain contact plug 56 penetrates the ILD 94 to be electrically coupled to the bottom source / drain region 22B. The source / drain contact plug 54 penetrates the ILD 94 to be electrically coupled to the conductive top hard layer 90, and thus is electrically coupled to the top source / drain region 48. The gate contact plug 54 penetrates the ILD 94 to be electrically coupled to the gate electrode 34. The dielectric layer 102 is formed to electrically isolate the gate contact plug 54 and the hard top layer 90.

FIG. 15 illustrates a top view of a vertical nanowire transistor 50 according to another alternative embodiment. These embodiments are similar to those shown in Figures 11, 12, and 13, except that the strain-applying layer includes layers on opposite sides of layers 34, 86, 88, and 90 in the Y direction but not in the X direction 34, 86, 88, and 90 on opposite sides. Therefore, as shown in FIG. 15, the strain applying layer 84 does not form a ring. When the cross-sectional view is obtained from a plane containing the line BB ′ in FIG. 15, the cross-sectional views of the vertical nanowire transistor 50 according to these embodiments may still be the same as those shown in FIGS. 11, 12, and 13. the same.

Although the term "nanowire" is used to describe vertical semiconductor features, the size of "nanowire 26" can be larger than the typical nanometer range. In addition, the shape of the nanowire 26 may be any suitable shape. FIG. 16 schematically illustrates a number of available shapes for the nanowire 26. For example, the shape of the top view of the nanowire 26 includes a circle, an oval, a rectangle with a rounded corner, a rectangle with a relatively sharp corner, a long strip, a triangle, a hexagon, or the like.

The embodiments shown in FIGS. 10A, 10B, 10C, 10D, and 11 to 15 have some advantageous features. Strain can be applied to multiple nanowires through a common strain applying layer. The manufacturing process is therefore significantly simplified. In addition, it is possible to customize the area of the nanowire where the strain is concentrated.

According to some embodiments of the present disclosure, a device includes a semiconductor substrate and a vertical nanowire above the semiconductor substrate. The vertical nanowire includes a bottom source / drain region, a channel region above the bottom source / drain region, and a top source / drain region above the channel region. The top ILD surrounds the top source / drain region. The device further includes a bottom ILD surrounding a bottom source / drain region, a gate electrode surrounding a channel region, and a strain applying layer having a vertical portion on opposite sides of the top ILD, bottom ILD, and gate electrode And contact opposite sidewalls of the top ILD, the bottom ILD, and the gate electrode.

According to an alternative embodiment of the present disclosure, a device includes a semiconductor substrate and a plurality of vertical nano-wires above the semiconductor substrate. Each of the plurality of vertical nanowires includes a bottom source / drain region, a channel region above the bottom source / drain region, and a top source / drain region above the channel region. The top ILD surrounds the top source / drain region of each of the plurality of vertical nanowires. The bottom ILD surrounds the bottom source / drain region of each of the plurality of vertical nanowires. A gate electrode surrounds a channel region of each of the plurality of vertical nanowires. The strain applying layer surrounds and physically contacts the sidewalls of the top ILD, the bottom ILD, and the gate electrode.

According to other alternative embodiments of the present disclosure, a device includes a semiconductor-based A board, a plurality of vertical nanowires above the semiconductor substrate, and a stack of layers having four edges, wherein the layer stack surrounds the vertical semiconductor nanowires. The layer stack includes a bottom ILD above the semiconductor substrate, a gate electrode above the bottom ILD, and a top ILD above the gate electrode, wherein the bottom ILD, the gate electrode, and the top ILD are connected. The strain applying layer extends from a first layer on the bottom of the nanowire to a second layer on the top surface of the nanowire. The strain application layer has a height and a thickness less than the height. The four edges of the layer stack contact the side walls of the strain applying layer.

The foregoing outlines the features of some embodiments, so that those skilled in the art may better understand the aspects disclosed in this application. Those skilled in the art should understand that the disclosure of this application can be easily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the implementation described in this application. Those familiar with this technology should also understand that this equal structure does not depart from the spirit and scope of the disclosure of this application, and that those skilled in this technology can make various changes, substitutions and substitutions without departing from the spirit and scope of this disclosure. range.

20‧‧‧ substrate

22‧‧‧Source / Drain Region

25‧‧‧Epicenter

26‧‧‧Nano wire

Part 26A, 26B, 26C ‧‧‧

30, 40‧‧‧ dielectric layer

32‧‧‧ Gate dielectric layer

34‧‧‧Gate electrode layer

38‧‧‧Low viscosity spacer

42‧‧‧Impermeable layer

44‧‧‧oxide ring

48‧‧‧Source / Drain Region

50‧‧‧ Transistor

52, 56‧‧‧ source / drain contact plugs

54‧‧‧Gate contact plug

Claims (10)

A semiconductor device includes: a semiconductor substrate; a vertical nanowire above the semiconductor substrate, the vertical nanowire including: a bottom source / drain region; a channel region above the bottom source / drain region; and the Top source / drain region above the channel region; top interlayer dielectric (ILD), which surrounds the top source / drain region; bottom interlayer dielectric, which surrounds the bottom source / drain region; gate An electrode surrounding the channel region; and a strain applying layer including vertical portions on opposite sides of the top interlayer dielectric, the bottom interlayer dielectric, and the gate electrode, and contacting the top interlayer dielectric, The bottom interlayer dielectric and opposite sidewalls of the gate electrode. The device according to claim 1, wherein the strain applying layer forms a complete ring surrounding the top interlayer dielectric, the bottom interlayer dielectric, and the gate electrode. The device according to claim 2, further comprising a plurality of vertical nanowires, the plurality of vertical nanowires including the vertical nanowire, wherein the complete ring surrounds the plurality of vertical nanowires. The device according to claim 1, wherein at least one of the top interlayer dielectric, the bottom interlayer dielectric, and the gate electrode extends in all lateral directions to contact the strain applying layer. The device according to claim 1, wherein the gate electrode has a Young's modulus that is lower than the Young's modulus of the top interlayer dielectric, the bottom interlayer dielectric, and the vertical nanowire. The device according to claim 1, further comprising an additional dielectric layer between the bottom interlayer dielectric and the gate electrode, wherein the additional dielectric layer has a Young's modulus, which is lower than the Young's modulus Young's modulus of the top interlayer dielectric, the bottom interlayer dielectric, the vertical nanowire, and the gate electrode. The device according to claim 1, further comprising an additional dielectric layer between the top interlayer dielectric and the gate electrode, wherein the additional dielectric layer has a Young's modulus, which is lower than the Young's modulus Young's modulus of the top interlayer dielectric, the bottom interlayer dielectric, the vertical nanowire, and the gate electrode. The device according to claim 1, further comprising a top hard layer above the top interlayer dielectric and surrounding the top source / drain region, wherein the vertical portion of the strain application layer further communicates with Opposite sidewalls of the top hard layer are in contact. A semiconductor device includes: a semiconductor substrate; a plurality of vertical nanowires above the semiconductor substrate, wherein each of the plurality of vertical nanowires includes: a bottom source / drain region; and the bottom source / A channel region above the drain region; and a top source / drain region above the channel region; a top interlayer dielectric (ILD) that surrounds the top source / of each of the plurality of vertical nanowires Drain region; bottom interlayer dielectric that surrounds the bottom source / drain region of each of the plurality of vertical nanowires; gate electrode that surrounds each of the plurality of vertical nanowires The channel region; and a strain applying layer that surrounds and physically contacts the top interlayer dielectric, the bottom interlayer dielectric, and a sidewall of the gate electrode. A semiconductor device includes: a semiconductor substrate; a vertical semiconductor nanowire above the semiconductor substrate; a stack of four edge-containing layers, wherein the layer stack surrounds the vertical semiconductor nanowire and includes: a bottom above the semiconductor substrate Interlayer dielectric (ILD); a gate electrode above the bottom interlayer dielectric; and a top interlayer dielectric above the gate electrode, wherein the bottom interlayer dielectric, the gate electrode, and the top interlayer dielectric are Connected; and a strain applying layer extending from a first layer on the bottom of the vertical semiconductor nanowire to a second layer on the top surface of the vertical semiconductor nanowire, wherein the strain applying layer has a height and a height less than the height Thickness, wherein the four edges of the layer stack contact the sidewall of the strain-applying layer.