CN111508988A - Chip packaging structure and packaging method - Google Patents

Chip packaging structure and packaging method Download PDF

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Publication number
CN111508988A
CN111508988A CN202010470133.0A CN202010470133A CN111508988A CN 111508988 A CN111508988 A CN 111508988A CN 202010470133 A CN202010470133 A CN 202010470133A CN 111508988 A CN111508988 A CN 111508988A
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CN
China
Prior art keywords
chip
shielding portion
package structure
back surface
substrate
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Pending
Application number
CN202010470133.0A
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Chinese (zh)
Inventor
吴明轩
杨剑宏
王蔚
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China Wafer Level CSP Co Ltd
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China Wafer Level CSP Co Ltd
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Publication date
Application filed by China Wafer Level CSP Co Ltd filed Critical China Wafer Level CSP Co Ltd
Priority to CN202010470133.0A priority Critical patent/CN111508988A/en
Publication of CN111508988A publication Critical patent/CN111508988A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention discloses a chip packaging structure and a chip packaging method, wherein the chip packaging structure comprises a substrate, a chip and a shielding part, wherein the substrate comprises a first surface and a second surface which are oppositely arranged; the chip is fixed on the second surface and comprises a functional surface and a back surface which are oppositely arranged, and the functional surface faces the second surface; the shielding part at least covers the back surface. The back surface of the chip is covered with the shielding part, and the shielding part can shield infrared light in the environment on the back surface of the chip, so that the infrared light is prevented from influencing the optical imaging process.

Description

Chip packaging structure and packaging method
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip packaging method.
Background
With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.
The main component of the electronic device for realizing the preset function is a chip, along with the continuous progress of the integrated circuit technology, the integration level of the chip is higher and higher, the function of the chip is stronger and stronger, and the size of the chip is smaller and smaller, so that the chip needs to form a packaging structure through packaging so as to be electrically connected with an external circuit board.
In the prior art, because the back surface of the chip is exposed, the pollution of infrared light in the environment to the optical imaging process cannot be shielded, for example, the image of the ball planted on the back surface of the chip appears in the final imaging pattern.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a chip packaging method which can avoid the influence of infrared light on the optical imaging process.
To achieve one of the above objects, an embodiment of the present invention provides a chip package structure, including:
the substrate comprises a first surface and a second surface which are oppositely arranged;
the chip is fixed on the second surface and comprises a functional surface and a back surface which are oppositely arranged, and the functional surface faces the second surface;
a shielding portion covering at least the back surface.
As a further improvement of an embodiment of the present invention, the shielding portion further covers a side edge of the chip and the second surface.
As a further improvement of an embodiment of the present invention, the package structure further includes a ball-planting portion located on the second surface, and the shielding portion exposes the ball-planting portion.
As a further improvement of the embodiment of the present invention, the package structure further includes a package adhesive connecting the side edge of the chip and the second surface, and the shielding portion is located on a side of the package adhesive away from the chip.
In a further improvement of an embodiment of the present invention, the shielding portion is an epoxy resin or ink mixed with carbon black.
As a further improvement of an embodiment of the present invention, the chip is a silicon chip.
As a further improvement of an embodiment of the present invention, the substrate is a transparent substrate.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for packaging a chip, including:
defining a plurality of substrates distributed in an array on the base, wherein cutting channels are arranged between adjacent substrates;
fixing a functional surface of a chip and a second surface of the substrate;
forming a shielding part at least covering the back surface of the chip far away from the functional surface;
and dividing the substrate based on the cutting channels to form a plurality of single-grain packaging structures.
As a further improvement of an embodiment of the present invention, the step of "forming a shielding portion covering at least a back surface of the chip away from the functional surface" specifically includes:
forming a shielding part covering the back surface of the chip, the periphery of the chip and the second surface by a coating process;
forming an opening at the area of the shielding part corresponding to the second surface through an exposure and development process;
and forming a planting ball in the opening.
As a further improvement of the embodiment of the present invention, the step of forming the shielding portion covering the back surface of the chip, the peripheral edge of the chip, and the second surface by a coating process further includes:
and forming packaging glue for connecting the side edge of the chip and the second surface.
Compared with the prior art, the invention has the beneficial effects that: the back surface of the chip is covered with the shielding part, and the shielding part can shield infrared light in the environment on the back surface of the chip, so that the infrared light is prevented from influencing the optical imaging process.
Drawings
FIG. 1 is a schematic diagram of a package structure according to an embodiment of the invention;
FIG. 2 is a diagram of the steps of a packaging method according to an embodiment of the present invention;
fig. 3 to 11 are schematic diagrams illustrating steps of a packaging method according to an embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
In the various drawings of the present invention, some dimensions of structures or portions are exaggerated relative to other structures or portions for convenience of illustration, and thus, are used only to illustrate the basic structure of the subject matter of the present invention.
Referring to fig. 1, a schematic diagram of a chip package structure 100 according to an embodiment of the invention is shown.
The package structure 100 includes a substrate 10, a chip 11, and a shielding portion 13.
The substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other.
The chip 11 is fixed on the second surface 102, the chip 11 includes a functional surface 111 and a back surface 112, which are oppositely disposed, and the functional surface 111 faces the second surface 102.
The shielding portion 13 covers at least the back surface 112.
Here, the shielding portion 13 may be an optical material layer formed by a coating process, and the shielding portion 13 is, for example, epoxy resin mixed with carbon black or ink, but not limited thereto, and the material of the shielding portion 13 may be determined according to actual circumstances, and the shielding portion 13 has a low light transmittance.
It should be noted that "the chip 11 is fixed to the second surface 102" means that the chip 11 is located on one side of the second surface 102 of the substrate 10, and the chip 11 and the second surface 102 may be directly connected or indirectly connected, in other words, one component described in this embodiment is connected, fixed, or located on another component, and means that two components are directly connected or indirectly connected.
The shielding portion 13 covers the back surface 112 of the chip 11 in this embodiment, and the shielding portion 13 can shield infrared light in the environment on the back surface 112 of the chip 11, so as to avoid the infrared light from affecting the optical imaging process.
Here, the chip 11 is a silicon chip 11, and in the prior art, since the back surface of the silicon chip is exposed outside, the pollution of infrared light in the environment to optical imaging cannot be shielded, in the present embodiment, a shielding portion 13 with low light transmittance is formed on the back surface 112 of the silicon chip 11, and the infrared light in the environment reaches the shielding portion 13 and is absorbed or reflected by the shielding portion 13, that is, the infrared light basically does not reach the back surface 112 of the silicon chip 11, and thus, the optical pollution is not caused.
In addition, the shielding portion 13 may also have a certain heat dissipation effect, which may improve the heat dissipation performance of the entire package structure 100.
In the present embodiment, the shielding portion 13 also covers the side edge 113 and the second surface 102 of the chip 11, so that the infrared light in the environment can be further prevented from entering from the side edge 113 of the chip 11 to cause optical pollution.
In the present embodiment, the substrate 10 is a transparent substrate 10, the chip 11 is an image sensing chip, external light directly reaches the functional surface 111 of the chip 11 through the transparent substrate 10, and then the chip 11 transmits the acquired signal to an external circuit board.
The second surface 102 of the transparent substrate 10 is provided with a transparent area 1021 and a first connection area 1022, the functional surface 111 of the chip 11 is provided with a sensing area 111a and a second connection area 111b, the sensing area 111a is disposed corresponding to the transparent area 1021, and the second connection area 111b is connected to the first connection area 1022, so that the chip 11 and the transparent substrate 10 can be fixed.
Here, the second connection region 111b includes the connection terminal 1111b, and the connection terminal 1111b is connected to the first connection region 1022, and at this time, a cavity S with a smaller size is formed between the sensing region 111a and the transparent region 1021, so as to prevent the sensing region 111a from being damaged due to the direct contact between the transparent region 1021 and the sensing region 111a, and further, the sensing effect of the chip 11 is not affected.
The package structure 100 further includes a package adhesive 14 connecting the side edge 113 of the chip 11 and the second surface 102, so as to improve the stability of the chip 11 matching with the transparent substrate 10, and the shielding portion 13 is located on a side of the package adhesive 14 away from the chip 11.
With reference to fig. 1, in the present embodiment, the package structure 100 further includes the solder balls 12 on the second surface 102, and the shielding portion 13 exposes the solder balls 12.
Specifically, the ball-planting 12 includes a first end 121 and a second end 122 disposed opposite to each other, the first end 121 is electrically connected to the first connection region 1022, and the ball-planting 12 is a solder ball.
When the package structure 100 and the external circuit board are assembled with each other, the package structure 100 is electrically connected to the external circuit board by soldering the solder balls 12 to the external circuit board, and since the solder balls 12 and the connection terminals 1111b of the chip 11 are electrically connected to the first connection regions 1022, the solder balls 12 and the connection terminals 1111b are conducted with each other, at this time, the signal obtained by the chip 11 can be transmitted to the external circuit board.
Of course, the ball-planting may also be formed at the back surface 112 of the chip 12.
Here, the first connection region 1022 includes the redistribution layer 1022, that is, the package structure 100 of the present embodiment is a fan-out (fan-out) package structure.
Specifically, the first connection region 1022 includes a protection layer 1023, a redistribution layer 1022 and a solder resist layer 1024 sequentially connected to the second surface 102, the connection terminal 1111b of the chip 11 is electrically connected to the redistribution layer 1022, the first end 121 of the ball-planting 12 is electrically connected to the solder resist layer 1024, and the package adhesive 14 is connected to the redistribution layer 1022.
The thermal expansion coefficient of the protection layer 1023 may be between the transparent substrate 10 and the redistribution layer 1022, but not limited thereto, the protection layer 1023 is disposed to prevent the redistribution layer 1022 and the transparent substrate 10 from separating from each other under stress and pulling, and the cavity S of the embodiment has a small size, so that the package structure 100 has a strong rigidity, and further prevents the redistribution layer 1022 from separating from the transparent substrate 10 under stress.
In addition, the package structure 100 of the present embodiment further includes a metal layer 1025 connected to the passivation layer 1023 and the redistribution layer 1022, and the metal layer 1025 can prevent the package adhesive 14 from entering the sensing region 111a of the chip 11.
In the present embodiment, the shielding portion 13 covers the back surface of the chip 11, the side edge of the package adhesive 14, the solder mask layer 1024 exposed on the second surface 102 side, and the redistribution layer 1022, and a portion of the solder mask layer 1024 is exposed by the shielding portion 13, so that the solder balls 12 are electrically connected to the solder mask layer 1024, that is, the shielding portion 13 exposes the solder balls 12.
The second ends 122 of the solder balls 12 protrude from the shielding portion 13 in a first direction X, which is defined as a direction (i.e. a vertical direction) from the first surface 101 of the substrate 10 toward the second surface 102, so that the package structure 100 can be electrically connected to an external circuit board via the solder balls 12, and the chip 11 is prevented from being damaged during a soldering process.
An embodiment of the present invention further provides a chip packaging method, which includes, with reference to fig. 2 to 11:
s1: referring to fig. 3, a plurality of substrates 10 are defined on a base in an array distribution, and a cutting channel is formed between adjacent substrates 10;
here, the substrate may be a wafer substrate, a plurality of substrates 10 may be pre-divided on the substrate in an array, and the substrate 10 is a transparent substrate.
S3: with reference to fig. 4 to 8, the functional surface 111 of the chip 11 and the second surface 102 of the substrate 10 are fixed;
here, step S3 is preceded by the step of:
with reference to fig. 4 and 5, a passivation layer 1023 and a redistribution layer 1022 are sequentially formed on the second surface 102 of the substrate 10.
Specifically, a protective layer 1023 may be coated on the substrate, and then a redistribution layer 1022 may be formed by electroplating, photolithography, and the like, and then, with reference to fig. 6 and 7, a metal layer 1025 connecting the protective layer 1023 and the redistribution layer 1022, and a solder resist layer 1024 under the redistribution layer 1022 may be formed.
Step S3 specifically includes:
with reference to fig. 8, the second connection region 111b at the functional surface 111 and the first connection region 1022 at the second surface 102 are connected, such that the sensing region 111a at the functional surface 111 corresponds to the transparent region 1021 at the second surface 102;
the encapsulation adhesive 14 connecting the side edge of the chip 11 and the second surface 102 is formed.
Here, the chip 11 is an image sensing chip as an example, but not limited to this, the connection between the chip 11 and the substrate 10 can be realized by a flip-chip method, the first connection region 1022 includes the protective layer 1023, the redistribution layer 1022 and the solder resist layer 1024, the second connection region 111b includes the connection terminal 1111b, the connection terminal 1111b is electrically connected with the redistribution layer 1022 on the second surface 102, and in addition, the package adhesive 14 is connected with the redistribution layer 1022, and the arrangement of the package adhesive 14 can improve the stability of the matching between the chip 11 and the substrate 10.
S5: referring to fig. 9, a shielding portion 13 is formed to cover at least the back surface 112 of the chip 11 away from the functional surface 111.
Step S5 specifically includes:
with reference to fig. 9, a shielding portion 13 is formed by a coating process to cover the back surface 112 of the chip 11, the peripheral edge 113 of the chip 11, and the second surface 102;
here, the shielding portion 13 may be formed by coating on the entire surface of the substrate provided with the chip 11, and the shielding portion 13 substantially covers the back surface of the chip 11, the side edge of the encapsulation adhesive 14, and the solder resist layer 1024 and the rewiring layer 1022 exposed on the second surface 102 side.
Step S5 is followed by the step of:
with reference to fig. 10, an opening 131 is formed at a region of the blocking portion 13 corresponding to the second surface 102 through an exposure and development process;
here, the opening 131 exposes a portion of the solder resist layer 1024.
Referring to fig. 11, the solder balls 12 are formed in the openings 131, i.e., the solder balls 12 are electrically connected to the solder resist layer 1024.
S7: the substrate is divided based on the dicing channels to form a plurality of singulated packaging structures 100.
The back surface 112 and the side edge 113 of the chip 11 of the present embodiment are covered with the shielding portion 13, and the shielding portion 13 can shield infrared light in the environment at the back surface 112 and the side edge 113 of the chip 11, so as to avoid the infrared light from affecting the optical imaging process.
For other descriptions of the packaging method of the present embodiment, reference may be made to the description of the packaging structure, and further description is omitted here.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.

Claims (10)

1. A chip package structure, comprising:
the substrate comprises a first surface and a second surface which are oppositely arranged;
the chip is fixed on the second surface and comprises a functional surface and a back surface which are oppositely arranged, and the functional surface faces the second surface;
a shielding portion covering at least the back surface.
2. The package structure of claim 1, wherein the shielding portion further covers a side edge of the chip and the second surface.
3. The package structure according to claim 2, further comprising a solder ball on the second surface, wherein the shielding portion exposes the solder ball.
4. The package structure according to claim 2, further comprising an encapsulant connecting the side edge of the chip and the second surface, wherein the shielding portion is located on a side of the encapsulant away from the chip.
5. The package structure of claim 1, wherein the shielding portion is an epoxy or ink mixed with carbon black.
6. The package structure of claim 1, wherein the chip is a silicon chip.
7. The package structure of claim 1, wherein the substrate is a transparent substrate.
8. A method for packaging a chip, comprising the steps of:
defining a plurality of substrates distributed in an array on the base, wherein cutting channels are arranged between adjacent substrates;
fixing a functional surface of a chip and a second surface of the substrate;
forming a shielding part at least covering the back surface of the chip far away from the functional surface;
and dividing the substrate based on the cutting channels to form a plurality of single-grain packaging structures.
9. The method according to claim 8, wherein the step of forming a shielding portion covering at least a back surface of the chip away from the functional surface comprises:
forming a shielding part covering the back surface of the chip, the periphery of the chip and the second surface by a coating process;
forming an opening at the area of the shielding part corresponding to the second surface through an exposure and development process;
and forming a planting ball in the opening.
10. The method of claim 9, wherein the step of forming the shielding portion covering the back surface of the chip, the peripheral edge of the chip, and the second surface by a coating process further comprises:
and forming packaging glue for connecting the side edge of the chip and the second surface.
CN202010470133.0A 2020-05-28 2020-05-28 Chip packaging structure and packaging method Pending CN111508988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010470133.0A CN111508988A (en) 2020-05-28 2020-05-28 Chip packaging structure and packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010470133.0A CN111508988A (en) 2020-05-28 2020-05-28 Chip packaging structure and packaging method

Publications (1)

Publication Number Publication Date
CN111508988A true CN111508988A (en) 2020-08-07

Family

ID=71864498

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010470133.0A Pending CN111508988A (en) 2020-05-28 2020-05-28 Chip packaging structure and packaging method

Country Status (1)

Country Link
CN (1) CN111508988A (en)

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