JP2002289908A - Optical semiconductor device - Google Patents

Optical semiconductor device

Info

Publication number
JP2002289908A
JP2002289908A JP2001088442A JP2001088442A JP2002289908A JP 2002289908 A JP2002289908 A JP 2002289908A JP 2001088442 A JP2001088442 A JP 2001088442A JP 2001088442 A JP2001088442 A JP 2001088442A JP 2002289908 A JP2002289908 A JP 2002289908A
Authority
JP
Japan
Prior art keywords
chip
light
signal processing
terminal portion
light receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001088442A
Other languages
Japanese (ja)
Inventor
Hiroshi Oguri
洋 小栗
Hiroto Suzuki
広人 鈴木
Yoshimarou Fujii
義磨郎 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hamamatsu Photonics KK
Original Assignee
Hamamatsu Photonics KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hamamatsu Photonics KK filed Critical Hamamatsu Photonics KK
Priority to JP2001088442A priority Critical patent/JP2002289908A/en
Publication of JP2002289908A publication Critical patent/JP2002289908A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an optical semiconductor device, which is hardly influenced by external noise and also improves the visibility of an electrode at assembly work. SOLUTION: This optical semiconductor device is equipped with a light- receiving element chip 2 which has a light-receiving region 4, where a photodiode(PD) 8 is formed and a chip-mounting region 5 at its main face 2a; a signal output circuit 12 which processes the output signal of PD 8, and a signal processing IC chip 3 which has its input terminal part 13a and its output terminal part 13b; and a connector terminal part 7 is formed in the chip- mounting region 5; and also at least the chip-mounting region 5 is covered with a light-absorbing film 11 with the connector terminal 7 being exposed; and the signal-processing IC chip 3 is mounted on the chip-mounting region 5, so that, even if the light-receiving element chip 2 is irradiated with light, the light reflected from the main face 2a will not enter a circuit-forming face 14; and noise occurrence in the signal processing chip 3 is suppressed. Moreover, since the light-absorbing film 11 is small in quantity of reflected light, visibility of the connector terminal part 7 is enhanced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、入射した光を電気
信号に変換する光半導体装置に関する。
The present invention relates to an optical semiconductor device for converting incident light into an electric signal.

【0002】[0002]

【従来の技術】従来より、光通信をはじめ光を電気信号
に変換する種々の分野において、フォトダイオードと、
フォトダイオードの出力信号を信号処理する回路が形成
された信号処理ICチップとを備えた光半導体装置が利
用されている。
2. Description of the Related Art Conventionally, in various fields for converting light into an electric signal including optical communication, a photodiode,
2. Description of the Related Art An optical semiconductor device including a signal processing IC chip provided with a circuit for processing a signal output from a photodiode is used.

【0003】このような光半導体装置においては、フォ
トダイオードが形成された受光素子チップと信号処理I
Cチップをワイヤで電気的に接続すると、ワイヤがアン
テナとなって電磁波を拾い易く、電気信号にノイズが発
生してしまう。また、信号処理ICチップ自体の動作も
光の影響を受けやすく、電気信号にノイズが発生する。
これらの電磁波や光は、シールドによって遮断すること
が考えられるが、シールドの設置は部品点数と工程数の
増加を招き、製造効率を大きく低下させる。さらに、ワ
イヤの端部が各チップから外れて接続不良が生じたり、
ワイヤが各チップの縁端に触れて回路短絡が生じたりす
ることによる不良品の発生率が高い。そこで、突起した
電極端子(バンプ)同士が結合するように受光素子チッ
プ上に信号処理ICチップを搭載させることにより、ノ
イズの発生を抑制し、製造効率がよく、不良品の発生率
を抑えた光半導体装置が、特開2000−307133
号公報に掲載されている。
In such an optical semiconductor device, a light receiving element chip on which a photodiode is formed is connected to a signal processing IC.
When the C chip is electrically connected with a wire, the wire easily functions as an antenna to pick up an electromagnetic wave, and noise is generated in an electric signal. Further, the operation of the signal processing IC chip itself is easily affected by light, and noise is generated in the electric signal.
These electromagnetic waves and light may be shielded by a shield. However, the installation of the shield causes an increase in the number of components and the number of steps, and greatly reduces the manufacturing efficiency. Furthermore, the end of the wire may come off each chip, resulting in poor connection,
The occurrence rate of defective products due to the short circuit caused by the wire touching the edge of each chip is high. Therefore, by mounting the signal processing IC chip on the light receiving element chip so that the protruding electrode terminals (bumps) are connected to each other, noise generation is suppressed, production efficiency is improved, and the occurrence rate of defective products is suppressed. An optical semiconductor device is disclosed in JP-A-2000-307133.
Published in the official gazette.

【0004】[0004]

【発明が解決しようとする課題】上記従来技術に係る光
半導体装置では、さらに外部からの光や電磁波を遮る目
的で、信号処理ICチップの信号処理回路が形成された
面(回路形成面)の裏面に金属膜が設けられている。
In the optical semiconductor device according to the above prior art, the surface of the signal processing IC chip on which the signal processing circuit is formed (circuit forming surface) is provided for the purpose of further shielding external light and electromagnetic waves. A metal film is provided on the back surface.

【0005】しかしながら、受光素子チップ上には電源
供給用や信号処理用等の多くのAl配線が形成されてい
るため、そこで反射した反射光が信号処理ICチップの
回路形成面へ入射することにより、やはり信号処理IC
チップの出力信号には光や電磁波に起因するノイズが発
生してしまう。
However, since a large number of Al wirings for power supply and signal processing are formed on the light receiving element chip, the reflected light is incident on the circuit forming surface of the signal processing IC chip. , Also a signal processing IC
Noise due to light or electromagnetic waves is generated in the output signal of the chip.

【0006】本発明は、上記従来技術の問題点を解決す
るためになされたものであり、外部からノイズの影響を
受け難い上に、組立て作業時の電極部の視認性を向上さ
せた光半導体装置を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and is an optical semiconductor which is hardly affected by noise from the outside and has improved visibility of an electrode portion during an assembling operation. It is intended to provide a device.

【0007】[0007]

【課題を解決するための手段】本発明に係る光半導体装
置は、外部からの光を光電変換するフォトダイオードが
形成された受光領域と、この受光領域に隣接して形成さ
れたチップ搭載領域とを主面に有する受光素子チップ
と、フォトダイオードの出力信号を処理する信号処理回
路と、この信号処理回路に電気的に接続された入力端子
部および出力端子部とを主面に有する信号処理ICチッ
プとを備え、チップ搭載領域には入力端子部および出力
端子部と接続させるための接続端子部を形成すると共
に、少なくともチップ搭載領域は接続端子部を露出させ
た状態で光吸収膜で覆い、信号処理ICチップは、信号
処理回路の形成された回路形成面が受光素子チップと対
向する状態で入力端子部および出力端子部と接続端子部
が接続されるようにチップ搭載領域に搭載することを特
徴とする。
An optical semiconductor device according to the present invention comprises a light receiving area in which a photodiode for photoelectrically converting external light is formed, and a chip mounting area formed adjacent to the light receiving area. , A signal processing circuit for processing an output signal of a photodiode, and a signal processing IC having an input terminal portion and an output terminal portion electrically connected to the signal processing circuit on a main surface. A chip is provided, and a connection terminal portion for connecting to the input terminal portion and the output terminal portion is formed in the chip mounting region, and at least the chip mounting region is covered with a light absorbing film with the connection terminal portion exposed. The signal processing IC chip is connected so that the input terminal portion and the output terminal portion are connected to the connection terminal portion in a state where the circuit forming surface on which the signal processing circuit is formed faces the light receiving element chip. Characterized in that mounted on the flop mounting region.

【0008】本発明に係る光半導体装置によれば、受光
素子チップに光が照射されても、少なくともチップ搭載
領域は光吸収膜で覆われているため、受光素子チップ上
に形成された金属配線等の反射光は信号処理ICチップ
の回路形成面に入射しない。したがって、信号処理回路
の出力信号に光の影響によるノイズ発生を抑制すること
が可能とされる。
According to the optical semiconductor device of the present invention, even if the light receiving element chip is irradiated with light, at least the chip mounting area is covered with the light absorbing film, so that the metal wiring formed on the light receiving element chip is formed. The reflected light does not enter the circuit forming surface of the signal processing IC chip. Therefore, it is possible to suppress the generation of noise due to the influence of light on the output signal of the signal processing circuit.

【0009】さらには、光吸収膜は、接続端子部を露出
させた状態でチップ搭載領域を覆うため、チップ搭載領
域と接続端子部とで反射光量に差が生じる。それによ
り、組立て作業時の接続端子部(電極部)の視認性が向
上し、受光素子チップ上に信号処理ICチップを搭載す
る際の位置あわせが容易となる。
Further, since the light absorbing film covers the chip mounting area in a state where the connection terminal portion is exposed, a difference occurs in the amount of reflected light between the chip mounting area and the connection terminal section. Thereby, the visibility of the connection terminal portion (electrode portion) at the time of assembling work is improved, and the alignment at the time of mounting the signal processing IC chip on the light receiving element chip becomes easy.

【0010】また、信号処理ICチップの回路形成面
は、入力端子部および出力端子部を露出させた状態で光
吸収膜で覆われていることが好ましい。この場合、信号
処理ICチップの回路形成面に光が入射する場合であっ
ても、信号処理ICチップの出力信号におけるノイズの
発生が抑制される。
It is preferable that the circuit forming surface of the signal processing IC chip is covered with a light absorbing film in a state where the input terminal portion and the output terminal portion are exposed. In this case, even when light is incident on the circuit forming surface of the signal processing IC chip, generation of noise in the output signal of the signal processing IC chip is suppressed.

【0011】また、光吸収膜は、絶縁コートされたカー
ボン粒子を含む液状の感光性樹脂を硬化させた黒レジス
トであることが好ましい。この場合、光吸収膜は効果的
に光を吸収することができる上に、位置精度が高く、ま
た剥がれにくい。
The light absorbing film is preferably a black resist obtained by curing a liquid photosensitive resin containing carbon particles coated with an insulating material. In this case, the light-absorbing film can effectively absorb light, has high positional accuracy, and is hardly peeled off.

【0012】[0012]

【発明の実施の形態】以下、添付図面を参照して本発明
に係る光半導体装置の実施の形態を詳細に説明する。な
お、同一の要素には同一の符号を付し、重複する説明を
省略する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the optical semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. Note that the same components are denoted by the same reference numerals, and redundant description will be omitted.

【0013】図1は、本発明の第1実施形態に係る光半
導体装置1を示す平面図であり、図2は図1のII−II線
に沿った断面図である。
FIG. 1 is a plan view showing an optical semiconductor device 1 according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line II-II in FIG.

【0014】図1,2に示すように光半導体装置1は、
受光素子チップ2と、受光素子チップ2上に搭載された
信号処理ICチップ3とで構成されている。受光素子チ
ップ2は、n型半導体(例えばシリコン)である基板6
をベースとして、SiO2またはSiNなどの絶縁膜
(不図示)が形成されている。また、受光素子チップ2
は主面2aに、p型不純物拡散層領域である受光領域4
と、この受光領域4に隣接したチップ搭載領域5とを有
している。そのため、受光領域4ではp型不純物拡散層
と基板6のn型半導体とがPN接合して、フォトダイオ
ード8を形成している。つまり、受光領域4に外部から
光が入射すると、光電変換されて電気信号として出力さ
れる。
As shown in FIGS. 1 and 2, the optical semiconductor device 1 comprises:
It comprises a light receiving element chip 2 and a signal processing IC chip 3 mounted on the light receiving element chip 2. The light receiving element chip 2 is a substrate 6 made of an n-type semiconductor (for example, silicon).
An insulating film (not shown) such as SiO2 or SiN is formed on the basis of the above. Also, the light receiving element chip 2
Denotes a light receiving region 4 which is a p-type impurity diffusion layer region on the main surface 2a.
And a chip mounting area 5 adjacent to the light receiving area 4. Therefore, in the light receiving region 4, the p-type impurity diffusion layer and the n-type semiconductor of the substrate 6 are PN-joined to form the photodiode 8. That is, when light enters the light receiving region 4 from the outside, it is photoelectrically converted and output as an electric signal.

【0015】また、受光素子チップ2の主面2aのチッ
プ搭載領域5には、接続端子部としてAu、In等の金
属であるバンプ電極7が形成されている。なお、バンプ
電極7には、金属以外にも、導電性のフィラーが混入し
た樹脂、導電性フィラーを含む樹脂からなるACF(An
isotroptic Conductive Film)など電気的に接続できる
ものを用いればよい。このバンプ電極7は、受光領域4
とチップ搭載領域5以外の領域に形成された電力供給用
および信号出力用の電極パッド9並びに受光領域4のフ
ォトダイオード8と、アルミニウム等の金属又はポリシ
リコン等の導電性材料で形成された配線10を介してそ
れぞれ電気的に接続されている。さらに、受光素子チッ
プ2の主面2aのうち、バンプ電極7を除いたチップ搭
載領域5は、配線10の上から光吸収膜11である、絶
縁コートされたカーボン粒子を含む液状の感光性樹脂を
硬化させた黒レジストで覆われており、この光吸収膜1
1は検出対象となる光を吸収する特性を有する。
In the chip mounting area 5 on the main surface 2a of the light receiving element chip 2, a bump electrode 7 made of a metal such as Au or In is formed as a connection terminal. In addition, the bump electrode 7 is made of a resin mixed with a conductive filler and an ACF (An
What can be electrically connected, such as an isotroptic conductive film, may be used. This bump electrode 7 is connected to the light receiving area 4.
And power supply and signal output electrode pads 9 formed in regions other than the chip mounting region 5 and the photodiodes 8 in the light receiving region 4, and wiring formed of a metal such as aluminum or a conductive material such as polysilicon. 10 are electrically connected to each other. Further, in the main surface 2 a of the light receiving element chip 2, the chip mounting region 5 excluding the bump electrodes 7 is a light absorbing film 11 from above the wiring 10, which is a liquid photosensitive resin containing carbon particles coated with insulation. This light absorbing film 1 is covered with a hardened black resist.
Numeral 1 has a characteristic of absorbing light to be detected.

【0016】一方、信号処理ICチップ3には、フォト
ダイオード8の出力信号に増幅等の処理をする信号処理
回路12と、この信号処理回路12と電気的に接続さ
れ、受光素子チップ2の接続端子部7に接続される入出
力端子部13が形成されている。なお、入出力端子部1
3は、入力端子部13aおよび出力端子部13bにより
構成されている。その信号処理回路12が形成された回
路形成面14は、各入出力端子部13を露出させた状態
で、絶縁コートされたカーボン粒子を含む液状の感光性
樹脂を硬化させた黒レジスト11で覆われている。
On the other hand, the signal processing IC chip 3 has a signal processing circuit 12 for performing processing such as amplification on the output signal of the photodiode 8, and is electrically connected to the signal processing circuit 12 to connect the light receiving element chip 2. An input / output terminal unit 13 connected to the terminal unit 7 is formed. The input / output terminal 1
Reference numeral 3 includes an input terminal 13a and an output terminal 13b. The circuit forming surface 14 on which the signal processing circuit 12 is formed is covered with a black resist 11 obtained by curing a liquid photosensitive resin containing carbon particles coated with an insulating material while exposing the input / output terminals 13. Have been done.

【0017】続いて、光半導体装置1の動作を図1およ
び図2を参照しつつ簡単に説明する。
Next, the operation of the optical semiconductor device 1 will be briefly described with reference to FIGS.

【0018】光半導体装置1に外部から光が照射される
と、受光領域4に入射した光は、フォトダイオード8に
より光電変換され、電気信号として検出される。また、
光吸収膜11に覆われた領域(チップ搭載領域)5で
は、バンプ電極7以外は配線10も含めてすべて光吸収
膜11で覆われているため、入射光は吸収される。一
方、受光領域4以外の領域で、かつチップ搭載領域5以
外の領域では、受光素子チップ2の主面2a上の配線等
で入射光は反射される。しかし、チップ搭載領域5以外
で反射した光は、反射方向が回路形成面14に向いてい
ないため、信号処理ICチップ3の信号処理回路12に
は入射しない。
When the optical semiconductor device 1 is irradiated with light from the outside, the light incident on the light receiving region 4 is photoelectrically converted by the photodiode 8 and detected as an electric signal. Also,
In the region (chip mounting region) 5 covered with the light absorbing film 11, the light except for the bump electrode 7 and the wiring 10 is entirely covered with the light absorbing film 11, so that the incident light is absorbed. On the other hand, in an area other than the light receiving area 4 and in an area other than the chip mounting area 5, incident light is reflected by a wiring or the like on the main surface 2a of the light receiving element chip 2. However, the light reflected from the area other than the chip mounting area 5 does not enter the signal processing circuit 12 of the signal processing IC chip 3 because the reflection direction is not directed to the circuit forming surface 14.

【0019】そのため、光半導体装置1に光が照射され
た場合、受光素子チップ2の主面2aで反射した光が、
信号処理ICチップ3の信号処理回路12に入射するこ
とはなく、信号処理回路12の出力信号に光の影響によ
るノイズ発生を抑制することが可能とされる。したがっ
て、製造効率の低下を招くシールドなどを設けずとも、
受光領域4のフォトダイオード8からの出力信号は、外
部から光や電磁波などに起因するノイズの影響を受け難
くすることが可能とされる。
Therefore, when the optical semiconductor device 1 is irradiated with light, the light reflected on the main surface 2a of the light receiving element chip 2 becomes
The signal does not enter the signal processing circuit 12 of the signal processing IC chip 3, and it is possible to suppress the generation of noise due to the influence of light on the output signal of the signal processing circuit 12. Therefore, even without providing a shield or the like that causes a decrease in manufacturing efficiency,
The output signal from the photodiode 8 in the light receiving area 4 can be made less susceptible to external noise or noise.

【0020】続いて、本発明の光半導体装置1の製造方
法について説明する。図5および図6に示すように、ま
ず、半導体ウエハ30にホトリソグラフィ工程、デポジ
ション工程、エッチング工程などの工程を施して半導体
素子31を多数形成すると同時に、半導体ウエハ30の
半導体素子31が形成されていない領域にフォトマスク
との位置決め用のマーク32を形成する。ここで、フォ
トマスクとの位置決め用のマーク32は、光半導体素子
1の製造工程のホトリソグラフィ工程で素子のパターン
露光をする際に用いるフォトマスクと半導体素子31と
の位置決め用マーク32を用いることができる。なお、
半導体ウエハ30には、ホトリソグラフィ工程での方向
検知用に半導体ウエハ30の結晶学的基準方向を示す切
り欠きであるオリエンテーションフラット33が設けら
れている。マーク32は、オリエンテーションフラット
33に対し、ほぼ平行に2ヶ所設けられる。
Next, a method for manufacturing the optical semiconductor device 1 of the present invention will be described. As shown in FIGS. 5 and 6, first, the semiconductor wafer 30 is subjected to steps such as a photolithography step, a deposition step, and an etching step to form a large number of semiconductor elements 31, and at the same time, the semiconductor elements 31 of the semiconductor wafer 30 are formed. A mark 32 for positioning with a photomask is formed in a region that is not formed. Here, as the mark 32 for positioning with the photomask, the mark 32 for positioning between the photomask and the semiconductor element 31 used when pattern exposure of the element in the photolithography step of the manufacturing process of the optical semiconductor element 1 is used. Can be. In addition,
The semiconductor wafer 30 is provided with an orientation flat 33 which is a notch indicating a crystallographic reference direction of the semiconductor wafer 30 for detecting a direction in a photolithography process. The marks 32 are provided at two positions substantially parallel to the orientation flat 33.

【0021】次に、図7および図8にに示すように、半
導体素子31が形成されていない領域であって、マーク
32の領域を含む領域にマスキングテープ34を貼付し
てマーク32を被覆後、図9および図10に示すように
に半導体ウエハ30の表面全体に感光性の黒色レジスト
11を塗布する。感光性の黒色レジスト11の塗布にあ
たっては、半導体ウエハ30をレジストコーティング用
の回転塗布装置にセットして、液状の感光性の黒色レジ
スト剤を滴下し、1000rpmの回転により所定の膜
厚となるように塗布する。また、黒色レジスト11は、
半導体素子31の形成面の前面を覆うと共に、マスキン
グテープ34上も覆う。マスキングテープ34には、ア
クリル系樹脂が接着剤として塗布されたポリエステル系
フィルムを使用したが、その他にも、後のプリベーク時
の温度(約80℃)に耐えられ、マスキングテープ34
の接着層の半導体ウエハ30への転写のない材質を適宜
選択すればよい。
Next, as shown in FIGS. 7 and 8, a masking tape 34 is applied to the area where the semiconductor element 31 is not formed and which includes the area of the mark 32 to cover the mark 32. 9 and 10, a photosensitive black resist 11 is applied to the entire surface of the semiconductor wafer 30. In applying the photosensitive black resist 11, the semiconductor wafer 30 is set in a spin coating device for resist coating, a liquid photosensitive black resist is dropped, and a predetermined film thickness is obtained by rotating at 1000 rpm. Apply to. In addition, the black resist 11
In addition to covering the front surface of the surface on which the semiconductor element 31 is formed, the masking tape 34 is also covered. As the masking tape 34, a polyester film coated with an acrylic resin as an adhesive was used. In addition, the masking tape 34 can withstand the temperature during pre-baking (about 80 ° C.).
The material which does not transfer the adhesive layer to the semiconductor wafer 30 may be appropriately selected.

【0022】続いて、感光性の黒色レジスト11が塗布
された半導体ウエハ30に、例えば80℃で30分間程
度の加熱処理を施して、感光性の黒色レジスト11をプ
リベークし、以後の露光時に寸法不良を誘発する原因と
なる感光性の黒色レジスト11の溶剤を蒸発させる。こ
のプリベークにより、半導体ウエハ30と感光性の黒色
レジスト11とは、ある程度密着した状態となる。
Subsequently, the semiconductor wafer 30 coated with the photosensitive black resist 11 is subjected to a heat treatment at, for example, 80 ° C. for about 30 minutes to pre-bake the photosensitive black resist 11 and to obtain a dimension during subsequent exposure. The solvent of the photosensitive black resist 11 which causes a defect is evaporated. By this pre-baking, the semiconductor wafer 30 and the photosensitive black resist 11 are in a state of being in close contact to some extent.

【0023】次に、図11および図12に示すように、
マスキングテープ34を半導体ウエハ30から剥離し、
マーク32を露出させる。この結果、感光性の黒色レジ
スト11が完全な遮光性を有していても、光によるマー
ク32の検出が可能となる。
Next, as shown in FIGS. 11 and 12,
Peeling off the masking tape 34 from the semiconductor wafer 30;
The mark 32 is exposed. As a result, even if the photosensitive black resist 11 has perfect light shielding properties, the mark 32 can be detected by light.

【0024】引き続き、マスクアライナ装置によって、
検出されたマーク32の位置に従って半導体ウエハ30
とフォトマスク(図示せず)との位置決めを行う。そし
て、フォトマスクを解して感光性の黒色レジスト11を
露光し、現像、リンス後ポストキュア(例えば、230
℃、15分)して、露光された感光性の黒色レジスト1
1の不要部を除去し、パターン付けを完了する。こうし
て、図13および図14に示すように、半導体素子31
の表面に遮光膜の機能を果たす黒色レジスト11が所定
のパターン(チップ搭載領域5のうち接続端子部7のみ
露出したパターン)で形成される。
Subsequently, the mask aligner device
The semiconductor wafer 30 according to the detected position of the mark 32
And a photomask (not shown). Then, the photosensitive black resist 11 is exposed by removing the photomask, developed, rinsed, and post-cured (for example, 230
C., 15 minutes), and then exposed to light.
Then, the unnecessary portion 1 is removed, and the patterning is completed. Thus, as shown in FIG. 13 and FIG.
Is formed in a predetermined pattern (a pattern in which only the connection terminal portion 7 is exposed in the chip mounting area 5) on the surface of the substrate.

【0025】次に、ウエハ状態で図1に示すような単一
チップ領域の信号処理ICチップ3を、信号処理回路1
2の回路形成面14が受光素子チップ2と対向する状態
で、入力及び出力端子部13a、13bで構成された入
出力端子部13に対応する接続端子部7が電気的に接続
されるように、受光素子チップ2上のチップ搭載領域5
に搭載する。受光素子チップ2の主面2aに配置された
電極パッド9を位置決めマーカとして見ながら、信号処
理ICチップ2をバンプ接続する。このとき、チップ搭
載領域5の接続端子部7は、黒色レジスト11から露出
しているため、視覚的に確認することが容易である。
Next, the signal processing IC chip 3 in a single chip area as shown in FIG.
2 with the circuit forming surface 14 facing the light receiving element chip 2 so that the connection terminal portions 7 corresponding to the input / output terminal portions 13 constituted by the input and output terminal portions 13a and 13b are electrically connected. Chip mounting area 5 on light receiving element chip 2
To be mounted on. The signal processing IC chip 2 is bump-connected while viewing the electrode pads 9 arranged on the main surface 2a of the light receiving element chip 2 as positioning markers. At this time, since the connection terminals 7 of the chip mounting area 5 are exposed from the black resist 11, it is easy to visually confirm.

【0026】このとき、金属製のバンプにて電気的接続
を行う場合は、Auボール又はInボールを受光素子チ
ップ2上の接続端子部7に形成した後、位置決めマーカ
を見ながら、信号処理ICチップ2をバンプに接続す
る。それに対して、ACFの場合は、受光素子チップ2
又は信号処理ICチップ3にACFを仮接着した後、位
置マーカを見ながら受光素子チップ2と信号処理ICチ
ップ3を位置合わせし、仮接着を行い圧着硬化させる。
At this time, when the electrical connection is made by using a metal bump, an Au ball or an In ball is formed on the connection terminal portion 7 on the light receiving element chip 2 and then the signal processing IC is viewed while looking at the positioning marker. Chip 2 is connected to the bump. On the other hand, in the case of the ACF, the light receiving element chip 2
Alternatively, after the ACF is temporarily bonded to the signal processing IC chip 3, the light receiving element chip 2 and the signal processing IC chip 3 are aligned while watching the position marker, and the temporary bonding is performed and the pressure bonding and curing are performed.

【0027】各単一チップ領域に信号処理ICチップ3
を搭載し終えたら、ダイシングを行って、各チップを分
離する。ダイシングの際に受光素子チップ2からの削り
カス等により、各バンプ電極7間が接続されショート等
の不良を発生させる可能性がある場合は、ダイシングの
前に、受光素子チップ2と信号処理ICチップ3との間
隙にアンダーフィル樹脂を充填しておけば、ショート等
による歩留まりの低下の恐れはなくなる。
In each single chip area, a signal processing IC chip 3
After mounting, dicing is performed to separate each chip. If there is a possibility that the bump electrodes 7 are connected to each other due to shavings or the like from the light receiving element chip 2 during dicing and a defect such as a short circuit may occur, the light receiving element chip 2 and the signal processing IC before dicing. By filling the gap with the chip 3 with an underfill resin, there is no possibility that the yield may be reduced due to a short circuit or the like.

【0028】次に、本発明の第2実施形態に係る光半導
体装置20について、図3と図4を参照しつつ説明す
る。なお、図3は、本発明の実施形態2に係る光半導体
装置20を示す平面図であり、図4は図3のIV−IV線に
沿った断面図である。
Next, an optical semiconductor device 20 according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a plan view showing the optical semiconductor device 20 according to the second embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV in FIG.

【0029】光半導体装置20は、受光素子チップ2の
主面2aのうち、受光領域4とバンプ電極7と電極パッ
ド9を除いた領域は、配線10も含めてすべて光吸収膜
11で覆われている点で、光半導体装置1と異なる。そ
のため、光半導体装置20に外部から光が照射される
と、受光領域4とバンプ電極7と電極パッド9以外の領
域に照射された光は、検出対象の光を吸収する光吸収膜
11によって吸収され、反射しない。したがって、照射
光が反射されて、信号処理ICチップ3の信号処理回路
12に入射することはない。また、外部からの光が不特
定の方向から信号処理回路12の回路形成面14に入射
する場合でも、入出力端子部13以外の回路形成面14
を覆う光吸収膜11によって信号処理回路12の出力信
号に発生するノイズを抑制できる。
In the optical semiconductor device 20, a region other than the light receiving region 4, the bump electrodes 7, and the electrode pads 9 in the main surface 2 a of the light receiving element chip 2 is covered with the light absorbing film 11 including the wiring 10. This is different from the optical semiconductor device 1. Therefore, when light is applied to the optical semiconductor device 20 from the outside, the light applied to regions other than the light receiving region 4, the bump electrode 7, and the electrode pad 9 is absorbed by the light absorbing film 11 that absorbs light to be detected. Is not reflected. Therefore, the irradiation light is not reflected and enters the signal processing circuit 12 of the signal processing IC chip 3. Further, even when external light enters the circuit forming surface 14 of the signal processing circuit 12 from an unspecified direction, the circuit forming surface 14
The noise generated in the output signal of the signal processing circuit 12 can be suppressed by the light absorbing film 11 covering.

【0030】そのため、光の影響により信号処理回路1
2の出力信号にノイズが発生すること抑えることが可能
とされる。それにより、製造効率の低下を招くシールド
などを設けずとも、受光領域4のフォトダイオード8か
らの出力信号は、外部から光や電磁波などに起因するノ
イズの影響を受け難くすることが可能とされる。
Therefore, the signal processing circuit 1 is affected by light.
2 can be prevented from generating noise. Thus, even without providing a shield or the like that causes a decrease in manufacturing efficiency, it is possible to make the output signal from the photodiode 8 in the light receiving area 4 less susceptible to external noise or noise caused by electromagnetic waves or the like. You.

【0031】また、本発明は、上記実施形態に限定され
るものではなく様々の変形が可能である。
Further, the present invention is not limited to the above-described embodiment, and various modifications are possible.

【0032】例えば、受光領域4に形成されるフォトダ
イオード8は、単一のダイオードに限らず、複数のダイ
オードをアレイ状に並べたものでもよい。また、接続端
子部7と入出力端子部13を電気的に接続する方法は、
直接電極パッド同士を結合したり、導電性物質を介して
接続したりするなど、バンプ接続に限らず、確実に電気
信号等を伝送できるものであればよく、またバンプ電極
部は信号処理ICチップ3側に形成してもよい。さら
に、光吸収膜11は、受光素子チップ側と信号処理チッ
プ側で異なる光吸収膜を選択しても良い。
For example, the photodiode 8 formed in the light receiving region 4 is not limited to a single diode, but may be a plurality of diodes arranged in an array. The method of electrically connecting the connection terminal 7 and the input / output terminal 13 is as follows.
It is not limited to bump connection, such as directly connecting electrode pads or connecting via a conductive substance, as long as it can reliably transmit electric signals and the like. The bump electrode portion is a signal processing IC chip It may be formed on the third side. Further, as the light absorbing film 11, different light absorbing films may be selected on the light receiving element chip side and the signal processing chip side.

【0033】[0033]

【発明の効果】以上説明したように本発明によれば、ワ
イヤを用いず、受光領域と信号処理ICチップとを容易
に接続することができる。また、ワイヤが存在せず、信
号処理ICチップとの接続部に光が入射することがな
く、しかも少なくとも接続端子部以外のチップ搭載領域
を黒色レジスト等の光吸収膜で被覆しているため、受光
素子チップの主面、特に信号配線等からの反射光が、信
号処理ICチップの回路形成面に入射するのを防ぎ、ノ
イズの発生を低減することができる。
As described above, according to the present invention, the light receiving area and the signal processing IC chip can be easily connected without using wires. In addition, since there is no wire, light does not enter the connection portion with the signal processing IC chip, and at least the chip mounting area other than the connection terminal portion is covered with a light absorbing film such as a black resist, It is possible to prevent reflected light from the main surface of the light receiving element chip, particularly from signal wiring or the like, from being incident on the circuit forming surface of the signal processing IC chip, thereby reducing noise.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る実施形態1に係る光半導体装置1
を示す平面図である。
FIG. 1 is an optical semiconductor device 1 according to a first embodiment of the present invention.
FIG.

【図2】図1のII−II線に沿った断面図である。FIG. 2 is a sectional view taken along the line II-II in FIG.

【図3】本発明に係る実施形態2に係る光半導体装置2
0を示す平面図である。
FIG. 3 is an optical semiconductor device 2 according to a second embodiment of the present invention.
FIG.

【図4】図3のIV−IV線に沿った断面図である。FIG. 4 is a sectional view taken along the line IV-IV in FIG. 3;

【図5】製造工程における被覆前の半導体ウエハを示す
平面図である。
FIG. 5 is a plan view showing a semiconductor wafer before coating in a manufacturing process.

【図6】図5のVI−VI線に沿った断面図である。FIG. 6 is a sectional view taken along the line VI-VI of FIG. 5;

【図7】製造工程における被覆前でテープ貼付後の半導
体ウエハを示す平面図である。
FIG. 7 is a plan view showing a semiconductor wafer after tape application before coating in a manufacturing process.

【図8】図7のVIII−VIII線に沿った断面図である。8 is a sectional view taken along the line VIII-VIII in FIG.

【図9】製造工程における被覆後の半導体ウエハを示す
平面図である。
FIG. 9 is a plan view showing a semiconductor wafer after coating in a manufacturing process.

【図10】図9のX−X線に沿った断面図である。FIG. 10 is a sectional view taken along line XX of FIG. 9;

【図11】製造工程における被覆後でテープ剥離後の半
導体ウエハを示す平面図である。
FIG. 11 is a plan view showing the semiconductor wafer after tape peeling after coating in a manufacturing process.

【図12】図11のXII−XII線に沿った断面図であ
る。
FIG. 12 is a sectional view taken along the line XII-XII in FIG. 11;

【図13】製造工程によって所定のパターンが形成され
た半導体ウエハを示す平面図である。
FIG. 13 is a plan view showing a semiconductor wafer on which a predetermined pattern is formed by a manufacturing process.

【図14】図13のXIV−XIV線に沿った断面図であ
る。
FIG. 14 is a sectional view taken along the line XIV-XIV in FIG.

【符号の説明】[Explanation of symbols]

1……光半導体装置、2……受光素子チップ、2a……
主面、3……信号処理ICチップ、3a……主面、4…
…受光領域、5……チップ搭載領域、7……バンプ電極
(接続端子部)、8……フォトダイオード、11……黒
色レジスト(光吸収膜)、12……信号処理回路、13
a……入力端子部、13b……出力端子部、13……入
出力端子部、14……回路形成面。
1 ... optical semiconductor device, 2 ... light receiving element chip, 2a ...
Main surface, 3 ... Signal processing IC chip, 3a ... Main surface, 4 ...
... Light receiving area, 5... Chip mounting area, 7... Bump electrode (connection terminal), 8... Photodiode, 11... Black resist (light absorbing film), 12.
a ... input terminal portion, 13b ... output terminal portion, 13 ... input / output terminal portion, 14 ... circuit formation surface.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 藤井 義磨郎 静岡県浜松市市野町1126番地の1 浜松ホ トニクス株式会社内 Fターム(参考) 4M109 AA01 BA07 CA10 ED01 EE13 GA01 4M118 AA05 AB05 BA02 BA03 CA03 DD02 FC05 FC15 FC18 GB01 GB03 HA03 HA07 HA12 HA21 HA31 5F049 MA02 MB03 NA04 NB01 RA06 SS03 SZ10 UA05  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshimuro Fujii 1126 Nomachi, Hamamatsu-shi, Shizuoka Prefecture F-term in Hamamatsu Photonics Co., Ltd. DD02 FC05 FC15 FC18 GB01 GB03 HA03 HA07 HA12 HA21 HA31 5F049 MA02 MB03 NA04 NB01 RA06 SS03 SZ10 UA05

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】外部からの光を光電変換するフォトダイオ
ードが形成された受光領域と、この受光領域に隣接して
形成されたチップ搭載領域とを主面に有する受光素子チ
ップと、 前記フォトダイオードの出力信号を処理する信号処理回
路と、この信号処理回路に電気的に接続された入力端子
部および出力端子部とを主面に有する信号処理ICチッ
プと を備え、 前記チップ搭載領域には前記入力端子部および前記出力
端子部と接続させるための接続端子部を形成すると共
に、少なくとも前記チップ搭載領域は前記接続端子部を
露出させた状態で光吸収膜で覆い、 前記信号処理ICチップは、前記信号処理回路の形成さ
れた回路形成面が前記受光素子チップと対向する状態で
前記入力端子部および前記出力端子部と前記接続端子部
が接続されるように前記チップ搭載領域に搭載すること
を特徴とする光半導体装置。
A light receiving element chip having a light receiving area in which a photodiode for photoelectrically converting external light is formed, and a chip mounting area formed adjacent to the light receiving area on a main surface; And a signal processing IC chip having a main surface having an input terminal portion and an output terminal portion electrically connected to the signal processing circuit. A connection terminal portion for connecting to the input terminal portion and the output terminal portion is formed, and at least the chip mounting area is covered with a light absorbing film in a state where the connection terminal portion is exposed, and the signal processing IC chip includes: The input terminal portion and the output terminal portion are connected to the connection terminal portion in a state where a circuit forming surface on which the signal processing circuit is formed faces the light receiving element chip. The optical semiconductor device is mounted on the chip mounting area as described above.
【請求項2】 前記信号処理ICチップの前記回路形成
面は、前記入力端子部および前記出力端子部を露出させ
た状態で光吸収膜で覆われていることを特徴とする請求
項1記載の光半導体装置。
2. The signal processing IC chip according to claim 1, wherein the circuit forming surface is covered with a light absorbing film in a state where the input terminal portion and the output terminal portion are exposed. Optical semiconductor device.
【請求項3】 前記光吸収膜は、絶縁コートされたカー
ボン粒子を含む液状の感光性樹脂を硬化させた黒レジス
トであることを特徴とする請求項1または2に記載の光
半導体装置。
3. The optical semiconductor device according to claim 1, wherein the light absorbing film is a black resist obtained by curing a liquid photosensitive resin containing carbon particles coated with insulation.
JP2001088442A 2001-03-26 2001-03-26 Optical semiconductor device Pending JP2002289908A (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
JP2001088442A JP2002289908A (en) 2001-03-26 2001-03-26 Optical semiconductor device

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Publication Number Publication Date
JP2002289908A true JP2002289908A (en) 2002-10-04

Family

ID=18943537

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Country Link
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JP2007155561A (en) * 2005-12-07 2007-06-21 Acrorad Co Ltd Radiological image detection module and radiological image detection device
CN100355078C (en) * 2002-12-27 2007-12-12 三洋电机株式会社 Integrated circuit for light coder
WO2010073520A1 (en) * 2008-12-26 2010-07-01 パナソニック株式会社 Solid-state imaging device and manufacturing method therefor
US7781720B2 (en) 2002-10-25 2010-08-24 Gennum Corporation Direct attach optical receiver module and method of testing
WO2012093426A1 (en) * 2011-01-07 2012-07-12 パナソニック株式会社 Semiconductor module
US10700116B2 (en) 2016-01-13 2020-06-30 Hamamatsu Photonics K.K. Rear-surface-incident solid state imaging element and method for manufacturing same
WO2024084865A1 (en) * 2022-10-19 2024-04-25 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device

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