CN111508892B - Method for manufacturing SOI wafer - Google Patents

Method for manufacturing SOI wafer Download PDF

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Publication number
CN111508892B
CN111508892B CN202010349382.4A CN202010349382A CN111508892B CN 111508892 B CN111508892 B CN 111508892B CN 202010349382 A CN202010349382 A CN 202010349382A CN 111508892 B CN111508892 B CN 111508892B
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layer
silicon
germanium
wafer
fabricating
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CN111508892A (en
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陈勇跃
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a manufacturing method of an SOI wafer, which comprises the following steps: epitaxially growing a first germanium-silicon layer on a first surface of a first silicon wafer; forming a first interface layer and a second high dielectric constant layer; implanting hydrogen impurities from within the first silicon germanium layer; forming a third silicon dioxide layer on the first surface of the second silicon wafer; bonding the second high dielectric constant layer and the third silicon dioxide layer; and removing the first germanium-silicon layer and the first silicon wafer which are positioned at the bottom of the hydrogen impurity injection region by stripping treatment, taking the reserved first germanium-silicon layer as a top germanium-silicon layer, stacking a first interface layer, a second high dielectric constant layer and a third silicon dioxide layer to form a high dielectric constant medium buried layer, and taking the second silicon wafer as bulk silicon. The invention can simultaneously form the high-dielectric-constant dielectric buried layer and the top germanium-silicon layer, can enhance the capacitive coupling effect of the back gate of the device to the channel region, reduce the power loss of the device, and can improve the performance of the device at the same time, and the forming process of the top germanium-silicon layer is simple.

Description

Method for manufacturing SOI wafer
Technical Field
The present invention relates generally to semiconductor integrated circuit fabrication, and more particularly to a method for fabricating silicon-on-insulator (SOI) wafers.
Background
With the continuous rapid development of integrated circuits, the critical dimensions of devices in the circuits are continuously reduced, the dimensions of corresponding component elements are continuously thinned, and Fully Depleted (FD) SOI is one of the main choices for continuous miniaturization of devices. With the continuous downsizing of FDSOI devices, on the one hand, different device threshold Voltages (VT) can be modulated by introducing a Si-connected Buried Oxide (BOX) of a Body (BULK) region into a Hybrid (Hybrid) region, which causes a requirement of enhancing the control capability of a back gate on a channel region, and the higher the dielectric constant, i.e., k, of the BOX, the stronger the capacitive coupling effect of the back gate connected through the Hybrid region on the channel region, and the stronger the control force of the back gate in Forward Body Bias (FBB) and Reverse Body Bias (RBB) modes.
On the other hand, further enhancement of device performance requires the provision of a silicon germanium layer (SiGe) as a high performance device for the channel region, since the silicon germanium layer can enhance hole mobility and thus PMOS performance.
Therefore, it is also desirable to prepare a structure in which the BOX is a high-k dielectric and the SiGe material is used as the channel region, so that the control forces and device performance of the back gate FBB and RBB modes can be improved.
In the existing mainstream methods, a SiGe channel region is prepared by adopting a Ge condensation method, the working procedures are various and complex, and a simpler and easier method is needed.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of an SOI wafer, which can form the SOI wafer with a high dielectric constant medium buried layer and a top germanium-silicon layer, can enhance the capacitive coupling effect of a back gate of a device to a channel region, is beneficial to forming an FDSOI device, remarkably improves the control force of the back gate in FBB and RBB modes, reduces the power loss of the device, can simultaneously improve the carrier mobility of PMOS, improves the performance of the device, and has simple forming process of the top germanium-silicon layer.
In order to solve the technical problems, the manufacturing method of the SOI wafer provided by the invention comprises the following steps:
step one, providing a first silicon wafer, and epitaxially growing a first germanium-silicon layer on a first surface of the first silicon wafer, wherein the first germanium-silicon layer is used for forming a top germanium-silicon layer, and the thickness of the first germanium-silicon layer is larger than that of the top germanium-silicon layer.
And step two, sequentially forming a first interface layer and a second high dielectric constant layer on the surface of the first germanium-silicon layer.
And thirdly, implanting hydrogen ions from above the second high dielectric constant layer to implant hydrogen impurities into the first germanium-silicon layer.
And step four, providing a second silicon wafer, and forming a third silicon dioxide layer on the first surface of the second silicon wafer.
And fifthly, bonding the second high dielectric constant layer and the third silicon dioxide layer to realize bonding (bonding) of the first silicon wafer and the second silicon wafer.
And step six, stripping the first silicon wafer, wherein the stripping is carried out to remove the first germanium-silicon layer and the first silicon wafer which are positioned at the bottom of the hydrogen impurity injection region, the first germanium-silicon layer is used as the top germanium-silicon layer, the first interface layer, the second high dielectric constant layer and the third silicon dioxide layer are stacked to form a high dielectric constant medium buried layer, and the second silicon wafer is used as bulk silicon.
A further improvement is that the first silicon wafer is a donor (donor) impurity doped silicon wafer, i.e., a donor wafer.
A further improvement is that the first interface layer has a thickness ofIs a very thin silica film.
A further improvement is that the first interface layer is formed using an Atomic Layer Deposition (ALD) process.
A further improvement is that the third silicon dioxide layer has a thickness ofIs a very thin silica film.
The third silicon dioxide layer is formed by adopting a thermal oxidation process, and is also formed on the second surface and the side surface of the second silicon wafer, wherein the first surface and the second surface of the second silicon wafer are the front surface and the back surface of the second silicon wafer.
A further improvement is that the k value of the second high dielectric constant layer is higher than the k value of silicon dioxide.
In a further improvement, the k value of the second high dielectric constant layer is 5 times or more the k value of silicon dioxide.
A further improvement is that the material of the second high dielectric constant layer comprises hafnium oxynitride, zirconium oxide or tantalum oxide. Typically, hafnium oxynitride is prepared using the formula HfO x N y And (3) representing. Molecular formula ZrO for zirconia x Here x is independent of x in HfOxNy. Molecular formula Ta for tantalum oxide 2 O 5 And (3) representing.
In the second step, the depth of the hydrogen ion implantation corresponds to the thickness of the top germanium-silicon layer.
In the sixth step, after the Si-H-Si bond, the Si-H-Ge bond and the Ge-H-Ge bond are torn off, the stripping process is stopped, and then annealing treatment is carried out.
In a further improvement, after the annealing treatment is completed, the method further comprises polishing the top-layer germanium-silicon layer by a chemical mechanical polishing process and adjusting the thickness of the top-layer germanium-silicon layer to a required thickness.
In a further improvement, in the fifth step, the first silicon wafer and the second silicon wafer are bonded in a bonding machine.
A further improvement is that the top silicon germanium layer is used to form an FDSOI device that includes a gate structure, a source region, a drain region, and a channel region.
The grid structure is formed on the surface of the top-layer germanium-silicon layer, the source region and the drain region are formed in the top-layer germanium-silicon layer on two sides of the grid structure in a self-aligned mode, the channel region is composed of the top-layer germanium-silicon layer located between the source region and the drain region, and the thickness of the top-layer germanium-silicon layer is enough that the channel region at the bottom of the inversion layer is completely consumed when the FDSOI device is conducted.
The method is characterized in that the bulk silicon is connected with a back gate electrode, and the back gate electrode controls the channel region through the high-dielectric-constant buried layer and adjusts the threshold voltage of the FDSOI device.
In a further improvement, in the first step, when the first germanium-silicon epitaxial layer is epitaxially grown, the germanium concentration gradually increases from the bottom to the top at the beginning, and the germanium concentration remains constant after the germanium concentration reaches the maximum value.
The further improvement is that the maximum value of the germanium concentration in the first germanium-silicon epitaxial layer is 40% -60%.
A further improvement is that the top-layer silicon germanium layer is located in a distribution region of a germanium concentration maximum.
The further improvement is that the thickness of the top germanium-silicon layer is 1 nm-50 nm; in the second step, the hydrogen ion implantation depth is 1 nm-50 nm.
The invention can form the SOI wafer with the high-dielectric-constant dielectric buried layer and the top germanium-silicon layer, the high-dielectric-constant dielectric buried layer can enhance the capacitive coupling effect of the back gate of the device to the channel region, is beneficial to forming the FDSOI device, remarkably improves the control force of the back gate in the FBB and RBB modes, and reduces the power loss of the device; the top germanium-silicon layer can improve the carrier mobility of the PMOS and the performance of the device.
In the invention, the top-layer germanium-silicon layer is obtained by epitaxially growing the first germanium-silicon layer on the first silicon wafer, then injecting hydrogen into the first germanium-silicon layer, and then stripping the first germanium-silicon layer, and the thickness and the flatness of the top-layer germanium-silicon layer can be further optimized by adopting a chemical mechanical polishing process, so that the thickness control process of the top-layer germanium-silicon layer is simple and convenient; in addition, the first germanium-silicon layer adopts the germanium doping concentration which is low to high and keeps the highest value after reaching the highest value, and the topmost germanium-silicon layer can adopt the first germanium-silicon layer with the highest germanium concentration, so that the doping concentration of the topmost germanium-silicon layer can be controlled directly through an epitaxial growth process without adopting a complex germanium condensation process, and the doping concentration control process of the topmost germanium-silicon layer is simple. Therefore, the invention can simplify the forming process of the topmost germanium-silicon layer while combining and forming the high-dielectric constant dielectric buried layer.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a flow chart of a method of fabricating an SOI wafer according to an embodiment of the present invention;
fig. 2A-2F are schematic views of a device structure at each step in a method for fabricating an SOI wafer according to an embodiment of the present invention.
Detailed Description
FIG. 1 is a flow chart of a method for fabricating an SOI wafer according to an embodiment of the present invention; fig. 2A to 2F are schematic views of device structures in steps of a method for fabricating an SOI wafer according to an embodiment of the present invention; the manufacturing method of the SOI wafer comprises the following steps:
step one, as shown in fig. 2A, a first silicon wafer 101 is provided, and a first sige layer 1 is epitaxially grown on a first surface of the first silicon wafer 101, where the first sige layer 1 is used to form a top sige layer 1a, and the thickness of the first sige layer 1 is greater than that of the top sige layer 1 a.
In the embodiment of the present invention, the first silicon wafer 101 is a silicon wafer doped with donor impurities.
And when the first germanium-silicon epitaxial layer is epitaxially grown, the germanium concentration gradually increases from the bottom to the top at the beginning, and the germanium concentration is kept constant after the germanium concentration reaches the maximum value.
Preferably, the maximum value of the germanium concentration in the first germanium-silicon epitaxial layer is 40% -60%. The top germanium-silicon layer 1a formed later is located in the distribution area of the maximum germanium concentration.
Step two, as shown in fig. 2A, a first interfacial layer 2A and a second high dielectric constant layer 2b are sequentially formed on the surface of the first sige layer 1.
In the embodiment of the present invention, the first interfacial layer 2a has a thickness ofIs a very thin silica film.
The first interfacial layer 2a is formed by an atomic layer deposition process.
The k value of the second high dielectric constant layer 2b is higher than that of silicon dioxide.
Preferably, the k value of the second high dielectric constant layer 2b is 5 times or more the k value of silicon dioxide. The material of the second high dielectric constant layer 2b includes hafnium oxynitride, zirconium oxide, or tantalum oxide.
The hydrogen ion implantation depth corresponds to the thickness of the top sige layer 1 a. Preferably, the thickness of the subsequent top germanium-silicon layer 1a is 1 nm-50 nm; the depth of the hydrogen ion implantation is 1 nm-50 nm.
Step three, as shown in fig. 2B, a hydrogen ion implantation is performed from above the second high dielectric constant layer 2B to implant hydrogen impurities into the first silicon germanium layer 1, wherein in fig. 2B, the depth of the hydrogen ion implantation reaches a position shown by a dotted line 4, the hydrogen impurities are located at a position corresponding to the dotted line 4 to a region between the interface of the first silicon germanium layer 1 and the first interface layer 2a, and Si-H-Si bonds, si-H-Ge bonds and Ge-H-Ge bonds are formed in the region doped with the hydrogen impurities.
Step four, as shown in fig. 2C, a second silicon wafer 102 is provided, and a third silicon dioxide layer 2C is formed on the first surface of the second silicon wafer 102.
In the embodiment of the present invention, the third silicon dioxide layer 2c has a thickness ofIs a very thin silica film.
The third silicon dioxide layer 2c is formed by thermal oxidation process, the third silicon dioxide layer 2c is also formed on the second surface and the side surface of the second silicon wafer 102, and the first surface and the second surface of the second silicon wafer 102 are the front and back surfaces of the second silicon wafer 102.
Step five, as shown in fig. 2D, bonding the second high dielectric constant layer 2b and the third silicon dioxide layer 2c to bond the first silicon wafer 101 and the second silicon wafer 102.
In the embodiment of the present invention, the bonding of the first silicon wafer 101 and the second silicon wafer 102 is implemented in a bonding machine.
Step six, as shown in fig. 2E, a lift-off process is performed on the first silicon wafer 101, where the lift-off removes both the first sige layer 1 and the first silicon wafer 101 at the bottom of the hydrogen impurity implantation region. In the embodiment of the present invention, after the Si-H-Si bond, the Si-H-Ge bond, and the Ge-H-Ge bond are torn out in the sixth step, that is, after the position corresponding to the dotted line 4 is exposed, the lift-off process is stopped, and the remaining first sige layer 1 corresponds to the top sige layer shown by the reference sign 1a in fig. 2E; and then annealing treatment is carried out.
As shown in fig. 2F, after the annealing treatment is completed, a chemical mechanical polishing process is further performed to polish the top sige layer 1a and adjust the thickness of the top sige layer 1a to a desired thickness and obtain a desired flatness.
The first germanium-silicon layer 1 is reserved as the top germanium-silicon layer 1a, the first interface layer 2a, the second high dielectric constant layer 2b and the third silicon dioxide layer 2c are overlapped to form a high dielectric constant medium buried layer, and the second silicon wafer 102 is used as bulk silicon.
The top silicon germanium layer 1a is used to form an FDSOI device that includes a gate structure, a source region, a drain region, and a channel region.
The grid structure is formed on the surface of the top-layer germanium-silicon layer 1a, the source region and the drain region are formed in the top-layer germanium-silicon layer 1a on two sides of the grid structure in a self-aligned mode, the channel region is composed of the top-layer germanium-silicon layer 1a located between the source region and the drain region, and the thickness of the top-layer germanium-silicon layer 1a is enough that the channel region at the bottom of the inversion layer is completely consumed when the FDSOI device is conducted.
The bulk silicon is connected with a back gate electrode, and the back gate electrode controls the channel region through the high-dielectric constant buried dielectric layer and adjusts the threshold voltage of the FDSOI device.
The embodiment of the invention can form the SOI wafer with the high-dielectric-constant dielectric buried layer and the top germanium-silicon layer 1a, and the high-dielectric-constant dielectric buried layer can enhance the capacitive coupling effect of the back gate of the device to the channel region, thereby being beneficial to forming an FDSOI device, remarkably improving the control force of the back gate in the FBB and RBB modes and reducing the power loss of the device; the top germanium-silicon layer 1a can improve the carrier mobility of the PMOS and the performance of the device.
In the embodiment of the invention, the top-layer germanium-silicon layer 1a is obtained by injecting hydrogen into the first germanium-silicon layer 1 after epitaxially growing the first germanium-silicon layer 1 on the first silicon wafer 101 and then stripping the first germanium-silicon layer 1, and the thickness and the flatness of the top-layer germanium-silicon layer 1a can be further optimized by adopting a chemical mechanical polishing process, so that the thickness control process of the top-layer germanium-silicon layer 1a is simple and convenient; in addition, the first sige layer 1 according to the embodiment of the present invention has a ge doping concentration that is kept at a maximum value from low to high and reaches the maximum value, and the topmost sige layer 1a according to the embodiment of the present invention can use the first sige layer 1 having the highest ge concentration, so that the control of the doping concentration of the topmost sige layer 1a according to the embodiment of the present invention is directly controllable by an epitaxial growth process, and a complicated ge condensation process is not required, so that the control process of the doping concentration of the topmost sige layer 1a according to the embodiment of the present invention is simple. Therefore, the embodiment of the invention can simplify the forming process of the topmost germanium-silicon layer 1a while combining and forming the high-dielectric-constant dielectric buried layer.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (15)

1. The manufacturing method of the SOI wafer is characterized by comprising the following steps:
providing a first silicon wafer, and epitaxially growing a first germanium-silicon layer on a first surface of the first silicon wafer, wherein the first germanium-silicon layer is used for forming a top germanium-silicon layer, and the thickness of the first germanium-silicon layer is larger than that of the top germanium-silicon layer;
sequentially forming a first interface layer and a second high dielectric constant layer on the surface of the first germanium-silicon layer;
the k value of the second high dielectric constant layer is higher than that of silicon dioxide;
step three, implanting hydrogen ions from above the second high dielectric constant layer to implant hydrogen impurities into the first germanium-silicon layer;
step four, providing a second silicon wafer, and forming a third silicon dioxide layer on the first surface of the second silicon wafer;
bonding the second high dielectric constant layer and the third silicon dioxide layer to bond the first silicon wafer and the second silicon wafer;
step six, stripping the first silicon wafer, wherein the stripping removes the first germanium-silicon layer and the first silicon wafer which are positioned at the bottom of the hydrogen impurity injection region, the first germanium-silicon layer is used as the top germanium-silicon layer, the first interface layer, the second high dielectric constant layer and the third silicon dioxide are stacked to form a high dielectric constant medium buried layer, and the second silicon wafer is used as bulk silicon;
in the first step, when the first germanium-silicon epitaxial layer is epitaxially grown, the germanium concentration gradually increases from the bottom to the top at the beginning, and the germanium concentration is kept constant after the germanium concentration reaches the maximum value;
the top-layer germanium-silicon layer is positioned in a distribution area of the maximum germanium concentration;
the thickness of the top germanium-silicon layer is 1 nm-50 nm; in the second step, the hydrogen ion implantation depth is 1 nm-50 nm.
2. The method for fabricating an SOI wafer as defined in claim 1, further comprising: the first silicon wafer is a donor impurity doped silicon wafer.
3. The method for fabricating an SOI wafer as defined in claim 1, further comprising: the first interface layer has a thickness ofIs a very thin silica film.
4. The method of fabricating an SOI wafer as defined in claim 3, further comprising: the first interface layer is formed by an atomic layer deposition process.
5. The method for fabricating an SOI wafer as defined in claim 1, further comprising: the third silicon dioxide layer has a thickness ofIs a very thin silica film.
6. The method for manufacturing an SOI wafer according to claim 5, wherein: the third silicon dioxide layer is formed by adopting a thermal oxidation process, and is also formed on the second surface and the side surface of the second silicon wafer, wherein the first surface and the second surface of the second silicon wafer are the front surface and the back surface of the second silicon wafer.
7. The method for fabricating an SOI wafer as defined in claim 1, further comprising: the k value of the second high dielectric constant layer is more than 5 times of the k value of silicon dioxide.
8. The method for fabricating an SOI wafer as defined in claim 1, further comprising: the material of the second high dielectric constant layer comprises hafnium oxynitride, zirconium oxide or tantalum oxide.
9. The method for fabricating an SOI wafer as defined in claim 1, further comprising: and in the second step, the hydrogen ion implantation depth corresponds to the thickness of the top germanium-silicon layer.
10. The method for fabricating an SOI wafer as defined in claim 9, further comprising: and step six, tearing Si-H-Si bonds, si-H-Ge bonds and Ge-H-Ge bonds, stopping the stripping process, and then carrying out annealing treatment.
11. The method of fabricating an SOI wafer as defined in claim 10, further comprising: and step six, polishing the top-layer germanium-silicon layer by a chemical mechanical polishing process after the annealing treatment is completed, and adjusting the thickness of the top-layer germanium-silicon layer to the required thickness.
12. The method for fabricating an SOI wafer as defined in claim 1, further comprising: and fifthly, bonding the first silicon wafer and the second silicon wafer in a bonding machine.
13. The method for fabricating an SOI wafer as defined in claim 1, further comprising: the top germanium-silicon layer is used for forming an FDSOI device, and the FDSOI device comprises a grid structure, a source region, a drain region and a channel region;
the grid structure is formed on the surface of the top-layer germanium-silicon layer, the source region and the drain region are formed in the top-layer germanium-silicon layer on two sides of the grid structure in a self-aligned mode, the channel region is composed of the top-layer germanium-silicon layer located between the source region and the drain region, and the thickness of the top-layer germanium-silicon layer is enough that the channel region at the bottom of the inversion layer is completely consumed when the FDSOI device is conducted.
14. The method for fabricating an SOI wafer as defined in claim 13, further comprising: the bulk silicon is connected with a back gate electrode, and the back gate electrode controls the channel region through the high-dielectric constant buried dielectric layer and adjusts the threshold voltage of the FDSOI device.
15. The method for fabricating an SOI wafer as defined in claim 1, further comprising: the maximum value of the germanium concentration in the first germanium-silicon epitaxial layer is 40% -60%.
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CN102738060B (en) * 2012-07-02 2014-04-23 中国科学院上海微系统与信息技术研究所 Preparation method of gate oxide integrity (GOI) wafer structure

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