CN111504482A - Single photon detection device and method capable of restraining back pulse - Google Patents
Single photon detection device and method capable of restraining back pulse Download PDFInfo
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Abstract
The invention discloses a single photon detection device and method capable of restraining a rear pulse. The single photon detection device capable of restraining the rear pulse comprises a synchronous light detection unit, a phase-locked loop, a clock selection unit, a clock distribution unit, a first logic unit, a second logic unit, a single photon detector, a coincidence control unit and a selection output unit. The method for inhibiting the rear pulse comprises the steps of recovering a clock signal by a system with a period of T, forming a detector gate control signal with a period difference of T/2 and a rear pulse release gate control signal, opening the rear pulse release gate control and releasing the rear pulse when a single-photon detector detects single-photon avalanche and closes the T/2 after gate control, thereby realizing the inhibition of the rear pulse and improving the detection efficiency of the single-photon detector.
Description
Technical Field
The invention relates to the technical field of optical communication, in particular to a single photon detection device and method capable of inhibiting rear pulses.
Background
The single-photon detector is a high-sensitivity detection device for detecting weak light signals, and is widely applied to the fields of Quantum Key Distribution (QKD), optical fiber sensing, optical fiber communication, laser radar, high-energy physics, semiconductor device characteristic analysis, biological imaging and the like. In the existing single photon detector, an Avalanche Photo Diode (APD) is commonly used, and has the characteristics of high detection efficiency, exquisite structure, high reliability, low energy consumption and the like.
Key performance parameters of Avalanche Photodiodes (APDs) include detection efficiency, post-pulse probability, dark count probability, etc. The back pulse refers to the re-avalanche caused by the previous avalanche after the Avalanche Photodiode (APD) is turned on. The back pulse is caused by Avalanche Photodiode (APD) material defects. After a single photon incident Avalanche Photodiode (APD) is avalanche, the single photon detector gate is closed. However, Avalanche Photodiode (APD) lattice defects trap carriers and release them slowly. After the Avalanche Photodiode (APD) is turned on for the second time to enter the geiger mode, avalanche is triggered again. The back pulse is caused by the re-release of carriers trapped by Avalanche Photodiodes (APDs) when no single photon reaches the single photon detector, and is a pseudo-avalanche count. The back pulse probability is the ratio of the total back pulse count to the single photon count after single photon counting. The dark count is a count of noise signals detected without single photon incidence due to factors such as material characteristics of Avalanche Photodiodes (APDs), doping processes, and thermal excitation effects. The dark count rate is defined as the ratio of the count rate output by the detector after the laser light source is turned off to the repetition frequency of the gate signal.
Both the back pulse and the dark count affect the detection efficiency of single photon detectors. In the prior art, a general method for suppressing the dark count is to provide a low temperature environment for the Avalanche Photodiode (APD), for example, the Avalanche Photodiode (APD) is operated in the low temperature environment of minus 40 degrees or even lower, so as to effectively suppress the dark count. However, the low temperature environment increases the cost of the single photon detector and also increases the probability of pulse after the single photon detector. This is a technical problem to be solved in the art.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a single photon detection method capable of inhibiting a back pulse, which comprises the following steps: receiving a detector gate control signal with a period of T at the single-photon detector, receiving a single photon, generating avalanche, forming a single-photon avalanche signal, and closing the gate control of the single-photon detector; and after the single photon detector is gated off by T/2, receiving a back pulse release gate control signal with the period of T, opening the back pulse release gate control to form a back pulse avalanche signal, releasing the back pulse, and closing the back pulse gate control.
In the method, the synchronous light is further received at the synchronous light detection unit to form a synchronous electric signal.
According to the method, the phase-locked loop further receives the synchronous electric signal to perform system clock recovery to form a system recovery clock signal with the period of T, the phase-locked loop forms a detector gated clock signal with the period of T and a back pulse release gated clock signal according to the system recovery clock signal, and the phase difference between the back pulse release gated clock signal and the detector gated clock signal is T/2.
The method as described above, further receiving the detector gate clock signal and the post-pulse release gate clock signal at a clock selection unit, and outputting the post-pulse release gate clock signal T/2 after outputting the detector gate clock signal by the clock selection unit.
The method as described above, further receiving the detector gated clock signal at a clock distribution unit, and distributing to form a first detector gated clock distribution signal and a second detector gated clock distribution signal with a period of T and without time difference.
The method as described above, further comprising receiving the first detector gated clock distribution signal at a first logic unit, and performing a logic operation to form the detector gated signal; and receiving the gated clock distribution signal of the second detector at a second logic unit, and forming a detector coincidence gate signal through logic operation.
The method further comprises the steps that a coincidence control unit receives the single photon avalanche signal and the detector coincidence gate signal and outputs a single photon detection coincidence signal; and the selection output unit receives the single photon detection coincidence signal and outputs a single photon detection pulse signal.
The method as described above, further receiving the post-pulse release gated clock signal at the clock distribution unit, and distributing to form a first post-pulse release gated clock distribution signal and a second post-pulse release gated clock distribution signal with a period of T and no time difference.
The method as described above, further receiving the first back pulse release gated clock distribution signal at the first logic unit, and performing a logic operation to form the back pulse release gated signal; and receiving the second rear pulse release gated clock distribution signal at the second logic unit, and forming a rear pulse release coincidence gate signal through logic operation.
The method as described above, further receiving the post-pulse avalanche signal and the post-pulse release coincidence gate signal at the coincidence control unit, and outputting a post-pulse release coincidence signal; and the selection output unit receives the rear pulse release coincidence signal and outputs a rear pulse release signal.
In another aspect of the present invention, a single photon detecting apparatus capable of suppressing a post pulse is provided, including: a synchronous light detection unit configured to receive synchronous light to form a synchronous electrical signal; a phase-locked loop configured to receive the synchronous electrical signal, form a system recovery clock signal with a period of T, further form a detector gated clock signal with a period of T and a post-pulse release gated clock signal according to the system recovery clock signal, wherein a difference between the post-pulse release gated clock signal and the detector gated clock signal is T/2 in period; a clock selection unit configured to receive the detector gated clock signal, the post-pulse release gated clock signal, the clock selection unit outputting the post-pulse release gated clock signal T/2 after outputting the detector gated clock signal; the clock distribution unit is configured to receive the detector gated clock signals and is distributed to form a first detector gated clock distribution signal and a second detector gated clock distribution signal which have a period of T and have no time difference; the first and second back pulse release gated clock distribution signals are distributed to form a first and second back pulse release gated clock distribution signal with a period of T and no time difference; a first logic unit configured to receive the first detector gated clock distribution signal, the first logic unit logically operated to form the detector gated signal; receiving the first back pulse release gating clock distribution signal, and forming the back pulse release gating signal through logic operation; a second logic unit configured to receive the second detector gated clock distribution signal, and to form a detector coincidence gate signal by a logic operation; receiving the second post-pulse release gated clock distribution signal, and forming a post-pulse release coincidence gate signal through logic operation; the single-photon detector is configured to receive a detector gate control signal with a period T, receive a single photon, generate avalanche, form a single-photon avalanche signal and close the gate control of the single-photon detector; after the single photon detector is gated off by T/2, receiving a back pulse release gate control signal with the period of T, opening the back pulse release gate control to form a back pulse avalanche signal, releasing a back pulse, and closing the back pulse gate control; a coincidence control unit configured to receive the single photon avalanche signal and the detector coincidence gate signal, and output a single photon detection coincidence signal; receiving the rear pulse avalanche signal and the rear pulse release gate signal, and outputting a rear pulse release coincidence signal; a selection output unit configured to receive the single photon detection coincidence signal and output a single photon detection pulse signal; and receiving the rear pulse release coincidence signal and outputting a rear pulse release signal.
Compared with the prior art, the invention obviously shortens the time occupied by the dead time of the single-photon detector and obviously improves the detection efficiency of the single-photon detector. In addition, the invention well inhibits the back pulse of the single photon detector, and can further reduce the environmental temperature of the single photon detector compared with the prior art, thereby effectively reducing the occurrence probability of dark counting. In summary, compared with the prior art, the technical scheme of the invention remarkably reduces the back pulse probability and the dark counting probability of the single-photon detector and greatly improves the detection efficiency of the single-photon detector.
Drawings
FIGS. 1a and 1b show a schematic diagram of detector gating operation and a signal timing diagram of a single photon detector according to the present invention;
FIGS. 2a and 2b are schematic diagrams showing the operation of post-pulse release gating of a single photon detector according to the present invention and signal timing diagrams;
figure 3 shows a schematic structural view of an exemplary embodiment of a single photon detection arrangement according to the present invention;
FIG. 4 shows a clock signal timing diagram for the embodiment shown in FIG. 3;
figure 5 shows a schematic structural view of another exemplary embodiment of a single photon detection arrangement according to the present invention;
FIG. 6 shows a clock signal timing diagram for the embodiment shown in FIG. 5;
FIG. 7 shows a schematic view of a detector gating operation process of the single photon detection device of the present invention;
FIG. 8 is a signal timing diagram showing detector gating operation of the single photon detection device of the present invention;
FIG. 9 is a schematic diagram of a post-pulse release gated operation of the present invention;
FIG. 10 is a signal timing diagram illustrating a post-pulse release gated operation of the present invention;
fig. 11 shows a schematic diagram of the technical effect according to the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application.
The working process of the single photon detector in the single photon detection device capable of inhibiting the back pulse can be divided into a detector gate control working process and a back pulse release gate control working process. In order to more accurately describe the technical scheme of the invention, the gating working process of the detector and the gating working process of the post-pulse release need to be respectively explained and described.
Fig. 1a and 1b show a schematic diagram of the detector gating operation of the single photon detector according to the invention and a signal timing diagram. As shown in fig. 1b, the first row is the detector gating signal 4013, the second row is a single photon, and the third row is the single photon avalanche signal 501.
In some embodiments, the single photon detector 101 shown in FIG. 1a can receive and detect optical signals and obtain corresponding electrical signals, and the single photon detector 101 can be a PN junction type photodetector, a PIN type photodetector, an Avalanche Photodiode (APD) detector, or a pull-through avalanche photodiode (RAPD) detector. The single photon detector 101 is a single photon gated detector, preferably the single photon detector 101 may be an Avalanche Photodiode (APD) detector. The cycle of the detector gate control signal 4013 shown in the first row of fig. 1b is T, when the system configuration single photon detector 101 receives the detector gate control signal 4013, the gate of the single photon detector 101 is opened, at this time, if the single photon detector 101 detects a single photon shown in the second row of fig. 1b, avalanche occurs, when the single photon avalanche signal intensity reaches a preset threshold value of the system, the gate of the single photon detector 101 is closed, the avalanche process of the single photon detector 101 is quenched, and the avalanche single photon signal 501 shown in the third row of fig. 1b is output.
When the single photon detector 101 receives the detector gate control signal 4013 shown in the first row of fig. 1b, the gate of the single photon detector 101 is opened, and if the single photon detector 101 does not detect a single photon shown in the second row of fig. 1b, no avalanche process occurs, no single photon avalanche signal is output, and after the gate opening time of the single photon detector 101 reaches the time specified by the system, the gate of the single photon detector 101 is closed.
Fig. 2a and 2b are schematic diagrams of the post-pulse release gating operation process and signal timing diagram of the single photon detector according to the invention. As shown in fig. 2b, the first post-row pulse releases the gating signal 4033 and the second post-row pulse avalanche signal 601.
In some embodiments, the single photon detector 101 shown in figure 2a is gated off after completion of a single photon detection avalanche, and no single photon is received and detected. The back pulse release gating signal 4033 as shown in the first row of figure 2b has the same period T as the detector gating signal 4013. After the gating of the single photon detector 101 is closed, after a half T of time elapses, the single photon detector 101 may receive the post-pulse release gating signal 4033, open the post-pulse release gating to release carriers captured by the single photon detector 101, to form a post-pulse release avalanche, and when the post-pulse release avalanche signal reaches a preset threshold of the system, the post-pulse release gating is closed, the post-pulse release avalanche is quenched, and a post-pulse avalanche signal is output, that is, the post-pulse avalanche signal 601 shown in the second row of fig. 2b is output. The single photon detector of the invention also releases a certain number of dark counts during the process of pulse after release.
Figure 3 shows a schematic structural view of an exemplary embodiment of a single photon detection arrangement according to the present invention. As shown in fig. 3, the single photon detection apparatus of the present invention may include a synchronous optical detection unit 103, a phase locked loop 201, and a clock selection unit 203.
Fig. 4 shows a clock signal timing diagram of the embodiment shown in fig. 3. As shown in fig. 4, the first behavior system recovers the clock signal, the second behavior detector gates the clock signal 401, and the third behavior is followed by a pulse release gated clock signal 403.
In some embodiments, the synchronization light detection unit 103 as shown in fig. 3 may receive and detect the synchronization light, convert the synchronization light into a synchronization electrical signal, and output the synchronization electrical signal. The synchronization light detection unit 103 may be a PN junction type photodetector, a PIN type photodetector, an Avalanche Photodiode (APD) detector, or a pull-through type avalanche photodiode (RAPD) detector. The synchronous light can be a low-frequency signal, can be a narrow pulse with the duty ratio less than or equal to 1 percent, and further can be a narrow pulse with the duty ratio less than or equal to 1 per thousand. The synchronous electrical signal detected by the synchronous light detection unit 103 has the same signal characteristics as the synchronous light, such as period, pulse width, duty ratio, and frequency.
In some embodiments, the phase-locked loop 201 may receive the synchronous electrical signal output by the synchronous optical detection unit 103, and recover the system clock, resulting in the system recovered clock signal shown in the first row of fig. 4. The frequency of the system recovered clock signal may be 100MHz to 1GHz, preferably 125 MHz. The period of the system recovery clock signal is T, and when the frequency of the system recovery clock signal is preferably 125MHz, the period T is 8 ns. The duty cycle of the system recovered clock signal is 50%. The phase-locked loop 201 generates two paths of signals with consistent signal characteristics, such as frequency, duty ratio, period, and the like, according to the obtained system recovery clock signal, which are the detector gate control clock signal 401 shown in the second row of fig. 4 and the back pulse release gate control clock signal 403 shown in the third row of fig. 4, and respectively outputs the detector gate control clock signal 401 and the back pulse release gate control clock signal 403. The frequency and period of the detector gated clock signal 401 and the post-pulse release gated clock signal 403 are the same as the system recovery clock signal. The back pulse releases the clock-gated signal 403 by a half T in period with respect to the detector clock-gated 401.
In some embodiments, the clock selection unit 203 may receive the detector gated clock signal 401 and the post-pulse release gated clock signal 403 respectively output by the phase locked loop 201, and select one of the detector gated clock signal 401 and the post-pulse release gated clock signal 403 for output according to the system operation requirement. The clock selection unit 203 can make the clock signal output each time only be one of the detector gated clock signal 401 or the post-pulse release gated clock signal 403, which can effectively improve the operation accuracy of the system. And at the output time, after the detector gate clock signal 401 is output, after the time passes by half T, the post-pulse release gate clock signal 403 is output.
Figure 5 shows a schematic structural view of another exemplary embodiment of a single photon detection arrangement according to the present invention. As shown in fig. 5, the single photon detection apparatus of the present embodiment may include a synchronous light detection unit 103, a phase locked loop 201, a delay unit 211, and a clock selection unit 203.
Fig. 6 shows a clock signal timing diagram of the embodiment shown in fig. 5. As shown in fig. 6, the first row of the system recovers the clock signal, the second row is the detector gated clock signal 401, the third row is the detector gated clock signal 401a, and the fourth row is the post-pulse release gated clock signal 403.
The device of the embodiment of fig. 5 has similar functions to the device of the embodiment of fig. 3 with similar components. In this embodiment, the phase-locked loop 201 may receive the synchronous electrical signal output by the synchronous optical detection unit 103, and recover the system clock, so as to obtain the system recovered clock signal shown in the first row of fig. 6. The phase-locked loop 201 generates two signals with consistent signal characteristics, such as frequency, duty ratio, period, etc., according to the obtained system recovered clock signal, and the two signals are respectively the detector gated clock signal 401 shown in the second row of fig. 6 and the detector gated clock signal 401a shown in the third row of fig. 6, and are respectively output, and the output does not have a time difference. The detector gated clock signal 401 is directly input to the clock selection unit 203. The detector gated clock signal 401a is input to the delay unit 211, and the delay unit 211 delays the detector gated clock signal 401a by one-half T to form a post-pulse release gated clock signal 403 shown in the fourth row of fig. 6, and outputs the post-pulse release gated clock signal to the clock selection unit 203. The frequency and period of the detector gated clock signal 401 and the post-pulse release gated clock signal 403 are the same as the system recovery clock signal. The back pulse releases the gated clock signal 403 by one-half of the system recovery clock signal period, i.e., T/2, in time relative to the detector gated clock 401.
The working process of the single photon detection device capable of inhibiting the back pulse can be divided into a detector gate control working process and a back pulse release gate control working process.
The following describes the gate control operation process of the single photon detector of the present invention with reference to the schematic diagram of the gate control operation process of the detector of the single photon detector of the present invention shown in fig. 7 and the signal timing diagram of the gate control operation process of the detector of the single photon detector of the present invention shown in fig. 8. As shown in fig. 8, the first line is a detector gated clock signal 401, the second line is a first detector gated clock distribution signal 4011, the third line is a second detector gated clock distribution signal 4015, the fourth line is a detector gated signal 4013, the fifth line is a single photon, the sixth line is a single photon avalanche signal 501, the seventh line is a detector coincidence gate signal 4017, the eighth line is a single photon detection coincidence signal 503, and the ninth line is a single photon detection pulse signal 505.
During the detector gating operation of the present invention, as shown in fig. 7, the clock selection unit 203 selects and outputs the detector gating clock signal 401 as shown in the first row of fig. 8. As shown in fig. 7, the clock distribution unit 205 may include one signal input port, may include two or more signal output ports, and may output the input electrical signal through different output ports after being distributed according to system requirements. Preferably, the clock distribution unit 205 may be a clock distributor. The clock distribution unit 205 may receive the detector gated clock signal 401 as shown in the first row of fig. 8, and output a first detector gated clock distribution signal 4011 as shown in the second row of fig. 8 and a second detector clock distribution signal 4015 as shown in the third row of fig. 8 after distribution, where the first detector gated clock distribution signal 4011 and the second detector clock distribution signal 4015 have the same signal characteristics as the detector gated clock signal 401, such as frequency, period, duty cycle, and pulse width. The first and second detector clock distribution signals 4011 and 4015 have no time difference.
In some embodiments, the first logic unit 301 shown in fig. 7 is a circuit capable of performing a logic operation, and may be an and circuit, an or circuit, an nor circuit, an xor circuit, or an xnor circuit. Preferably, the first logic unit 301 may be a logic chip. The second logic unit 303 has a similar structure and function as the first logic unit 301. Preferably, the first logic unit 301 and the second logic unit 303 may be an or gate circuit. The first logic unit 301 may receive the first detector gate clock distribution signal 4011, and output a detector gate signal 4013 as shown in the fourth row of fig. 8 after logical operation of an or gate. The detector gate signal 4013 has the same signal characteristics of period, frequency, etc. as the first detector gate clock distribution signal 4011.
In some embodiments, a single photon detector 101 as shown in figure 7 can receive and detect optical signals and derive corresponding electrical signals. When the single photon detector 101 receives a detector gate control signal 4013 shown in the fourth row of fig. 8 through system configuration, the gate of the single photon detector 101 is opened, at this time, avalanche occurs if the single photon detector 101 detects a single photon shown in the fifth row of fig. 8, when the single photon avalanche signal intensity reaches a preset threshold value of the system, the gate of the single photon detector 101 is closed, the avalanche process of the single photon detector 101 is quenched, and the single photon avalanche signal 501 shown in the sixth row of fig. 8 is output. When the single photon detector 101 receives the detector gate control signal 4013 shown in the fourth row of fig. 8, the gate of the single photon detector 101 is opened, at this time, if the single photon detector 101 does not detect a single photon shown in the fifth row of fig. 8, no avalanche process occurs, no single photon avalanche signal is output, and after the gate opening time of the single photon detector 101 reaches the time specified by the system, the gate of the single photon detector 101 is closed.
In some embodiments, the second logic unit 303 as shown in fig. 7 may receive the second detector gated clock distribution signal 4015, and output the detector coincidence gate signal 4017 as shown in the seventh row of fig. 8 after the or gate logic operation. The detector coincidence gate signal 4017 has the same signal characteristics of period, frequency, etc. as the second detector gated clock distribution signal 4015.
In some embodiments, the coincidence control unit 207 shown in fig. 7 may receive the single photon avalanche signal 501 shown in the sixth line of fig. 8 and may receive the detector coincidence gating signal 4017 shown in the seventh line of fig. 8. The coincidence control unit 207 is a logic circuit capable of performing coincidence control, and may be an and gate circuit, an or gate circuit, or a nor gate circuit, an exclusive or gate circuit, or an exclusive or gate circuit. Preferably, the coincidence control unit 207 may be an and gate circuit. After receiving the single photon detection electrical signal 501 and the detector coincidence gate control signal 4017, the coincidence control unit 207 may perform coincidence control by performing logic operation, preferably an and gate operation, to remove a noise signal, and output a single photon detection coincidence signal 503, which meets system requirements and is shown in the eighth row of fig. 8.
In some embodiments, the selection output unit 209 shown in fig. 7 may have two signal output ports, where one signal output port is a single photon detection pulse signal output port, the other signal output port is a post-pulse release signal output port, and the selection output unit 209 may select one signal output port to output a signal according to a system requirement. The selection output unit 209 can receive the single photon detection coincidence signal 503 and output a single photon detection pulse signal 505 shown in the ninth row of fig. 8 according to the system requirements.
The following describes the post-pulse release gating operation of the present invention with reference to the schematic diagram of the post-pulse release gating operation apparatus of the present invention shown in fig. 9 and the schematic diagram of the signal timing of the post-pulse release gating operation of the present invention shown in fig. 10. As shown in fig. 10, the first post-row pulse release gated clock signal 403, the second row the first post-row pulse release gated clock distribution signal 4031, the third row the second post-row pulse release gated clock distribution signal 4035, the fourth post-row pulse release gated signal 4033, the fifth post-row pulse avalanche signal 601, the sixth post-row pulse release coincidence gate signal 4037, the seventh post-row pulse release coincidence signal 603, and the eighth post-row pulse release signal 605.
In the post-pulse release gating operation of the present invention, as shown in fig. 9, the clock selection unit 203 selects and outputs the post-pulse release gating clock signal 403 shown in the first row of fig. 10. As shown in fig. 9, the clock distribution unit 205 may include one signal input port, may include two or more signal output ports, and may output the input electrical signal through different output ports after being distributed according to system requirements. Preferably, the clock distribution unit 205 may be a clock distributor. The clock distribution unit 205 may receive the post-pulse release-gated clock signal 403 shown in the first row of fig. 10, and output the first post-pulse release-gated clock distribution signal 4031 shown in the second row of fig. 10, the second post-pulse release-gated clock distribution signal 4035 shown in the third row of fig. 10, and the first post-pulse release-gated clock distribution signal 4031 and the second post-pulse release-gated clock distribution signal 4035 have the same signal characteristics as the post-pulse release-gated clock signal 403, such as frequency, period, duty cycle, and pulse width. The first rear pulse release gated clock distribution signal 4031 and the second rear pulse release gated clock distribution signal 4035 do not have a time difference.
In some embodiments, the first logic unit 301 shown in fig. 9 is a circuit capable of performing a logic operation, and may be an and circuit, an or circuit, an nor circuit, an xor circuit, or an xnor circuit. Preferably, the first logic unit 301 may be a logic chip. The second logic unit 303 has a similar structure and function as the first logic unit 301. Preferably, the first logic unit 301 and the second logic unit 303 may be an or gate circuit. The first logic unit 301 may receive the first post-pulse release gating clock distribution signal 4031, and output the post-pulse release gating signal 4033 as shown in the fourth row of fig. 6 after the logical operation of the or gate. The back-pulse release gated signal 4033 has the same signal characteristics of period, frequency, etc. as the first back-pulse release gated clock distribution signal 4031.
In some embodiments, the single photon detector 101 shown in figure 9 is gated off after completion of a single photon detection avalanche, and no single photon is received and detected. After the gating of the single photon detector 101 is closed and a clock signal cycle is recovered by one half of the system, the single photon detector 101 may receive the post-pulse release gating signal 4033, open the post-pulse release gating to release carriers captured by the single photon detector 101 to form a post-pulse release avalanche, and when the post-pulse release avalanche signal reaches a preset threshold of the system, the post-pulse release gating is closed, the post-pulse release avalanche is quenched, and a post-pulse avalanche signal 601 shown in the fifth row of fig. 10 is output.
In some embodiments, the second logic unit 303 shown in fig. 9 may receive the second post-pulse release gated clock distribution signal 4035 shown in the third row of fig. 10, and may output a post-pulse release coincidence gate signal 4037 shown in the sixth row of fig. 10 after the or gate logic operation, wherein the post-pulse release coincidence gate signal 4037 and the second post-pulse release gated clock distribution signal 4035 have the same signal characteristics of period, frequency, and the like. The coincidence control unit 207 shown in fig. 9 may receive the post-pulse avalanche signal 601 shown in the fifth row of fig. 10 and may receive the post-pulse release coincidence gate signal 4037 shown in the sixth row of fig. 10. The coincidence control unit 207 is a logic circuit capable of performing coincidence control, and may be an and gate circuit, an or gate circuit, or a nor gate circuit, an exclusive or gate circuit, or an exclusive or gate circuit. Preferably, the coincidence control unit 207 may be an and gate circuit. After receiving the post-pulse avalanche signal 601 and the post-pulse release coincidence gate signal 4037, the coincidence control unit 207 may perform coincidence control by performing logic operation, preferably by performing and gate operation, remove a noise signal, and output a post-pulse release coincidence signal 603 shown in the seventh row of fig. 10, which meets the system requirements.
In some embodiments, as shown in fig. 9, the selection output unit 209 may have two signal output ports, where one signal output port is a single photon detection pulse signal output port, the other signal output port is a post-pulse release signal output port, and the selection output unit 209 may select one signal output port to output a signal according to a system requirement. The selection output unit 209 may receive the post-pulse release compliance signal 603 and output a post-pulse release signal 605, shown in the eighth row of fig. 10, that is compliant with the system requirements. The single photon detection device of the invention also releases a certain number of dark counts in the process of pulse after release.
Fig. 11 shows a schematic diagram of the technical effect according to the invention. Fig. 11 is intended to schematically show the technical effect achieved by the technical solution of the present invention by selecting key information, not all information, of the technical solution of the present invention. As shown in fig. 11, the system is divided into three parts from top to bottom by a dotted line, the first part schematically illustrates the prior art, the second part schematically illustrates single photon detection, and the third part schematically illustrates post-pulse suppression.
The first row of the first part of figure 11 is the prior art single photon, the second row is the prior art single photon detector gating signal, the third row is the prior art single photon avalanche signal and the fourth row is the prior art dead time control. As shown in the first part of fig. 11, in the prior art, after detecting the single photon occurrence of avalanche, the single photon detector gates are turned off immediately after the avalanche signal reaches a preset threshold value of the system, and after waiting time t, the gates are turned on again, and this waiting time t is generally called as the dead time t of the single photon detector. The main purpose of configuring the dead time t for the single-photon detector is to suppress the back pulse, but the release of the carriers captured by the single-photon detector requires the dead time t of the single-photon detector to be long enough, so that the single-photon detector cannot detect the single photon during the dead time t.
The detector gate signal 4013 shown in the third row of the second part of fig. 11 and the post-pulse release gate signal 4033 shown in the first row of the third part of fig. 11 have the same signal characteristics of period, frequency, etc., but the post-pulse release gate signal 4033 is delayed in time by T/2 with respect to the detector gate signal 4013. After the single photon detector 101 completes one single photon detection avalanche, the gate of the single photon detector 101 is closed, and the single photon is no longer received and detected. After the gating of the single photon detector 101 is closed, the single photon detector 101 can receive the back pulse release gating signal 4033 through T/2, the back pulse release gating is opened to form back pulse release avalanches, when the back pulse release avalanches signal reaches a preset threshold value of the system, the back pulse release gating is closed, the back pulse release avalanches are quenched, and a back pulse release signal 605 shown in the third row of the third part is output. Compared with the technical scheme in the prior art, the technical scheme of the invention can greatly shorten the gating dead time of the single photon detector and reduce the influence of the post-pulse release process on the detection efficiency of the single photon detector 101 by the technical means of actively releasing the post-pulse and outputting the post-pulse. Therefore, compared with the prior art, the technical scheme of the invention obviously shortens the time occupied by the dead time of the single-photon detector and obviously improves the detection efficiency of the single-photon detector. The single photon detection device of the invention also releases a certain number of dark counts in the process of pulse after release. In addition, the invention well inhibits the back pulse of the single photon detector, and can further reduce the environmental temperature of the single photon detector compared with the prior art, thereby effectively reducing the occurrence probability of dark counting. In summary, compared with the prior art, the technical scheme of the invention remarkably reduces the back pulse probability and the dark counting probability of the single-photon detector, greatly improves the detection efficiency of the single-photon detector and remarkably reduces the signal-to-noise ratio.
The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the scope of the present invention, and therefore, all equivalent technical solutions should fall within the scope of the present invention.
Claims (11)
1. A single photon detection method capable of restraining a back pulse comprises the following steps:
receiving a detector gate control signal with a period of T at the single-photon detector, receiving a single photon, generating avalanche, forming a single-photon avalanche signal, and closing the gate control of the single-photon detector;
and after the single photon detector is gated off by T/2, receiving a back pulse release gate control signal with the period of T, opening the back pulse release gate control to form a back pulse avalanche signal, releasing the back pulse, and closing the back pulse gate control.
2. The method of claim 1, further comprising receiving the synchronization light at a synchronization light detection unit to form a synchronization electrical signal.
3. The method of claim 2, further comprising receiving said synchronization electrical signal at a phase locked loop for system clock recovery to form a system recovered clock signal having a period T, said phase locked loop forming a detector gated clock signal having a period T and a post-pulse release gated clock signal based on said system recovered clock signal, said post-pulse release gated clock signal having a period T/2 different from said detector gated clock signal.
4. The method of claim 3, further comprising receiving the detector gated clock signal and the post-pulse release gated clock signal at a clock select unit, the clock select unit outputting the post-pulse release gated clock signal T/2 after outputting the detector gated clock signal.
5. The method of claim 4, further comprising receiving the detector gated clock signals at a clock distribution unit, distributed to form a first detector gated clock distribution signal having a period T and no time difference, and a second detector gated clock distribution signal.
6. The method of claim 5, further comprising receiving, at a first logic unit, the first detector gated clock distribution signal, logically operating to form the detector gated signal; and receiving the gated clock distribution signal of the second detector at a second logic unit, and forming a detector coincidence gate signal through logic operation.
7. The method of claim 6, further comprising receiving said single photon avalanche signal and said detector coincidence gate signal at a coincidence control unit, outputting a single photon detection coincidence signal; and the selection output unit receives the single photon detection coincidence signal and outputs a single photon detection pulse signal.
8. The method of claim 4, further comprising receiving the post-pulse release gated clock signal at a clock distribution unit, distributed to form a first post-pulse release gated clock distribution signal and a second post-pulse release gated clock distribution signal with a period T and no time difference.
9. The method of claim 8, further receiving, at the first logic unit, the first post-pulse release gated clock distribution signal, the post-pulse release gated signal being formed by a logic operation; and receiving the second rear pulse release gated clock distribution signal at the second logic unit, and forming a rear pulse release coincidence gate signal through logic operation.
10. The method of claim 9, further comprising receiving said post-pulse avalanche signal and said post-pulse release coincidence gate signal at said coincidence control unit, outputting a post-pulse release coincidence signal; and the selection output unit receives the rear pulse release coincidence signal and outputs a rear pulse release signal.
11. A single photon detector capable of suppressing post-pulses, comprising:
a synchronous light detection unit configured to receive synchronous light to form a synchronous electrical signal;
a phase-locked loop configured to receive the synchronous electrical signal, form a system recovery clock signal with a period of T, further form a detector gated clock signal with a period of T and a post-pulse release gated clock signal according to the system recovery clock signal, wherein a difference between the post-pulse release gated clock signal and the detector gated clock signal is T/2 in period;
a clock selection unit configured to receive the detector gated clock signal, the post-pulse release gated clock signal, the clock selection unit outputting the post-pulse release gated clock signal T/2 after outputting the detector gated clock signal;
the clock distribution unit is configured to receive the detector gated clock signals and is distributed to form a first detector gated clock distribution signal and a second detector gated clock distribution signal which have a period of T and have no time difference; the first and second back pulse release gated clock distribution signals are distributed to form a first and second back pulse release gated clock distribution signal with a period of T and no time difference;
a first logic unit configured to receive the first detector gated clock distribution signal, the first logic unit logically operated to form the detector gated signal; receiving the first back pulse release gating clock distribution signal, and forming the back pulse release gating signal through logic operation;
a second logic unit configured to receive the second detector gated clock distribution signal, and to form a detector coincidence gate signal by a logic operation; receiving the second post-pulse release gated clock distribution signal, and forming a post-pulse release coincidence gate signal through logic operation;
the single-photon detector is configured to receive a detector gate control signal with a period T, receive a single photon, generate avalanche, form a single-photon avalanche signal and close the gate control of the single-photon detector; after the single photon detector is gated off by T/2, receiving a back pulse release gate control signal with the period of T, opening the back pulse release gate control to form a back pulse avalanche signal, releasing a back pulse, and closing the back pulse gate control;
a coincidence control unit configured to receive the single photon avalanche signal and the detector coincidence gate signal, and output a single photon detection coincidence signal; receiving the rear pulse avalanche signal and the rear pulse release gate signal, and outputting a rear pulse release coincidence signal;
a selection output unit configured to receive the single photon detection coincidence signal and output a single photon detection pulse signal; and receiving the rear pulse release coincidence signal and outputting a rear pulse release signal.
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