CN111490839B

CN111490839B - Frequency modulation broadcasting frequency measurement demodulation electronic system

Info

Publication number: CN111490839B
Application number: CN202010309817.2A
Authority: CN
Inventors: 焦杰
Original assignee: Jilin Radio And Television Research Institute (science And Technology Information Center Of Jilin Radio And Television Bureau)
Current assignee: Jilin Radio And Television Research Institute (science And Technology Information Center Of Jilin Radio And Television Bureau)
Priority date: 2020-04-20
Filing date: 2020-04-20
Publication date: 2021-11-30
Anticipated expiration: 2040-04-20
Also published as: CN111490839A

Abstract

An electronic system for frequency measurement and demodulation of frequency modulation broadcasting relates to the field of broadcast television and solves the problem that the existing frequency modulation broadcasting monitoring and demodulation system is limited in use and cannot meet the use requirement of the system; the invention can cancel the frequency discriminator, the analog-to-digital converter and the amplifying circuit connected between the two which are necessary in the traditional demodulation equipment, thereby reducing the distortion while reducing the cost; the required circuit elements are few; demodulating to obtain digital data stream of audio program content, which can be directly played, stored or transmitted; because the program signal is sampled at four times the frequency of the pilot signal, hardware extraction of the pilot signal is not required during subsequent stereo decoding.

Description

Frequency modulation broadcasting frequency measurement demodulation electronic system

Technical Field

The invention relates to the field of broadcast television, in particular to a frequency modulation and broadcast frequency measurement demodulation electronic system.

Background

According to national standard regulation of frequency modulation broadcasting in China, frequency modulation is adopted for frequency modulation broadcasting programs, the maximum frequency deviation is 75Khz, the left and right stereo channels are carrier-suppressed double-sideband amplitude modulation 38KHz carriers, the carriers are divided into two parts to be pilot signals, and the pilot signals and the program signals are transmitted in a frequency modulation mode; the traditional program demodulation method is that a frequency discriminator is used for demodulating an intermediate frequency signal to obtain an audio frequency analog signal, and the audio frequency analog signal is converted into a digital sound data stream by an analog-to-digital converter after being amplified; in the conversion process, the analog circuit part links experienced by the program signal are more, the introduced noise and distortion are larger, and the consistency of the analog circuit product in production is not well controlled.

The prior document discloses a demodulation method for directly measuring frequency of frequency modulation broadcast by a single chip microcomputer, and provides the demodulation method for directly measuring the frequency of the single chip microcomputer, which can be used for a single sound channel program monitoring system, in particular to the demodulation method for directly measuring the frequency by the single chip microcomputer. There are the following problems:

1. the problem that hardware cannot sample two information of count and period at the same time, only correct results can be collided in an interrupt processing program repeatedly, the file also mentions that intermediate frequency signal pulses may arrive during the interrupt processing period, and an interrupt service program cannot read data of two registers at the same time, so that an accident is likely to occur. Otherwise the contents of the two registers are not paired and need to loop back to re-read until it is confirmed that their contents have not changed unexpectedly. The sampling rate of the method can reach 16 KHz; because the time required by the interrupt processing program of the single chip microcomputer to enter and exit is microsecond magnitude, the probability is required to be relied on after the time of retry collision is more than the number of times of success, and the frequency of over 24KHz is actually measured, the time slice of the main program is hardly executed by the single chip microcomputer; therefore, if a sampling rate of 76KHz for stereo decoding is required, the sampling rate is difficult to realize due to the performance limitation of the single chip microcomputer;

2. the ring oscillator is used as a filter to improve the performance of a system, the ring oscillator adopts a filter circuit of a resistance injection signal, so that the sensitivity is improved from 50dBuV to 30dBuV, the improvement can be improved by 20dB, the element parameters of the filter circuit are difficult to calculate, only proper values can be adopted, the oscillation frequency of the filter circuit is about 1.25MHz, namely the oscillation frequency is 1.25MHz by using element experience values obtained by experiments, and proper passband cannot be designed by corresponding analysis and calculation.

3. The system output data only refers to the data needing to be converted into 8 bits of data, and a specific conversion method is not provided; the present invention provides specific circuits and methods of conversion.

Disclosure of Invention

The invention provides a frequency modulation broadcast frequency measurement demodulation electronic system, aiming at solving the problems that the use of the existing frequency modulation broadcast monitoring demodulation system is limited and the use requirement of the existing frequency modulation broadcast monitoring demodulation system cannot be met.

An electronic system for frequency modulation and broadcast frequency measurement demodulation comprises an INPUT end INPUT, a clock INPUT end OSC, a sampling output end CLK, a data output end AUDIO, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an operational amplifier U1, a D flip-flop U3, an AND gate U4, a D flip-flop U5, a synchronous enabling counter U6, a synchronous zero clearing counter U7, a synchronous enabling latch U8, a synchronous frequency divider U9, a latch U10, a latch U12, a multiplier U11, a divider U15, a subtracter U16, a constant output U14 and a U13;

the INPUT end INPUT is connected with a capacitor C1, and the capacitor C1 is respectively connected with one end of a resistor R2, one end of a resistor R3, one end of a resistor R4 and the positive INPUT end of an operational amplifier U1;

the other end of the resistor R2 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is respectively connected with one end of a resistor R1 and the negative input end of an operational amplifier U1; the output end of the operational amplifier U1 is connected with the other end of the resistor R1, the other end of the resistor R3, the D input end of the D trigger U5 and the positive input end of the AND gate U4 respectively; the power supply VCC end is respectively connected with the positive power end of the operational amplifier U1 and the other end of the resistor R4; the GND end is respectively connected with the grounding end of the operational amplifier U1, one end of the capacitor C2 and the other end of the resistor R2;

the Q output end of the D flip-flop U5 is connected with the inverted input end of the AND gate U4, and the output end of the AND gate U4 is connected with the D input end of the D flip-flop U3; the C clock end of the D flip-flop U5 is respectively connected with the CP clock end of the synchronization enabling counter U6, the C clock end of the D flip-flop U3, the CP clock end of the synchronization zero clearing counter U7, the C clock end of the synchronization enabling latch U8, the C clock end of the synchronization frequency divider U9 and the clock input end OSC; the Q output end of the D flip-flop U3 is respectively connected with the CE counting enabling end of the synchronization enabling counter U6 and the LE synchronization latching enabling end of the synchronization enabling latch U8;

the QN data output end of the synchronous enabling counter U6 is connected with the DN input end of the latch U10 by a parallel data bus; the QN data output end of the synchronous clear counter U7 is connected with the DN input end of the synchronous enable latch U8 by a parallel data bus; the QN data output end of the synchronous enabling latch U8 is connected with the DN input end of the latch U12 by a parallel data bus;

the OV output end of the synchronous frequency divider U9 is respectively connected with a CLR synchronous zero clearing end of a synchronous zero clearing counter U7, a CLR synchronous zero clearing end of a synchronous enable counter U6, a C clock end of a latch U10, a C clock end of a latch U12 and a sampling output end CLK;

the QN data output end of the latch U10 is connected with the IN input end of the multiplier U11 by a parallel data bus; the OUT output end of the multiplier U11 is connected with the A input end of the divider U15 by a parallel data bus; the QN output end of the latch U12 is connected with the B input end of the divider U15 by a parallel data bus; the Y output end of the divider U15 is connected with the IN input end of the subtracter U16 through a parallel data bus;

the output end OUT of the subtracter U16 is a 24-bit parallel interface, the input end A of the divider U13 is a 32-bit parallel bus interface, wherein the low-8 bit parallel data bus NF [7..0] is connected with GND, and the high-24 bit parallel data bus NF [31..8] is connected with the 24-bit parallel interface of the output end OUT of the subtracter U16 parallel bus; the B input terminal of the divider U13 is connected to the output terminal of the constant output U14 by a parallel data bus, and the output terminal of the divider U13 is connected to the data output terminal AUDIO by a parallel data bus.

The invention has the beneficial effects that: the demodulation electronic system realizes the digital demodulation of the frequency modulation broadcast program by adopting a method of quickly measuring the frequency by four times of the frequency of the pilot signal, and is used for stereo frequency modulation broadcast signal receiving equipment;

the invention designs a signal filter circuit using frequency occupation, so that the system has higher sensitivity; by applying the technical scheme provided by the invention, a frequency discriminator, an analog-to-digital converter and an amplifying circuit connected between the frequency discriminator and the analog-to-digital converter which are necessary in the traditional demodulation equipment can be eliminated, so that the cost is reduced and the distortion is reduced; the required circuit elements are small compared to other digital demodulation circuits; demodulating to obtain digital data stream of audio program content, which can be directly played, stored or transmitted; since the program signal is sampled at four times the frequency of the pilot signal, no hardware is required to extract the pilot signal during subsequent stereo decoding.

The invention adopts a digital logic circuit, designs an edge synchronous sampling circuit for input signals, can ensure that the whole circuit synchronously works under a unified clock after synchronizing the input asynchronous signals, can simultaneously sample two information of counting and period, can measure the frequency of an intermediate frequency signal by using the rate as high as 76KHz to realize demodulation, has four times of data sampling rate as the frequency of a pilot signal, and can be directly used for stereo decoding.

The invention adopts an operational amplifier, an oscillator consisting of a resistor and a capacitor, and adopts the capacitor to inject signals to the positive input end of an operational amplifier, and the filter can conveniently design parameters of elements through calculation and can accurately design central frequency and passband; because the open loop gain of the common operational amplifier is more than one hundred thousand times, the sensitivity can be improved by more than 40dB, and the sensitivity is higher.

Drawings

Fig. 1 is a circuit diagram of an fm broadcast fm demodulation electronic system according to the present invention.

Detailed Description

First embodiment, the fm broadcast frequency measurement demodulation electronic system according to this embodiment is described with reference to fig. 1, and the system includes an INPUT terminal INPUT, a clock INPUT terminal OSC171M, a sampling output terminal CLK76, a data output terminal AUDIO, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an operational amplifier U1, a D flip-flop U3, an and gate U4, a D flip-flop U5, a synchronization enable counter U6, a synchronization clear counter U7, a synchronization enable latch U8, a synchronization frequency divider U9, a latch U10, a latch U12, a multiplier U11, a divider U15, a subtractor U16, a constant output U14, and a divider U13;

the INPUT end INPUT is connected with a capacitor C1, and a capacitor C1 is respectively connected with the positive INPUT ends of a resistor R2, a resistor R3, a resistor R4 and an operational amplifier U1; the capacitor C2 is respectively connected with the resistor R1 and the negative input end of the operational amplifier U1;

the output end of the operational amplifier U1 is respectively connected with the resistor R1, the resistor R3, the D input end of the D trigger U5 and the positive input end of the AND gate U4;

the Q output end of the D trigger U5 is connected with the reverse input end of the AND gate U4;

the clock input end OSC171M is connected to the C clock end of the D flip-flop U3, the C clock end of the D flip-flop U5, the CP clock end of the sync enable counter U6, the CP clock end of the sync clear counter U7, the C clock end of the sync enable latch U8, and the C clock end of the sync divider U9, respectively;

the output end of the AND gate U4 is connected with the D input end of a D flip-flop U3, the Q output end of the D flip-flop U3 is respectively connected with the CE counting enable end of a synchronization enable counter U6 and the LE synchronization latch enable end of a synchronization enable latch U8, the QN data output end of the synchronization enable counter U6 is connected with the DN input end of a latch U10 through a parallel data bus, and the QN data output end of the latch U10 is connected with the IN input end of a multiplier U11 through a parallel data bus;

the QN data output end of the synchronous clear counter U7 is connected with the DN input end of the synchronous enable latch U8 by a parallel data bus, the QN data output end of the synchronous enable latch U8 is connected with the DN input end of the latch U12 by a parallel data bus, the OV output end of the synchronous frequency divider U9 is respectively connected with the CLR synchronous clear end of the synchronous enable counter U6, the C clock end of the latch U10, the C clock end of the latch U12, the CLR synchronous clear end of the synchronous clear counter U7 and the sampling output end CLK 76;

the OUT output end of the multiplier U11 is connected with the A input end of a divider U15 through a parallel data bus, the QN output end of the latch U12 is connected with the B input end of a divider U15 through a parallel data bus, the Y output end of the divider U15 is connected with the IN input end of a subtracter U16 through a parallel data bus, and the output end OUT of the subtracter U16 is a 24-bit parallel interface; the A input end of the divider U13 is a 32-bit parallel bus interface, wherein the low-bit 8 is connected with GND by a parallel data bus NF [7..0 ]; and the upper 24 bits of the a input are connected to 24 bits of the parallel bus output OUT of the subtractor U16 by a parallel data bus NF [31..8 ].

The B input end of the divider U13 is connected with the output end of the constant output device U14 through a parallel data bus, the output end of the divider U13 is connected with the data output end AUDIO through a parallel data bus, and VCC is respectively connected with a positive power supply end of the operational amplifier U1 and a resistor R4; GND is connected to the op-amp U1, the capacitor C2, and the resistor R2, respectively.

In this embodiment, the operational amplifier U1, the INPUT terminal INPUT, the capacitor C1, the capacitor C2, the resistor R1, the resistor R2, the resistor R3, and the resistor R4 form a signal filter circuit; the traditional filter circuit can not output signals when no signals are input, but the signal filter circuit is a self-excited oscillation circuit and always outputs square wave signals, namely a program signal pulse sequence; when R2 ═ R4, the oscillation frequency f can be calculated;

inputting a low intermediate frequency modulated signal with a center frequency of 1.25MHz at an INPUT terminal, and limiting the amplitude with V_MRepresenting the maximum peak-to-peak value of the frequency modulated signal voltage, the signal filter circuit will be affected by the input signal to bring the output frequency close to the input signal frequency.

When a broadcast signal with better signal-to-noise ratio is received, the noise in the low-intermediate frequency modulation signal is very small and can be ignored; at this time, the low-intermediate frequency modulation signal is injected into the positive input end of the operational amplifier through the capacitor C1, and the frequency occupation occurs due to the approach of the oscillation frequency f, so that the frequency of the program signal pulse sequence is equal to the input low-intermediate frequency modulation signal;

when a weak broadcast signal is received, the signal-to-noise ratio is poor, more noise is mixed in the low-intermediate frequency modulation signal, and the noise can be distributed in a wide frequency range; at this time, the signal filter circuit can suppress signals outside the passband BW, so that the program signals near the oscillation frequency f are promoted, the frequency of the pulse sequence of the output program signals is approximately equal to the frequency of the low-intermediate frequency modulation signals, and effective program signals can be filtered from noise; if the power supply voltage of the operational amplifier is VCC, the passband BW can be calculated;

design V_MWhen the frequency is 2mV, R2 ═ R4 ═ 1K, R3 ═ 100K, R1 ═ 200K, C2 ═ 200P, and VCC ═ 3.3V, the center frequency of the filter circuit is 1.25MHz, and the bandwidth is 150 KHz.

When the received signal is strong, the amplitude of the low-IF FM signal is large, and the preceding circuit of the INPUT signal to the INPUT terminal limits the maximum peak-to-peak value of the amplitude of the INPUT signal not to exceed V_MThe passband BW is fixed to 150 KHz; when the received signal is weak, the maximum peak-to-peak value of the input signal amplitude is less than V_MThe passband will decrease.

The signal filter circuit has higher sensitivity if A is used_uRepresenting the open loop gain of the op-amp as long as the signal amplitude is greater than

The oscillation frequency can be influenced; because the open loop gain of the operational amplifier is generally more than one hundred thousand, that is to say, the filter circuit can improve the receiving sensitivity of the system by more than 40 dB.

In this embodiment, a 171MHz clock signal input from the clock input terminal OSC171M is used as a synchronous clock of the whole system, the synchronous clock is divided by the synchronous frequency divider U9 through 2250 to obtain a 76KHz sampling clock signal, the high level lasts for one synchronous clock cycle, and the sampling clock signal is output from the sampling output terminal CLK76 and simultaneously sent to the clock input terminals of the latch U10 and the latch U12, so that the latch U10 and the latch U12 latch data by using the sampling clock; according to national standard of FM stereo broadcast, the frequency of stereo pilot signal is 19KHz, the frequency of sampling clock of said system is four times of the frequency of pilot signal, and the sampled data can be directly decoded by software.

In this embodiment, a synchronous edge sampling circuit is formed by the D flip-flop U3, the and gate U4, and the D flip-flop U5, and no matter when the rising edge of the asynchronous program signal pulse arrives, a high pulse of one synchronous clock period can always be generated at the D flip-flop U3, so that the synchronous operation of the synchronous enable counter U6 and the synchronous enable latch U8 can be ensured; the basic principle of the system is to jointly calculate the values in the sync enable counter U6 and the sync enable latch U8, and the two are strictly synchronized; the sync enable counter U6 accumulates once every rising edge of the sync clock when the CE terminal is high, and the sync enable latch U8 latches once every rising edge of the sync clock when the LE terminal is high, and the accumulation and latching can be strictly synchronized.

In this embodiment, the data collector is composed of the synchronization enabling counter U6, the synchronization zero clearing counter U7, the synchronization enabling latch U8, the latch U10 and the latch U12, and the collected data can calculate the frequency of the program signal pulse; the data of the synchronization enable counter U6 can only change on the rising edge of the synchronization clock; when the CLR end and the CE end of the synchronization enabling counter U6 are at a low level at the same time, the data of the synchronization enabling counter U6 are kept unchanged all the time; when the CLR terminal of the synchronization enable counter U6 is at low level and the CE terminal is at high level, data in the synchronization enable counter U6 is accumulated at each rising edge of the synchronization clock; when the CLR terminal of the synchronization enable counter U6 is high and the CE terminal is low at the same time, the data of the synchronization enable counter U6 becomes zero at the rising edge of the synchronization clock; when the CLR terminal and the CE terminal of the synchronization enable counter U6 are simultaneously high, the data of the synchronization enable counter U6 becomes one on the rising edge of the synchronization clock; when the CLR end of the synchronous clear counter U7 is at low level, the synchronous clear counter U7 counts up at the rising edge of the synchronous clock; when the CLR terminal of the synchronous clear counter U7 is at a high level, the data of the synchronous clear counter U7 becomes zero on the rising edge of the synchronous clock; the sync enable latch U8 also completes a latch synchronously when the sync enable counter U6 increments or changes.

Therefore, at the same time that the sync enable counter U6 determines the data to be zero or one according to the condition of the program signal pulse at the rising edge of the sampling clock signal, the latch U10 latches the data of the sync enable counter U6, and the latch U12 latches the data of the sync enable latch U8.

In this embodiment, the frequency calculator is composed of the latch U10, the latch U12, the multiplier U11 and the divider U15, and each time a rising edge of the sampling clock signal passes, if data in the latch U10 is N and data in the latch U12 is M, the frequency G of the input program low and intermediate frequency signal can be calculated;

G＝N*171MHz/M

the multiplier U11 multiplies the data N input from the IN input terminal by 171 mega and then supplies the multiplied data N from the OUT output terminal to the a input terminal of the divider U15, and divides the multiplied data N by the data M supplied from the latch U12 to obtain the frequency of the program signal pulses IN Hz; the circuit is designed by adopting 32-bit width elements, the frequency of a program signal can be rapidly measured under the sampling frequency of 76KHz, the measurement precision can be better than five ten-thousandths, and the effect of the traditional 11-bit analog-to-digital conversion circuit is achieved by realizing stereo decoding.

In the embodiment, the subtracter U16 and the constant output unit U14 and the divider U13 form a sound data reducer; according to the national standard of frequency modulation broadcasting, different frequencies correspond to different sound signal voltages, and if the frequency is G, a frequency modulation program signal with 1.25MHz as the center frequency is converted into 8-bit sound data S;

S＝(G-1175000)*256/150000

the frequency G of the program signal is subtracted by 1175000 by a subtracter U16 and is sent to the upper 24 bits of an NF bus, the lower 8 bits of the NF bus are fixed to be zero, the 32-bit NF bus is connected to the input end A of a divider U13, the effect of multiplying by 256 is obtained, a constant output unit U14 fixedly outputs 150000 constants to the input end B of the divider U13, and 8-bit sound data are obtained at a data output end AUDIO; the sound data takes a sampling clock of 76KHz as a synchronous signal, and the sound data demodulated last time is output at the rising edge of each sampling clock of 76 KHz; the actual information delay time of the entire demodulation system is therefore equal to 26.3us, which is twice the sampling clock period.

Claims

1. An electronic system for frequency modulation and broadcast frequency measurement and demodulation comprises an INPUT end INPUT, a clock INPUT end OSC, a sampling output end CLK, a data output end AUDIO, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an operational amplifier U1, a D flip-flop U3, an AND gate U4, a D flip-flop U5, a synchronous enabling counter U6, a synchronous zero clearing counter U7, a synchronous enabling latch U8, a synchronous frequency divider U9, a latch U10, a latch U12, a multiplier U11, a divider U15, a subtracter U16, a constant output unit 14 and a divider U13; the method is characterized in that:

the other end of the resistor R2 is connected with one end of a capacitor C2, and the other end of the capacitor C2 is respectively connected with one end of a resistor R1 and the negative input end of an operational amplifier U1;

the output end of the operational amplifier U1 is connected with the other end of the resistor R1, the other end of the resistor R3, the D input end of the D trigger U5 and the positive input end of the AND gate U4 respectively;

the power supply VCC end is respectively connected with the positive power end of the operational amplifier U1 and the other end of the resistor R4;

the GND end is respectively connected with the grounding end of the operational amplifier U1, one end of the capacitor C2 and the other end of the resistor R2;

the Q output end of the D flip-flop U5 is connected with the inverted input end of the AND gate U4, and the output end of the AND gate U4 is connected with the D input end of the D flip-flop U3;

the C clock end of the D flip-flop U5 is respectively connected with the CP clock end of the synchronization enabling counter U6, the C clock end of the D flip-flop U3, the CP clock end of the synchronization zero clearing counter U7, the C clock end of the synchronization enabling latch U8, the C clock end of the synchronization frequency divider U9 and the clock input end OSC;

the Q output end of the D flip-flop U3 is respectively connected with the CE counting enabling end of the synchronization enabling counter U6 and the LE synchronization latching enabling end of the synchronization enabling latch U8;

the QN data output end of the synchronous enabling counter U6 is connected with the DN input end of the latch U10 by a parallel data bus;

the QN data output end of the synchronous clear counter U7 is connected with the DN input end of the synchronous enable latch U8 by a parallel data bus;

the QN data output end of the synchronous enabling latch U8 is connected with the DN input end of the latch U12 by a parallel data bus;

the QN data output end of the latch U10 is connected with the IN input end of the multiplier U11 by a parallel data bus;

the OUT output end of the multiplier U11 is connected with the A input end of the divider U15 by a parallel data bus;

the QN output end of the latch U12 is connected with the B input end of the divider U15 by a parallel data bus;

the Y output end of the divider U15 is connected with the IN input end of the subtracter U16 through a parallel data bus;

the output end OUT of the subtracter U16 is a 24-bit parallel interface, the input end A of the divider U13 is a 32-bit parallel bus interface, wherein the low-8 bit parallel data bus NF [7..0] is connected with GND, and the high-24 bit parallel data bus NF [31..8] is connected with the 24-bit parallel interface of the output end OUT of the subtracter U16 parallel bus;

the B input end of the divider U13 is connected with the output end of the constant output device U14 through a parallel data bus, and the output end of the divider U13 is connected with the data output end AUDIO through the parallel data bus;

the operational amplifier U1, the INPUT end INPUT, the capacitor C1, the capacitor C2, the resistor R1, the resistor R2, the resistor R3 and the resistor R4 form a signal filter circuit;

when R is₂＝R₄The calculation formula of the oscillation frequency f is as follows:

inputting a low intermediate frequency modulated signal with a center frequency of 1.25MHz at an INPUT end, limiting the amplitude, and adopting V_MThe maximum peak value of the voltage of the frequency modulation signal is represented, and the signal filter circuit is influenced by the input signal to enable the output frequency to be close to the input signal frequency;

when a broadcast signal with better signal-to-noise ratio is received, the noise in the low-intermediate frequency modulation signal is very small and is ignored; at this time, the low-intermediate frequency modulation signal is injected into the positive input end of the operational amplifier through the capacitor C1, and the frequency of the program signal pulse sequence is equal to the input low-intermediate frequency modulation signal;

when a weak broadcast signal is received, the signal-to-noise ratio is poor, more noise is mixed in the low-intermediate frequency modulation signal, and the noise can be distributed in a wide frequency range; at the moment, the signal filtering circuit suppresses signals outside a passband BW, so that program signals near the oscillation frequency f are promoted, the frequency of the pulse sequence of the output program signals is approximately equal to the frequency of low and medium frequency modulation signals, and effective program signals are filtered from noise; if the power supply voltage of the operational amplifier is VCC, the passband BW can be calculated;

design V_MWhen the frequency is 2mV, R2 ═ R4 ═ 1K, R3 ═ 100K, R1 ═ 200K, C2 ═ 200P, and VCC ═ 3.3V, the center frequency of the filter circuit is 1.25MHz, and the bandwidth is 150 KHz;

when the received signal is strong, the amplitude of the low-IF FM signal is large, and the preceding circuit of the INPUT signal to the INPUT terminal limits the maximum peak-to-peak value of the amplitude of the INPUT signal not to exceed V_MThe passband BW is fixed to 150 KHz; when the received signal is weak, the maximum peak-to-peak value of the input signal amplitude is less than V_MThe passband will decrease;

the latch U10, the latch U12, the multiplier U11 and the divider U15 form a frequency calculator, and each time the rising edge of the sampling clock signal passes through, if the data in the latch U10 is N and the data in the latch U12 is M, the frequency G of the low-intermediate frequency signal of the input program is calculated;

G＝N*171MHz/M

the multiplier U11 multiplies the data N inputted from the IN input terminal by 171MHz, and then supplies the multiplied data N from the OUT output terminal to the a input terminal of the divider U15, and divides the multiplied data N by the data M supplied from the latch U12 to obtain the frequency of the program signal pulse;

the subtracter U16, the constant output unit U14 and the divider U13 form a sound data reductor, and the calculation formula of converting the sound data reductor into 8-bit sound data S is as follows:

S＝(G-1175000)*256/150000

1175000 is subtracted from the frequency G of the low-IF signal by a subtracter U16, and a constant output U14 fixes the output 150000 and sends the constant to a divider U13, and 8-bit sound data is obtained at a data output terminal AUDIO.

2. An fm broadcast fm demodulation electronics system as claimed in claim 1, wherein: the 171MHz clock signal inputted from the clock input end OSC is used as the synchronous clock of the whole system, the synchronous clock is divided by the synchronous frequency divider U9 through 2250 to obtain the 76KHz sampling clock signal, the high level lasts for one synchronous clock period, and the sampling clock signal is outputted from the sampling output end CLK and is simultaneously sent to the clock input ends of the latch U10 and the latch U12, so that the latch U10 and the latch U12 can simultaneously latch data by using the sampling clock.

3. An fm broadcast fm demodulation electronics system as claimed in claim 1, wherein: the D flip-flop U3, the AND gate U4 and the D flip-flop U5 form a synchronous edge sampling circuit, and the D flip-flop U3 generates a high pulse of a synchronous clock period, so that the synchronous enabling counter U6 and the synchronous enabling latch U8 work synchronously; the values in the sync enable counter U6 and the sync enable latch U8 are counted, the sync enable counter U6 is incremented once per rising edge of the sync clock when the CE terminal is high, the sync enable latch U8 is latched once per rising edge of the sync clock when the LE terminal is high, and the incrementing and latching are synchronized.

4. An fm broadcast fm demodulation electronics system as claimed in claim 1, wherein: the synchronous enabling counter U6, the synchronous zero clearing counter U7, the synchronous enabling latch U8, the latch U10 and the latch U12 form a data acquisition unit, and acquired data are used for calculating the frequency of program signal pulses; the data of the synchronization enabling counter U6 only changes at the rising edge of the synchronization clock;

when the CLR end and the CE end of the synchronization enabling counter U6 are at a low level at the same time, the data of the synchronization enabling counter U6 are kept unchanged all the time;

when the CLR terminal of the synchronization enable counter U6 is at low level and the CE terminal is at high level, data in the synchronization enable counter U6 is accumulated at each rising edge of the synchronization clock;

when the CLR terminal of the synchronization enable counter U6 is at a high level and the CE terminal is at a low level, the data of the synchronization enable counter U6 becomes zero at the rising edge of the synchronization clock;

when the CLR terminal and the CE terminal of the synchronization enable counter U6 are simultaneously high, the data of the synchronization enable counter U6 becomes one on the rising edge of the synchronization clock;

when the CLR end of the synchronous clear counter U7 is at low level, the synchronous clear counter U7 counts up at the rising edge of the synchronous clock;

when the CLR terminal of the synchronous clear counter U7 is at a high level, the data of the synchronous clear counter U7 becomes zero on the rising edge of the synchronous clock; when the synchronization enable counter U6 is accumulated or changed to one, the synchronization enable latch U8 also synchronously completes one latch;

at the same time that the sync enable counter U6 determines the data to be zero or one according to the program signal pulse condition at the rising edge of the sampling clock signal, latch U10 latches the data of sync enable counter U6 and latch U12 latches the data of sync enable latch U8.