CN111489679B - Control method and device of time schedule controller and electronic equipment - Google Patents
Control method and device of time schedule controller and electronic equipment Download PDFInfo
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- CN111489679B CN111489679B CN202010414184.1A CN202010414184A CN111489679B CN 111489679 B CN111489679 B CN 111489679B CN 202010414184 A CN202010414184 A CN 202010414184A CN 111489679 B CN111489679 B CN 111489679B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The embodiment of the application discloses a control method and a control device of a time schedule controller and electronic equipment, wherein the method comprises the following steps: acquiring the level on a function selection pin; wherein the timing controller comprises the function selection pin; determining a signal processing mode of the time schedule controller according to the level of the function selection pin; and processing the input signal according to the signal processing mode to obtain an output signal. According to the control method and device of the time schedule controller and the electronic equipment, the production cost can be reduced.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a method and an apparatus for controlling a timing controller, and an electronic device.
Background
Currently, a high-resolution display panel requires a plurality of timing controllers including a master timing controller and a slave timing controller for driving.
The current time schedule controller needs to be provided with preset pins independently to mark a main time schedule controller or a subordinate time schedule controller, however, the pins of the time schedule controller are increased, so that the pins on a mainboard are correspondingly increased, and the production cost is higher.
Disclosure of Invention
The embodiment of the application provides a control method and device of a time schedule controller and an electronic device, which can reduce production cost.
The embodiment of the application provides a control method of a time schedule controller, which comprises the following steps:
acquiring the level of a function selection pin; wherein the timing controller includes the function selection pin;
determining a signal processing mode of the time schedule controller according to the level of the function selection pin;
and processing the input signal according to the signal processing mode to obtain an output signal.
An embodiment of the present application provides a control device of a timing controller, the device includes:
the acquisition module is used for acquiring the level on the function selection pin; wherein the timing controller includes the function selection pin;
the determining module is used for determining the signal processing mode of the time schedule controller according to the level on the function selecting pin;
and the processing module is used for processing the input signal according to the signal processing mode to obtain an output signal.
An embodiment of the present application further provides an electronic device, which includes a processor, a memory, and a computer program that is stored in the memory and can be run on the processor, and when the processor executes the program, the method for controlling any one of the timing controllers is implemented.
According to the control method and device of the time schedule controller and the electronic equipment, the level on the function selection pin is obtained; wherein the timing controller includes the function selection pin; determining a signal processing mode of the time schedule controller according to the level of the function selection pin; processing the input signal according to the signal processing mode to obtain an output signal; the signal processing mode of the time schedule controller is determined according to the level of the function selection pin, so that the function of a single pin is convenient to integrate, the number of the pins can be reduced, and the production cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a timing controller according to an embodiment of the present application.
Fig. 3 is a flowchart illustrating a control method of a timing controller according to an embodiment of the present disclosure.
Fig. 4 is a flowchart illustrating a control method of a timing controller according to another embodiment of the present disclosure.
Fig. 5 is a schematic structural diagram of a control device of a timing controller according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of a control device of a timing controller according to another embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically, electrically or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
As shown in fig. 1, a display device 100 according to an embodiment of the present invention includes a main board 10, a timing controller 20, and a display panel 50, wherein the display panel 50 includes source driving chips, and the source driving chips in the display panel 50 are connected to the timing controller 20 through a flexible connector 30.
The timing controller 20 is also connected to the main board 10. The main board 10 is used for providing video information to the timing controller 20; the video information comprises multi-frame image information, and the image information carries clock information.
The timing controller 20 is a key component of the display panel for displaying the image information of the current frame, and is configured to convert the image information into pixel data, and then convert the pixel data into a data signal by the source driver chip, and input the data signal into the display panel.
In one embodiment, the timing controller 20 includes a master timing controller 21 and two slave timing controllers 22, wherein each slave timing controller 22 is connected to the master timing controller 21. It is understood that the number of the slave timing controllers 22 is not limited thereto. The display panel 50 may include three sub-display regions, each sub-display region corresponds to a slave timing controller 22, the master timing controller 21 corresponds to a sub-display region, and the master timing controller 21 and the slave timing controller 22 are respectively configured to input pixel data to the corresponding sub-display region, that is, the master timing controller 21 and the slave timing controller 22 respectively drive the corresponding sub-display regions.
In one embodiment, as shown in fig. 2, the timing controller 20 includes: a function selection pin 23; the function selection pin 23 is used to determine a signal processing mode of the timing controller 20, and the signal processing mode is used to process an input signal.
To further reduce the production cost, the function selection pin 23 may include at least one of an activation mode selection pin 231, a cascade selection pin 232, a master-slave selection pin 233, and a mode selection pin 234. The timing controller 20 of the present embodiment can be used as a master timing controller or a slave timing controller.
When the function selection pin 23 has a first level, the function selection pin 23 has a first function;
when the function selection pin 23 has a second level, the function selection pin 23 has a second function; the first level is different from the second level.
For example, in one embodiment, when the level of the enable mode select pin 231 is 0, the timing controller is determined to be in the first enable mode (i.e., enabled from the rom); when the level of the start mode selection pin 231 is 1, determining that the timing controller is in the second start mode (i.e., starting from the flash memory);
when the level of the cascade selection pin 232 is 0, determining that the timing controller is in a non-cascade mode (namely, a single chip); when the level of the cascade selection pin 232 is 1, determining that the time schedule controller is in a cascade mode;
when the level of the master-slave selection pin 233 is 0, it is determined that the timing controller is the master controller; when the level of the master-slave selection pin 233 is 1, it is determined that the timing controller is a slave controller;
When the level of the mode selection pin 234 is 0, determining that the timing controller is in a normal mode; when the level of the mode selection pin 234 is 1, it is determined that the timing controller is the test mode.
Referring to fig. 3, fig. 3 is a flowchart illustrating a control method of a timing controller according to an embodiment of the present disclosure.
The method can comprise the following steps:
s101, obtaining the level of the function selection pin;
for example, when the display device is powered on, the level on the function selection pin 23 is acquired. To improve processing efficiency and reduce power consumption, the method may further include: the acquired level on the function selection pin 23 is stored.
In one embodiment, the function selection pin 23 may include at least one of an activation mode selection pin 231, a cascade selection pin 232, a master slave selection pin 233, and a mode selection pin 234.
S102, determining a signal processing mode of the time schedule controller according to the level of the function selection pin;
for example, the signal processing method is used for processing an input signal.
In one embodiment, to facilitate the function of the function selection pin 23, when the function selection pin 23 has a first level, the function selection pin 23 has a first function; when the function selection pin 23 has a second level, the function selection pin 23 has a second function; the first level is different from the second level.
And S103, processing the input signal according to the signal processing mode to obtain an output signal.
For example, the timing controller processes the currently input image information according to the determined signal processing manner.
For example, in one embodiment, when the timing controller is a master timing controller, the image information corresponding to each slave timing controller is sent to the corresponding slave timing controller, and the pixel data is sent to the corresponding sub-display region.
And the time sequence controller is a slave time sequence controller, converts the received image information into pixel data and sends the pixel data to the source driving chip.
The signal processing mode of the time schedule controller is determined according to the level of the function selection pin, so that the function of a single pin is convenient to integrate, the number of the pins can be reduced, and the production cost is reduced.
Referring to fig. 4, fig. 4 is a flowchart illustrating a control method of a timing controller according to another embodiment of the present disclosure. The method can comprise the following steps:
s201, respectively acquiring and storing levels on a starting mode selection pin, a cascade selection pin, a master-slave selection pin and a mode selection pin;
For example, when the display device is powered on, the levels on the start mode selection pin 231, the cascade selection pin 232, the master-slave selection pin 233, and the mode selection pin 234 are respectively obtained and stored.
And S202, determining the starting mode of the time sequence controller according to the level on the starting mode selection pin.
For example, in one embodiment, when the level of the enable mode select pin 231 is 0, the timing controller is determined to be in the first enable mode (i.e., enabled from the rom); when the level of the enable mode select pin 231 is 1, it is determined that the timing controller is in the second enable mode (i.e., is enabled from the flash memory).
And S203, determining the working mode of the time schedule controller according to the level on the mode selection pin.
For example, in one embodiment, when the level of the mode selection pin 234 is 0, the timing controller is determined to be in the normal mode; when the level of the mode selection pin 234 is 1, it is determined that the timing controller is the test mode.
S204, determining a cascade mode of the time schedule controller according to the level on the cascade selection pin;
for example, in one embodiment, when the level of the cascade select pin 232 is 0, the timing controller is determined to be in the non-cascade mode (i.e., on-chip); when the level of the cascade selection pin 232 is 1, it is determined that the timing controller is in the cascade mode.
S205, determining the current master-slave relationship of the time schedule controller according to the level of the master-slave selection pin.
For example, in one embodiment, when the level of the master slave select pin 233 is 0, the timing controller is determined to be the master controller; when the level of the master-slave selection pin 233 is 1, it is determined that the timing controller is a slave controller;
s206, determining a signal processing mode of the time schedule controller according to the cascade mode of the time schedule controller and the current master-slave relation of the time schedule controller.
In one embodiment, in order to improve processing efficiency, the determining a signal processing manner of the timing controller according to a cascade manner of the timing controller and a master-slave relationship to which the timing controller currently belongs includes:
s2061, determining a target algorithm in a preset algorithm list according to the cascade mode of the time sequence controller and the current master-slave relationship of the time sequence controller, and processing an input signal according to the target algorithm.
The time sequence controller is pre-stored with an algorithm list, namely a preset algorithm list, namely, algorithms in the preset algorithm list are used for processing the image.
For example, when the time schedule controllers are not cascaded and the time schedule controllers currently belong to a main time schedule controller, processing an input signal according to a first mode;
the first mode may be to convert the input image information according to a first preset algorithm to obtain pixel data.
When the time sequence controllers are in cascade connection and the time sequence controllers currently belong to a main time sequence controller, processing input signals according to a second mode;
the second way may be to transmit a sync signal to each slave timing controller and to convert the received image information into pixel data.
And when the time sequence controller is a slave time sequence controller, converting the received image information into pixel data and sending the pixel data to the source driving chip.
When the time sequence controllers are in cascade connection and the time sequence controllers currently belong to the subordinate time sequence controllers, processing input signals according to a third mode;
the third way may be to convert the received image information into pixel data according to a second preset algorithm, and send the pixel data to the source driver chip.
In other embodiments, the method may include one or more of steps S202 to S205. On the basis of the previous embodiment, the functions of a plurality of pins are integrated, so that the number of the pins can be further reduced, and the production cost is further reduced.
In a specific embodiment, the method specifically includes:
(1) after power up, the timing controller is locked by the phase locked loop, and the TCON reads the initial level on each pin (pin).
The Phase-Locked Loop is a feedback control circuit, referred to as a Phase-Locked Loop (PLL). The clock signal is integrated uniformly to make the high frequency device work normally, such as the access data of the memory; the phase-locked loop is characterized in that: the frequency and phase of the oscillation signal inside the loop are controlled by an externally input reference signal. Phase-locked loops are commonly used in closed-loop tracking circuits because they allow for automatic tracking of the frequency of the input signal with respect to the frequency of the output signal. In the working process of the phase-locked loop, when the frequency of the output signal is equal to that of the input signal, the output voltage and the input voltage keep a fixed phase difference value, namely the phase of the output voltage and the phase of the input voltage are locked.
(2) TCON saves the initial levels on the various pins.
(3) The TCON selects the level on the pin through the latched starting mode, and selects the corresponding starting mode. The corresponding mode is then entered by the latched level on the mode select pin.
Selecting a base pin as a BOOT base pin in a starting mode; the mode select pins are Normal and Test pins.
The modes of the timing controller may include a Normal mode (Normal mode) and a TEST mode (TEST mode), i.e., the Normal mode is a Normal use mode and the TEST mode is a factory mode.
(4) The TCON determines the final processing algorithm to process the input signal through the latched levels on the cascade select pin and the master-slave select pin. The selection principle of the multiplexing pin is as follows: when in normal use, the device can only be used for the output pin.
The Master-Slave selection pin is a Master or Slave pin, and the cascade selection pin is a single chip or cascade pin.
Based on the same inventive concept, the present embodiment further provides a control apparatus of a timing controller, as shown in fig. 5 and 6, wherein the control apparatus 60 includes: an acquisition module 61, a determination module 62 and a processing module 63;
an obtaining module 61, configured to obtain a level on the function selection pin; wherein the timing controller comprises the function selection pin;
a determining module 62, configured to determine a signal processing manner of the timing controller according to a level on the function selection pin;
and the processing module 63 is configured to process the input signal according to the signal processing mode to obtain an output signal.
The function selection pin comprises at least one of a starting mode selection pin, a cascade selection pin, a master-slave selection pin and a mode selection pin.
In an embodiment, the obtaining module 61 is specifically configured to:
respectively acquiring and storing the levels of a starting mode selection pin, a cascade selection pin, a master-slave selection pin and a mode selection pin;
in one embodiment, the determining module 62 includes:
a start determining unit 621, configured to determine a start mode of the timing controller according to a level on the start mode selection pin; and/or
A mode determining unit 622 for determining an operation mode of the timing controller according to a level on the mode selection pin; and/or
A cascade determining unit 623, configured to determine a cascade manner of the timing controller according to the level on the cascade selection pin; and/or
A master-slave determining unit 624, configured to determine a master-slave relationship to which the timing controller belongs currently according to a level on the master-slave selection pin;
a mode determining unit 625, configured to determine a signal processing mode of the timing controller according to a cascade mode of the timing controller and a master-slave relationship to which the timing controller currently belongs.
In an embodiment, the mode determining unit 625 is specifically configured to:
and determining a target algorithm in a preset algorithm list according to the cascade mode of the time sequence controller and the current master-slave relationship to which the time sequence controller belongs, and processing an input signal according to the target algorithm.
When the function select pin has a first level, the function select pin has a first function;
when the function selection pin has a second level, the function selection pin has a second function; the first level is different from the second level.
Additionally, an embodiment of the present invention further provides an electronic device, including: the timing controller comprises a processor, a memory and a computer program which is stored on the memory and can run on the processor, wherein the processor realizes the control method of the timing controller when executing the program.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
According to the control method and device of the time schedule controller and the electronic equipment, the level on the function selection pin is obtained; wherein the timing controller comprises the function selection pin; determining a signal processing mode of the time schedule controller according to the level of the function selection pin; processing the input signal according to the signal processing mode to obtain an output signal; the signal processing mode of the time schedule controller is determined according to the level of the function selection pin, so that the function of a single pin is convenient to integrate, the number of the pins can be reduced, the production cost can be reduced, and in addition, the number of connecting wires and the voltage drop can be reduced.
The foregoing detailed description is directed to a method and an apparatus for controlling a timing controller and an electronic device provided in the embodiments of the present application, and specific examples are applied in the detailed description to explain the principles and implementations of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (6)
1. A method for controlling a timing controller, comprising:
obtaining a level on a function select pin, comprising: respectively acquiring and storing the levels of a starting mode selection pin, a cascade selection pin, a master-slave selection pin and a mode selection pin; wherein the timing controller comprises the function selection pin; the function selection pin comprises at least one of a starting mode selection pin, a cascade selection pin, a master-slave selection pin and a mode selection pin;
determining a signal processing mode of the timing controller according to a level on the function selection pin, comprising: determining a starting mode of the time schedule controller according to the level on the starting mode selection pin; and/or determining the working mode of the time schedule controller according to the level on the mode selection pin; and/or determining the cascade mode of the time schedule controller according to the level on the cascade selection pin; and/or determining the current master-slave relationship of the time schedule controller according to the level on the master-slave selection pin; determining a signal processing mode of the time schedule controller according to a cascade mode of the time schedule controller and a master-slave relation to which the time schedule controller belongs currently;
And processing the input signal according to the signal processing mode to obtain an output signal.
2. The control method of the timing controller according to claim 1,
the step of determining the signal processing mode of the time schedule controller according to the cascade mode of the time schedule controller and the current master-slave relationship of the time schedule controller comprises the following steps:
and determining a target algorithm in a preset algorithm list according to the cascade mode of the time sequence controller and the current master-slave relationship to which the time sequence controller belongs, and processing an input signal according to the target algorithm.
3. The control method of the timing controller according to claim 1,
when the function select pin has a first level, the function select pin has a first function;
when the function select pin has a second level, the function select pin has a second function; the first level is different from the second level.
4. A control apparatus of a timing controller, comprising:
the acquisition module is used for acquiring the level on the function selection pin; wherein the timing controller comprises the function selection pin; the function selection pin comprises at least one of a starting mode selection pin, a cascade selection pin, a master-slave selection pin and a mode selection pin; the acquisition module is specifically configured to: respectively acquiring and storing the levels of a starting mode selection pin, a cascade selection pin, a master-slave selection pin and a mode selection pin;
The determining module is used for determining a signal processing mode of the time schedule controller according to the level on the function selecting pin; the determining module comprises: the starting determining unit is used for determining the starting mode of the time schedule controller according to the level on the starting mode selecting pin; and/or a mode determining unit for determining the working mode of the time schedule controller according to the level on the mode selection pin; and/or the cascade determining unit is used for determining the cascade mode of the time schedule controller according to the level on the cascade selection pin; and/or a master-slave determining unit, which is used for determining the current master-slave relationship of the time schedule controller according to the level on the master-slave selection pin; the mode determining unit is used for determining a signal processing mode of the time sequence controller according to the cascade mode of the time sequence controller and the current master-slave relationship of the time sequence controller;
and the processing module is used for processing the input signal according to the signal processing mode to obtain an output signal.
5. The control apparatus of the timing controller according to claim 4,
the mode determination unit is specifically configured to:
And determining a target algorithm in a preset algorithm list according to the cascade mode of the time sequence controller and the current master-slave relationship to which the time sequence controller belongs, and processing an input signal according to the target algorithm.
6. An electronic device comprising a processor, a memory, and a computer program stored on the memory and executable on the processor, the processor implementing the control method of the timing controller according to any one of claims 1 to 3 when executing the program.
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