KR101481162B1 - Method for synchronizing clock frequency of CPU and memory and apparatus using the same - Google Patents

Abstract

The present invention relates to a clock frequency synchronization method for a CPU and a memory, which can reduce unnecessary power consumption by synchronizing a clock of a CPU FSB and a memory clock when the operation of a computer system is started, thereby reducing power consumption and extending battery life. .

That is, the present invention relates to a method of synchronizing a CPU FSB and a memory module by adjusting a multiplication factor of a source clock in a CPU or adjusting a bit selector bit input to a clock generator, and an apparatus using the same.

CPU, FSB, clock, synchronization, power consumption, frequency

Description

TECHNICAL FIELD [0001] The present invention relates to a method of synchronizing a clock frequency of a CPU and a memory,

The present invention relates to a clock frequency synchronization method for a CPU and a memory, which can reduce unnecessary power consumption by synchronizing a clock of a CPU FSB with a memory clock when the computer system starts to be driven, thereby reducing power consumption and extending battery life. .

When the computer system is started, the ROM BIOS bootstrap is loaded from the FFFF0h memory address and POST (Post On Self Test) is started. Next, if the boot disk is not checked in the A drive, the bootstrap checks the hard disk, and if the boot disk is found, the ROM loader transfers control to the operating system. Next, the master table code and the partition table are read. Thereafter, the startup process is completed so that the user can operate the computer system.

In addition, at the time of starting the computer system, a central processing unit (CPU) checks the current state of various peripheral devices and controls so as to provide appropriate feedback to each device. The CPU can control the clock frequency of each device. In the related art, a problem caused by a difference in clock frequency driven at different positions is not compensated for but is directly driven, thereby causing a large loss in power consumption.

For example, taking the Montevina platform as an example, the CPU Front Side Bus (FSB) operates at 1066M and the memory clock can operate at 667M / 800M / 1066M, depending on the characteristics of the memory module.

If the memory module is operating at 667M, then the CPU FSB will run at 1066M and the memory will run at 667M. Therefore, in an environment where the memory operates at 667M, there is no significant difference in CPU performance between the case where the CPU FSB operates at 667M or 800M.

However, in the above case, as the clock frequency of the CPU FSB becomes larger, the power consumption consumed by the computer system increases and at the same time the battery life is affected. Accordingly, the power consumption problem caused by unnecessarily driving the clock frequency of the CPU FSB when the memory operates as a low clock frequency is pointed out as a serious problem in a computer system.

Accordingly, the present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method of reducing power consumption and improving the life of a battery by synchronizing a CPU FSB with a memory clock and a device using the same .

In order to solve the above problems, the present invention proposes a clock frequency synchronization method for a CPU and a memory and an apparatus using the same.

A method of synchronizing a clock frequency of a CPU and a memory according to a first embodiment of the present invention includes: measuring a clock frequency of a memory when power of the system is applied; Receiving a bit selector signal from a CPU and transmitting a clock signal corresponding to the received bit selector signal to the CPU and the memory controller; And adjusting the cell multiplier of the clock signal received by the CPU to synchronize to the measured clock frequency of the memory.

According to another aspect of the present invention, there is provided a clock frequency synchronization method for a CPU and a memory, comprising: measuring a clock frequency of a memory when power of the system is applied; Receiving a bit selector signal from a CPU; Adjusting a bit of the received bit selector signal to synchronize to a clock frequency of the measured memory; Transmitting the adjusted bit selector signal to a clock generator; And transmitting a clock signal corresponding to the received bit selector signal to the CPU and the memory controller.

According to the present invention, by synchronizing the clock frequency of the CPU FSB with the memory module, the conventional unnecessary power consumption can be reduced and the life of the battery can be improved.

The present invention relates to a clock frequency synchronization method for a CPU and a memory, which can reduce unnecessary power consumption by synchronizing a clock of a CPU FSB and a memory clock when the computer system is started, thereby reducing power consumption and extending battery life will be.

A method of synchronizing a clock frequency of a CPU and a memory according to a first embodiment of the present invention includes: measuring a clock frequency of a memory when power of the system is applied; Receiving a bit selector signal from a CPU and transmitting a clock signal corresponding to the received bit selector signal to the CPU and the memory controller; And adjusting the cell multiplier of the clock signal received by the CPU to synchronize to the measured clock frequency of the memory.

Preferably, the bit selector signal is a 3-bit signal, and the frequency of the clock signal transmitted to the CPU and the memory controller is the same.

Preferably, the bit selector signal generated from the CPU is transmitted to a clock generator, and a predetermined clock signal is transmitted to the CPU and the memory controller by the clock generator.

According to another aspect of the present invention, there is provided a clock frequency synchronization method for a CPU and a memory, comprising: measuring a clock frequency of a memory when power of the system is applied; Receiving a bit selector signal from a CPU; Adjusting a bit of the received bit selector signal to synchronize to a clock frequency of the measured memory; Transmitting the adjusted bit selector signal to a clock generator; And transmitting a clock signal corresponding to the received bit selector signal to the CPU and the memory controller.

Preferably, adjusting the bits of the received bit selector signal to synchronize to the measured clock frequency of the memory is performed by an I / O Controller Hub (ICH) or an Embedded Controller (EC).

Preferably, the measured clock frequency information of the memory is transmitted to the ICH or the EC via the BIOS.

The clock frequency synchronization apparatus for a CPU and a memory according to an exemplary embodiment of the present invention includes a central processing unit (CPU) for controlling a current state of a peripheral device to provide appropriate feedback to each device; A memory controller for controlling a memory module in a system controlled by the central processing unit and connected to the central processing unit via a FSB; And a clock generator that receives a bit selector signal from the central processing unit and transmits a clock signal corresponding to the received bit selector signal to the central processing unit (CPU) and the memory controller.

The clock frequency synchronization apparatus for a CPU and a memory according to an exemplary embodiment of the present invention includes a central processing unit (CPU) for controlling a current state of a peripheral device to provide appropriate feedback to each device; A memory controller for controlling a memory module in a system controlled by the central processing unit and connected to the central processing unit via a FSB; Switch logic for receiving a bit selector signal from the central processing unit and adjusting bits of the received bit selector to synchronize to a clock frequency of the memory; And a clock generator receiving the adjusted bit selector signal from the switch logic and transmitting a corresponding clock signal to the central processing unit (CPU) and the memory controller.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout.

1 is a block diagram illustrating a clock frequency synchronization method for a CPU and a memory according to a first embodiment of the present invention.

The clock frequency synchronization method of the CPU and the memory according to the first embodiment of the present invention measures the clock frequency of the memory module and adjusts the clock frequency of the CPU FSB so as to be synchronized with the measured clock frequency. Is adjusted by adjusting the sieve multiplication factor.

Therefore, it is desirable that the sieve multiplier is designed to be arbitrarily adjustable according to external control at the time of CPU production, and as a result, it can be set to be synchronized with the clock frequency of the memory according to the adjusted sieve multiplier.

As shown in FIG. 1, the clock frequency of the memory module 13 is measured by the memory controller 12. The memory module 13 may be somewhat different depending on the platform environment, but is generally set to operate at 667M / 800M / 1066M.

The memory controller 12 generally includes an element that is responsible for connection between a memory and a CPU. The memory controller 12 may include an MCH (Memory Controller Hub) or a GMCH (Graphics Memory Controller Hub), for example.

The MCH is a chip having a conventional northbridge function for connecting a memory and a CPU. Depending on which microprocessor or memory the MCH corresponds to, the type of microprocessor memory to which the chipset is compatible is determined.

In addition, the GMCH incorporates a graphic accelerator function in the MCH responsible for connection between a memory and a microprocessor. The GMCH is a method of occupying a part of the main memory as a video memory, but a method of securing a dedicated memory by mounting a memory module in the AGP slot is also possible.

If the clock frequency information of the memory module 13 is checked by the memory controller 12, the memory controller 12 transmits the collected information to the CPU 11. [ Therefore, the CPU 11 uses the clock frequency information as information to be synchronized with the memory module 13.

Further, the CPU 11 transmits a Bit Selector (BSEL) signal to the clock generator 14. The bit selector signal is a signal containing clock frequency signal information supported by the CPU. When the bit selector signal is transmitted to the clock generator 14, the clock generator 14, which receives the bit selector signal, And transfers the source clock to the CPU 11 and the memory controller 12.

The bit selector signal may be a 3-bit signal, for example, and is therefore designed to adjust 2 ³ = 8 source clock signals. For example, when the bit selector signal is a 3-bit signal, [000: 266M], [001: 233M], [010: 200M], [011: 166M], [100: Source clock information can be set.

For example, in a system in which the clock frequency supported by the CPU FSB is 1066M and the multiplier factor of the multiplier is × 4 in the CPU, it is appropriate that the source clock signal is about 266M, so that the bit selector signal [000: 266M] Is transmitted to the clock generator (14).

Then, the clock generator 14 receiving the 000 bit selector signal transmits the source clock signal of 266M to the CPU 11 and the memory controller 12. The source clock signal input to the CPU 11 as the 266M is output through an internal multiplier (described in FIG. 2) to have a clock frequency of about 4 times, that is, 1066M, so that the CPU FSB is set to operate at 1066M .

In the system in which the memory module 13 operates at 1066M, there is no big problem even if the CPU FSB operates at 1066M. However, even when the memory module 13 operates at 800M or 667M as described above, The power consumption is greatly reduced.

Therefore, in the clock frequency synchronization method of the CPU and the memory according to the first embodiment of the present invention, the clock frequency of the memory module 13 is synchronized by adjusting the multiplication factor of the source clock frequency received by the CPU 11.

The process of multiplying the frequency of the source clock signal input to the CPU 11 by a predetermined factor will be described in detail with reference to FIG.

2 is a schematic diagram schematically illustrating a process of adjusting a cell multiplier of a source clock signal in a CPU according to a first embodiment of the present invention.

The CPU 11 includes a multiplier 16 for increasing a predetermined input clock frequency by an integer multiple. The multiplier 16 utilizes a feature of a nonlinear element that generates harmonics. That is, it is possible to adjust the magnification according to the control of the system using a desired one harmonic among a plurality of output harmonics. This can be obtained by calculating and matching the nonlinear element output impedance value at the desired harmonic frequency.

This can be achieved by matching the desired frequency and filtering all the remaining frequency components. However, since only the specific frequency is minimized and the high-frequency output is smaller than the original frequency, the gain can not be avoided.

In addition, the circuit construction method of the multiplier 16 has a structure similar to that of a mixer. The multiplier 16 is divided into a passive type using a diode and an active type using a transistor.

FIG. 2 illustrates an example in which the magnification of the multiplier 16 is adjusted by a plurality of switches according to a control signal input to the multiplier 16. Therefore, the source clock signal of the CPU can be adjusted to a desired magnification so as to synchronize with the memory module.

It is obvious that the method and structure of the multiplier 16 for adjusting the magnification of the source clock are not limited to the embodiment of the present invention, and the structure and the method of any multiplier fall within the scope of the present invention.

3 and 4 are block diagrams illustrating a clock frequency synchronization method for a CPU and a memory according to a second embodiment of the present invention.

The clock frequency synchronization method of the CPU and the memory according to the second embodiment of the present invention adjusts the bit of the bit selector signal itself received from the CPU so as to be adjusted to be synchronized with the clock frequency of the memory.

That is, the first embodiment of the present invention is characterized by adjusting the multiplication factor of the source clock signal in the CPU, while in the second embodiment of the present invention, the bit selector signal itself input to the clock generator 24 is adjusted Thereby adjusting the clock size to be transmitted to the CPU 21 and the memory controller 22.

As shown in FIG. 3, the clock frequency of the memory module 23 is measured by the memory controller 22. The memory module 23 may be somewhat different depending on the platform environment, but is generally set to operate at 667M / 800M / 1066M.

The memory controller 22 generally includes an element that is responsible for connection between a memory and a CPU, and may include, for example, an MCH (Memory Controller Hub) or a GMCH (Graphics Memory Controller Hub).

The MCH is a chip having a conventional northbridge function for connecting a memory and a CPU. Depending on which microprocessor or memory the MCH corresponds to, the type of microprocessor memory to which the chipset is compatible is determined.

In addition, the GMCH incorporates a graphic accelerator function in the MCH responsible for connection between a memory and a microprocessor. The GMCH is a method of occupying a part of the main memory as a video memory, but a method of securing a dedicated memory by mounting a memory module in the AGP slot is also possible.

If the clock frequency information of the memory module 23 is checked by the memory controller 22, the memory controller 22 transmits the collected information to the CPU 21. [ Therefore, the CPU 21 uses the clock frequency information as information for synchronizing with the memory module 23.

Also, the CPU 21 transmits a Bit Selector (BSEL) signal to the external switch logic 25. The bit selector signal may be, for example, a 3-bit signal, so that it is designed to adjust 2 ³ = 8 source clock signals. For example, when the bit selector signal is a 3-bit signal, [000: 266M], [001: 233M], [010: 200M], [011: 166M], [100: Source clock information can be set.

For example, in a system in which the clock frequency supported by the CPU FSB is 1066M and the multiplier factor of the multiplier in the CPU is × 4, since the source clock signal is about 266M, the bit selector signal of [000: 266M] Clock generator.

In the system in which the memory module 23 operates at 1066M, even if the CPU FSB operates at 1066M, there is no serious problem. However, even when the memory module 23 operates at 800M or 667M as described above, The power consumption is greatly reduced.

Therefore, in the clock frequency synchronization method of the CPU and the memory according to the second embodiment of the present invention, the CPU 21 and the memory controller 22 are controlled by the bit And may transmit a source clock signal that enables synchronization to the frequency of the memory module 23. [

In a system in which the CPU FSB operates at 1066M and the CPU has a multiplier factor of x4, the CPU 21 controls the switch logic 25 to select [000: 266M] of the second embodiment of the present invention. Bit selector signal.

Therefore, if the memory module 23 is driven at 800M, if the clock generator 24 transmits a source clock signal of 266M to the CPU 21 corresponding to the bit selector signal of [000: 266M] The CPU is set to a multiplier factor of x4, and the CPU FSB is driven at about 1066M.

That is, the bit of the bit selector signal is adjusted by an ICH (I / O Controller Hub) or an EC (Embedded Controller) in order to minimize unnecessary power consumption as described above.

More specifically, since the current CPU 21 is driven at 1066M, the bit selector signal generated from the CPU 21 is [000: 266M], but ICH or EC causes bits of the [000] (23).

The clock frequency information of the memory module 23 is transmitted to the ICH or the EC via a BIOS or the like.

In the above example, since the memory module 23 is driven at 800M, a source clock of 200M is required for the CPU 21 to synchronize with the bit clock signal. This corresponds to the bit selector signal [010: 200M] in the above example, Can be obtained by inverting the middle bit (B1) of the 3-bit signal.

An example of this is illustrated in FIG. As shown in FIG. 4, it can be seen that the original bit selector signal is [000], but the center bit is inverted by inverting by ICH or EC control signal to [010].

Therefore, when a bit selector signal of [010: 200M] is input to the clock generator 24, a source clock signal of 200M is input to the CPU 21 and the memory controller 22, so that the CPU FSB is driven at 800M, Synchronization with the clock frequency of the memory module 23 can be matched to minimize power consumption of the system.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. It can be implemented.

The scope of the present invention is defined by the appended claims, and all differences within the scope of the claims are to be construed as being included in the present invention.

1 is a block diagram showing a clock frequency synchronization method of a CPU and a memory according to a first embodiment of the present invention;

2 is a schematic view schematically illustrating a process of adjusting a sieve rate of a source clock signal in a CPU according to a first embodiment of the present invention;

3 is a block diagram illustrating a clock frequency synchronization method for a CPU and a memory according to a second embodiment of the present invention;

4 is a schematic diagram schematically illustrating a process of adjusting a bit selector signal received from a CPU according to a second embodiment of the present invention;

       Description of Major Parts of the Invention

11, 21: CPU 12, 22: memory controller

13, 23: memory modules 14, 24: clock generator

16: multiplier 25: switch logic

26: ICH or EC

Claims (15)

The central processing unit (CPU) measuring the clock frequency of the memory when power of the system is applied; The clock generator receiving a bit selector signal from the CPU and transmitting a clock signal corresponding to the received bit selector signal to the CPU and the memory controller; And Wherein the central processing unit comprises adjusting the cell multiplier of the clock signal received by the CPU to synchronize to the clock frequency of the measured memory The step of adjusting the sieve factor of the clock signal comprises: And adjusting a sieve ratio of the clock signal using one harmonic among a plurality of harmonics output from the CPU How to synchronize clock frequency of CPU and memory. The method according to claim 1, The step of adjusting the sieve factor of the clock signal Matching the frequency for synchronizing with the clock frequency of the measured memory to the impedance value of the nonlinear element output from the CPU and adjusting the sieve factor of the clock signal to correspond to the obtained frequency How to synchronize clock frequency of CPU and memory. The method according to claim 1, Wherein the bit selector signal is a 3-bit signal. The method according to claim 1, Wherein the frequency of the clock signal transmitted to the CPU and the memory controller is the same. The method according to claim 1, Wherein the bit selector signal generated from the CPU is transmitted to a clock generator and a predetermined clock signal is transmitted to the CPU and the memory controller by the clock generator. A central processing unit (CPU), measuring the clock frequency of the memory when the power of the system is applied; The switch logic receiving a bit selector signal from the CPU; Adjusting the bit of the received bit selector signal such that the switch logic synchronizes to a clock frequency of the measured memory; The switch logic transmitting the adjusted bit selector signal to a clock generator; And The clock generator transmitting a clock signal corresponding to the received bit selector signal to the CPU and the memory controller, Adjusting the bits of the received bit selector signal to synchronize to the measured clock frequency of the memory Adjusting the bit of the bit selector signal to coincide with the clock of the memory module in consideration of a pre-set power factor to the CPU  How to synchronize clock frequency of CPU and memory. The method according to claim 6, Wherein the bit selector signal is a 3-bit signal. The method according to claim 6, Wherein adjusting the bits of the received bit selector signal to synchronize to the measured clock frequency of the memory is performed by an I / O Controller Hub (ICH) or an Embedded Controller (EC) Of clock frequency synchronization. 9. The method of claim 8, And the clock frequency information of the measured memory is transmitted to the ICH or the EC via the BIOS. A central processing unit (CPU) for controlling the status of the peripheral device to provide feedback to each device; A memory controller for controlling a memory module in a system controlled by the central processing unit and connected to the central processing unit via a FSB; And And a clock generator for receiving a bit selector signal from the central processing unit and for transmitting a clock signal corresponding to the received bit selector signal to the central processing unit (CPU) and the memory controller, Wherein the central processing unit (CPU) includes a multiplier that adjusts the multiplication factor of the clock signal by using one harmonic among a plurality of harmonics output from the CPU. 11. The method of claim 10, The multiplier in the central processing unit (CPU) And a multiplier that adjusts the sieve factor of the clock signal so as to correspond to the frequency obtained by matching the impedance value of the nonlinear element output from the CPU CPU and memory clock frequency synchronization device. 11. The method of claim 10, Wherein the central processing unit further comprises a multiplier for increasing an input clock frequency signal by a predetermined magnification and outputting the multiplied clock signal. 13. The method of claim 12, Wherein the multiplier adjusts the multiplication factor of the clock signal received by the central processing unit (CPU) so as to synchronize with the clock frequency of the memory module, and outputs the adjusted clock signal. A central processing unit (CPU) for controlling the status of the peripheral device to provide feedback to each device; A memory controller for controlling a memory module in a system controlled by the central processing unit and connected to the central processing unit via a FSB; Switch logic for receiving a bit selector signal from the central processing unit and adjusting bits of the received bit selector to synchronize to a clock frequency of the memory; And And a clock generator that receives the adjusted bit selector signal from the switch logic and transmits a corresponding clock signal to the central processing unit (CPU) and the memory controller The switch logic for adjusting the bits of the bit selector And switch logic for adjusting the bit of the bit selector signal to match the clock of the memory module in consideration of a predetermined multiplier factor to the CPU CPU and memory clock frequency synchronization device. 15. The method of claim 14, And an ECC (I / O Controller Hub) or an EC (Embedded Controller) for receiving the clock signal information of the memory module from the memory controller and controlling the switch logic to synchronize with the clock frequency of the memory module Features a CPU and memory clock frequency synchronization device.

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