CN111477689A - Silicon carbide JBS structure with high avalanche tolerance and preparation method thereof - Google Patents
Silicon carbide JBS structure with high avalanche tolerance and preparation method thereof Download PDFInfo
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- CN111477689A CN111477689A CN201910071617.5A CN201910071617A CN111477689A CN 111477689 A CN111477689 A CN 111477689A CN 201910071617 A CN201910071617 A CN 201910071617A CN 111477689 A CN111477689 A CN 111477689A
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 238000002513 implantation Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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Abstract
The invention discloses a high avalanche tolerance silicon carbide JBS structure and a preparation method thereof. The two types of P-type injection are realized by photoetching and etching grooves with different depths on the mask layer twice, and the avalanche tolerance of the silicon carbide JBS can be obviously improved by introducing the tapered P-type injection region.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a device structure and a preparation method thereof.
Background
Silicon carbide (SiC) is a wide-bandgap semiconductor material with very excellent electrical properties, has the characteristics of large forbidden bandwidth, high critical breakdown field strength, high saturated electron drift speed, high thermal conductivity and the like, is particularly suitable for preparing various power electronic devices, and has remarkable application prospect in the extreme application fields of high temperature, high pressure, high power, high radiation and the like. Because of the large forbidden bandwidth of SiC, schottky diodes are the most commonly used rectifying devices made of SiC materials. However, because the critical breakdown electric field intensity of the SiC material is large, and a pure schottky has obvious electric leakage when the reverse blocking occurs, the SiC schottky diode generally adopts a junction barrier schottky diode (JBS) structure, and adopts the mutual interpenetration arrangement of a PN junction and a schottky junction, and shields the electric field intensity of the surrounding schottky junction by using the depletion effect of the PN junction, thereby reducing the reverse leakage current. However, the avalanche tolerance of the common JBS structure is not high, and the ability to resist voltage fluctuation is insufficient.
Disclosure of Invention
Technical problem to be solved
The invention provides a silicon carbide JBS structure with high avalanche tolerance and a preparation method thereof, which at least partially solve the technical problems.
(II) technical scheme
According to an aspect of the invention, there is provided a silicon carbide JBS structure comprising:
an N + type substrate;
the N-type epitaxial layer is positioned on the N + type substrate;
the P-type injection region is positioned in the N-type epitaxial layer;
the N + type substrate and the N-type epitaxial layer are made of silicon carbide;
the P-type implantation region comprises a strip-shaped implantation region and a cone-shaped implantation region.
In a further embodiment, the silicon carbide JBS structure further comprises:
the cathode electrode is prepared at the bottom of the N + type substrate;
and the anode electrode is prepared on the top of the N-type epitaxial layer.
According to another aspect of the present invention, there is provided a method for preparing a silicon carbide JBS structure, comprising:
depositing a mask layer on the top surface of the silicon carbide epitaxial wafer and etching to form a plurality of grooves with different depths;
and carrying out ion implantation on the upper surface of the silicon carbide epitaxial wafer to form a strip-shaped implantation area and a cone-shaped implantation area.
In a further embodiment, the method for preparing a silicon carbide JBS structure further comprises:
removing the mask layer and activating implanted ions by high-temperature annealing; depositing cathode electrode metal on the bottom surface of the silicon carbide epitaxial wafer, and annealing to form ohmic contact; and depositing anode electrode metal on the top surface of the silicon carbide epitaxial wafer.
In a further embodiment, the etching to form a plurality of trenches having different depths includes:
etching a strip-shaped groove on the mask layer;
and performing stripe etching again in a direction different from the stripe-shaped grooves to form a plurality of grooves with different depths.
In a further embodiment, the strip-shaped trench is not etched to the bottom of the mask layer;
and etching the overlapped area twice until the etching depth reaches the bottom of the mask layer.
In further embodiments, the implanted ions are B or Al.
In a further embodiment, the high temperature annealing activates the implanted ions at 1500-2000 ℃ for 1-60 min.
In further embodiments, the cathode electrode metal is Ni, Ti, W, Ta, or a mixture of a plurality thereof; the anode electrode metal is Ni, Ti, W, Ta, Al, TiN, TiC, TiW or the lamination of a plurality of metal systems.
In further embodiments, the annealing is rapid thermal annealing or laser annealing.
(III) advantageous effects
The method has the advantages that the strip-shaped injection region and the cone-shaped injection region are prepared, particularly the edge of the cone-shaped region is easy to initiate an electric field aggregation effect and an avalanche effect, so that the avalanche tolerance of the silicon carbide JBS structure is effectively improved.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of the present invention for depositing an implantation mask on the top surface of a SiC epitaxial wafer;
FIG. 2 is a schematic structural diagram of a mask layer after a stripe-shaped trench is formed by etching according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of the mask layer after a plurality of trenches with different depths are formed by secondary etching according to the embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an embodiment of the present invention after ion implantation;
FIG. 5 is a schematic structural diagram of the mask layer after being removed according to the embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a cathode electrode prepared on the bottom surface of a SiC epitaxial wafer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the structure after deposition of anodic metal in accordance with one embodiment of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
According to an embodiment of the present invention, there is provided a silicon carbide JBS structure, as shown in fig. 6, including:
an N + type substrate 2;
the N-type epitaxial layer 3 is positioned on the N + type substrate 2;
the P-type injection region 4 is positioned in the N-type epitaxial layer 3;
the N + type substrate 2 and the N-type epitaxial layer 3 are made of silicon carbide;
the P-type implantation region 4 includes a strip-shaped implantation region and a cone-shaped implantation region.
The avalanche tolerance of the silicon carbide JBS structure can be effectively improved through the strip-shaped injection region and the cone-shaped injection region; wherein, the depth of the taper-shaped implantation region is deeper than that of the strip-shaped implantation region.
In this embodiment, the silicon carbide JBS structure further includes:
the cathode electrode 1 is prepared at the bottom of the N + type substrate;
and the anode electrode 5 is prepared on the top of the N-type epitaxial layer.
According to another embodiment of the invention, there is provided a method for preparing a silicon carbide JBS structure, including:
as shown in fig. 1 to 3, a mask layer 6 is deposited on the top surface of the silicon carbide epitaxial wafer and etched to form a plurality of trenches with different depths;
as shown in fig. 4, ion implantation is performed on the upper surface of the silicon carbide epitaxial wafer to form a stripe-shaped implantation region and a taper-shaped implantation region.
Because the depth of the grooves on the mask layer 6 is different, strip-shaped injection regions and cone-shaped injection regions with different depths are formed in the epitaxial layer on the lower layer of the mask layer after ion implantation is carried out on the upper surface of the mask layer, and therefore the avalanche tolerance of the silicon carbide JBS structure is improved.
In this embodiment, the method for preparing the JBS structure further includes:
as shown in fig. 5, the mask layer 6 is removed and high temperature annealing is performed to activate implanted ions;
as shown in fig. 6, cathode electrode metal is deposited on the bottom surface of the silicon carbide epitaxial wafer, and ohmic contact is formed by annealing; and depositing anode electrode metal on the top surface of the silicon carbide epitaxial wafer.
In this embodiment, the forming of the plurality of trenches with different depths by etching includes:
etching a strip-shaped groove on the mask layer 6;
and performing stripe etching again in a direction different from the stripe-shaped grooves to form a plurality of grooves with different depths.
Wherein, the number and the depth of the grooves are not limited. Preferably, the strip-shaped groove is not etched to the bottom of the mask layer 6; the etching depth of the overlapped area of the two times reaches the bottom of the mask layer 6.
In this embodiment, the implanted ions are B or Al.
In this embodiment, the high temperature annealing activates the implanted ions at 1500-2000 ℃ for 1-60 min.
In this embodiment, the cathode electrode metal is Ni, Ti, W, Ta, or a mixture of a plurality thereof; the anode electrode metal is Ni, Ti, W, Ta, Al, TiN, TiC, TiW or a lamination of a plurality of metal systems.
In this embodiment, the annealing method may be rapid thermal annealing or laser annealing.
It should be noted that the examples provided herein may include parameters of particular values, but these parameters need not be exactly equal to the corresponding values, but may be approximated to the corresponding values within acceptable error tolerances or design constraints. Directional phrases used in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", "top", "bottom", etc., refer only to the orientation of the attached drawings and are not intended to limit the scope of the present invention. In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A silicon carbide JBS structure comprising:
an N + -type substrate (2);
an N-type epitaxial layer (3) on the N + type substrate (2);
the P-type injection region (4) is positioned in the N-type epitaxial layer (3);
the N + type substrate (2) and the N-type epitaxial layer (3) are made of silicon carbide;
the P-type injection region (4) is characterized by comprising a strip-shaped injection region and a cone-shaped injection region.
2. The silicon carbide JBS structure of claim 1, further comprising:
the cathode electrode (1) is prepared at the bottom of the N + type substrate;
and the anode electrode (5) is prepared on the top of the N-type epitaxial layer.
3. A preparation method of a silicon carbide JBS structure is characterized by comprising the following steps:
depositing a mask layer (6) on the top surface of the silicon carbide epitaxial wafer and etching to form a plurality of grooves with different depths;
and carrying out ion implantation on the upper surface of the silicon carbide epitaxial wafer to form a strip-shaped implantation area and a cone-shaped implantation area.
4. The method of preparing a silicon carbide JBS structure of claim 3, further comprising:
removing the mask layer (6) and activating implanted ions by high-temperature annealing; depositing cathode electrode metal on the bottom surface of the silicon carbide epitaxial wafer, and annealing to form ohmic contact; and depositing anode electrode metal on the top surface of the silicon carbide epitaxial wafer.
5. The method of claim 3, wherein the etching to form the plurality of trenches having different depths comprises:
etching a strip-shaped groove on the mask layer (6);
and performing stripe etching again in a direction different from the stripe-shaped grooves to form a plurality of grooves with different depths.
6. The method for preparing the silicon carbide JBS according to the claim 5, wherein the strip-shaped trench is not etched to the bottom of the mask layer (6);
and etching the overlapped area of the two times to reach the bottom of the mask layer (6).
7. The method of claim 3, wherein the implanted ions are B or Al.
8. The method for preparing the silicon carbide JBS as claimed in claim 4, wherein the high temperature annealing activates the implanted ions at 1500-2000 ℃ for 1-60 min.
9. The method for preparing silicon carbide JBS according to claim 4, wherein the cathode electrode metal is Ni, Ti, W, Ta or a mixture of a plurality of Ni, Ti, W, Ta or a mixture of Ni and Ta; the anode electrode metal is Ni, Ti, W, Ta, Al, TiN, TiC, TiW or the lamination of a plurality of metal systems.
10. The method for preparing the silicon carbide JBS according to claim 4, wherein the annealing mode is rapid thermal annealing or laser annealing.
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| CN201910071617.5A CN111477689A (en) | 2019-01-24 | 2019-01-24 | Silicon carbide JBS structure with high avalanche tolerance and preparation method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252478A (en) * | 1999-02-26 | 2000-09-14 | Hitachi Ltd | Schottky barrier diode |
| JP2005229070A (en) * | 2004-02-16 | 2005-08-25 | Matsushita Electric Ind Co Ltd | Schottky barrier diode and manufacturing method therefor |
| CN106057912A (en) * | 2015-04-09 | 2016-10-26 | 丰田自动车株式会社 | Diode and method of manufacturing diode |
-
2019
- 2019-01-24 CN CN201910071617.5A patent/CN111477689A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252478A (en) * | 1999-02-26 | 2000-09-14 | Hitachi Ltd | Schottky barrier diode |
| JP2005229070A (en) * | 2004-02-16 | 2005-08-25 | Matsushita Electric Ind Co Ltd | Schottky barrier diode and manufacturing method therefor |
| CN106057912A (en) * | 2015-04-09 | 2016-10-26 | 丰田自动车株式会社 | Diode and method of manufacturing diode |
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Application publication date: 20200731 |